inc/abi/ckmmu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __ASM_CSKY_CKMMUV2_H
0004 #define __ASM_CSKY_CKMMUV2_H
0005
0006 #include <abi/reg_ops.h>
0007 #include <asm/barrier.h>
0008
0009 static inline int read_mmu_index(void)
0010 {
0011     return mfcr("cr<0, 15>");
0012 }
0013
0014 static inline void write_mmu_index(int value)
0015 {
0016     mtcr("cr<0, 15>", value);
0017 }
0018
0019 static inline int read_mmu_entrylo0(void)
0020 {
0021     return mfcr("cr<2, 15>");
0022 }
0023
0024 static inline int read_mmu_entrylo1(void)
0025 {
0026     return mfcr("cr<3, 15>");
0027 }
0028
0029 static inline void write_mmu_pagemask(int value)
0030 {
0031     mtcr("cr<6, 15>", value);
0032 }
0033
0034 static inline int read_mmu_entryhi(void)
0035 {
0036     return mfcr("cr<4, 15>");
0037 }
0038
0039 static inline void write_mmu_entryhi(int value)
0040 {
0041     mtcr("cr<4, 15>", value);
0042 }
0043
0044 static inline unsigned long read_mmu_msa0(void)
0045 {
0046     return mfcr("cr<30, 15>");
0047 }
0048
0049 static inline void write_mmu_msa0(unsigned long value)
0050 {
0051     mtcr("cr<30, 15>", value);
0052 }
0053
0054 static inline unsigned long read_mmu_msa1(void)
0055 {
0056     return mfcr("cr<31, 15>");
0057 }
0058
0059 static inline void write_mmu_msa1(unsigned long value)
0060 {
0061     mtcr("cr<31, 15>", value);
0062 }
0063
0064 /*
0065  * TLB operations.
0066  */
0067 static inline void tlb_probe(void)
0068 {
0069     mtcr("cr<8, 15>", 0x80000000);
0070 }
0071
0072 static inline void tlb_read(void)
0073 {
0074     mtcr("cr<8, 15>", 0x40000000);
0075 }
0076
0077 static inline void tlb_invalid_all(void)
0078 {
0079 #ifdef CONFIG_CPU_HAS_TLBI
0080     sync_is();
0081     asm volatile(
0082         "tlbi.alls  \n"
0083         "sync.i     \n"
0084         :
0085         :
0086         : "memory");
0087 #else
0088     mtcr("cr<8, 15>", 0x04000000);
0089 #endif
0090 }
0091
0092 static inline void local_tlb_invalid_all(void)
0093 {
0094 #ifdef CONFIG_CPU_HAS_TLBI
0095     sync_is();
0096     asm volatile(
0097         "tlbi.all   \n"
0098         "sync.i     \n"
0099         :
0100         :
0101         : "memory");
0102 #else
0103     tlb_invalid_all();
0104 #endif
0105 }
0106
0107 static inline void tlb_invalid_indexed(void)
0108 {
0109     mtcr("cr<8, 15>", 0x02000000);
0110 }
0111
0112 #define NOP32 ".long 0x4820c400\n"
0113
0114 static inline void setup_pgd(pgd_t *pgd, int asid)
0115 {
0116 #ifdef CONFIG_CPU_HAS_TLBI
0117     sync_is();
0118 #else
0119     mb();
0120 #endif
0121     asm volatile(
0122 #ifdef CONFIG_CPU_HAS_TLBI
0123         "mtcr %1, cr<28, 15>    \n"
0124 #endif
0125         "mtcr %1, cr<29, 15>    \n"
0126         "mtcr %0, cr< 4, 15>    \n"
0127         ".rept 64       \n"
0128         NOP32
0129         ".endr          \n"
0130         :
0131         :"r"(asid), "r"(__pa(pgd) | BIT(0))
0132         :"memory");
0133 }
0134
0135 static inline pgd_t *get_pgd(void)
0136 {
0137     return __va(mfcr("cr<29, 15>") & ~BIT(0));
0138 }
0139 #endif /* __ASM_CSKY_CKMMUV2_H */