csky/abiv2/cacheflush.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
0003
0004 #include <linux/cache.h>
0005 #include <linux/highmem.h>
0006 #include <linux/mm.h>
0007 #include <asm/cache.h>
0008
0009 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
0010               pte_t *pte)
0011 {
0012     unsigned long addr;
0013     struct page *page;
0014
0015     if (!pfn_valid(pte_pfn(*pte)))
0016         return;
0017
0018     page = pfn_to_page(pte_pfn(*pte));
0019     if (page == ZERO_PAGE(0))
0020         return;
0021
0022     if (test_and_set_bit(PG_dcache_clean, &page->flags))
0023         return;
0024
0025     addr = (unsigned long) kmap_atomic(page);
0026
0027     dcache_wb_range(addr, addr + PAGE_SIZE);
0028
0029     if (vma->vm_flags & VM_EXEC)
0030         icache_inv_range(addr, addr + PAGE_SIZE);
0031
0032     kunmap_atomic((void *) addr);
0033 }
0034
0035 void flush_icache_deferred(struct mm_struct *mm)
0036 {
0037     unsigned int cpu = smp_processor_id();
0038     cpumask_t *mask = &mm->context.icache_stale_mask;
0039
0040     if (cpumask_test_cpu(cpu, mask)) {
0041         cpumask_clear_cpu(cpu, mask);
0042         /*
0043          * Ensure the remote hart's writes are visible to this hart.
0044          * This pairs with a barrier in flush_icache_mm.
0045          */
0046         smp_mb();
0047         local_icache_inv_all(NULL);
0048     }
0049 }
0050
0051 void flush_icache_mm_range(struct mm_struct *mm,
0052         unsigned long start, unsigned long end)
0053 {
0054     unsigned int cpu;
0055     cpumask_t others, *mask;
0056
0057     preempt_disable();
0058
0059 #ifdef CONFIG_CPU_HAS_ICACHE_INS
0060     if (mm == current->mm) {
0061         icache_inv_range(start, end);
0062         preempt_enable();
0063         return;
0064     }
0065 #endif
0066
0067     /* Mark every hart's icache as needing a flush for this MM. */
0068     mask = &mm->context.icache_stale_mask;
0069     cpumask_setall(mask);
0070
0071     /* Flush this hart's I$ now, and mark it as flushed. */
0072     cpu = smp_processor_id();
0073     cpumask_clear_cpu(cpu, mask);
0074     local_icache_inv_all(NULL);
0075
0076     /*
0077      * Flush the I$ of other harts concurrently executing, and mark them as
0078      * flushed.
0079      */
0080     cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
0081
0082     if (mm != current->active_mm || !cpumask_empty(&others)) {
0083         on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
0084         cpumask_clear(mask);
0085     }
0086
0087     preempt_enable();
0088 }