inc/abi/entry.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __ASM_CSKY_ENTRY_H
0004 #define __ASM_CSKY_ENTRY_H
0005
0006 #include <asm/setup.h>
0007 #include <abi/regdef.h>
0008
0009 #define LSAVE_PC    8
0010 #define LSAVE_PSR   12
0011 #define LSAVE_A0    24
0012 #define LSAVE_A1    28
0013 #define LSAVE_A2    32
0014 #define LSAVE_A3    36
0015 #define LSAVE_A4    40
0016 #define LSAVE_A5    44
0017
0018 #define usp ss1
0019
0020 .macro USPTOKSP
0021     mtcr    sp, usp
0022     mfcr    sp, ss0
0023 .endm
0024
0025 .macro KSPTOUSP
0026     mtcr    sp, ss0
0027     mfcr    sp, usp
0028 .endm
0029
0030 .macro  SAVE_ALL epc_inc
0031     mtcr    r13, ss2
0032     mfcr    r13, epsr
0033     btsti   r13, 31
0034     bt      1f
0035     USPTOKSP
0036 1:
0037     subi    sp, 32
0038     subi    sp, 32
0039     subi    sp, 16
0040     stw     r13, (sp, 12)
0041
0042     stw     lr, (sp, 4)
0043
0044     mfcr    lr, epc
0045     movi    r13, \epc_inc
0046     add lr, r13
0047     stw     lr, (sp, 8)
0048
0049     mov lr, sp
0050     addi    lr, 32
0051     addi    lr, 32
0052     addi    lr, 16
0053     bt  2f
0054     mfcr    lr, ss1
0055 2:
0056     stw     lr, (sp, 16)
0057
0058     stw     a0, (sp, 20)
0059     stw     a0, (sp, 24)
0060     stw     a1, (sp, 28)
0061     stw     a2, (sp, 32)
0062     stw     a3, (sp, 36)
0063
0064     addi    sp, 32
0065     addi    sp, 8
0066     mfcr    r13, ss2
0067     stw r6, (sp)
0068     stw r7, (sp, 4)
0069     stw r8, (sp, 8)
0070     stw r9, (sp, 12)
0071     stw r10, (sp, 16)
0072     stw r11, (sp, 20)
0073     stw r12, (sp, 24)
0074     stw r13, (sp, 28)
0075     stw r14, (sp, 32)
0076     stw r1, (sp, 36)
0077     subi    sp, 32
0078     subi    sp, 8
0079 .endm
0080
0081 .macro  RESTORE_ALL
0082     ldw lr, (sp, 4)
0083     ldw     a0, (sp, 8)
0084     mtcr    a0, epc
0085     ldw     a0, (sp, 12)
0086     mtcr    a0, epsr
0087     btsti   a0, 31
0088     bt      1f
0089     ldw     a0, (sp, 16)
0090     mtcr    a0, ss1
0091 1:
0092     ldw     a0, (sp, 24)
0093     ldw     a1, (sp, 28)
0094     ldw     a2, (sp, 32)
0095     ldw     a3, (sp, 36)
0096
0097     addi    sp, 32
0098     addi    sp, 8
0099     ldw r6, (sp)
0100     ldw r7, (sp, 4)
0101     ldw r8, (sp, 8)
0102     ldw r9, (sp, 12)
0103     ldw r10, (sp, 16)
0104     ldw r11, (sp, 20)
0105     ldw r12, (sp, 24)
0106     ldw r13, (sp, 28)
0107     ldw r14, (sp, 32)
0108     ldw r1, (sp, 36)
0109     addi    sp, 32
0110     addi    sp, 8
0111
0112     bt      2f
0113     KSPTOUSP
0114 2:
0115     rte
0116 .endm
0117
0118 .macro SAVE_SWITCH_STACK
0119     subi    sp, 32
0120     stm     r8-r15, (sp)
0121 .endm
0122
0123 .macro RESTORE_SWITCH_STACK
0124     ldm     r8-r15, (sp)
0125     addi    sp, 32
0126 .endm
0127
0128 /* MMU registers operators. */
0129 .macro RD_MIR   rx
0130     cprcr   \rx, cpcr0
0131 .endm
0132
0133 .macro RD_MEH   rx
0134     cprcr   \rx, cpcr4
0135 .endm
0136
0137 .macro RD_MCIR  rx
0138     cprcr   \rx, cpcr8
0139 .endm
0140
0141 .macro RD_PGDR  rx
0142     cprcr   \rx, cpcr29
0143 .endm
0144
0145 .macro WR_MEH   rx
0146     cpwcr   \rx, cpcr4
0147 .endm
0148
0149 .macro WR_MCIR  rx
0150     cpwcr   \rx, cpcr8
0151 .endm
0152
0153 .macro SETUP_MMU
0154     /* Init psr and enable ee */
0155     lrw r6, DEFAULT_PSR_VALUE
0156     mtcr    r6, psr
0157     psrset  ee
0158
0159     /* Select MMU as co-processor */
0160     cpseti  cp15
0161
0162     /*
0163      * cpcr30 format:
0164      * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0
0165      *   BA     Reserved  C   D   V
0166      */
0167     cprcr   r6, cpcr30
0168     lsri    r6, 29
0169     lsli    r6, 29
0170     addi    r6, 0xe
0171     cpwcr   r6, cpcr30
0172
0173     movi    r6, 0
0174     cpwcr   r6, cpcr31
0175 .endm
0176 #endif /* __ASM_CSKY_ENTRY_H */