arm64/mm/context.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Based on arch/arm/mm/context.c
0004  *
0005  * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved.
0006  * Copyright (C) 2012 ARM Ltd.
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/bitops.h>
0011 #include <linux/sched.h>
0012 #include <linux/slab.h>
0013 #include <linux/mm.h>
0014
0015 #include <asm/cpufeature.h>
0016 #include <asm/mmu_context.h>
0017 #include <asm/smp.h>
0018 #include <asm/tlbflush.h>
0019
0020 static u32 asid_bits;
0021 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
0022
0023 static atomic64_t asid_generation;
0024 static unsigned long *asid_map;
0025
0026 static DEFINE_PER_CPU(atomic64_t, active_asids);
0027 static DEFINE_PER_CPU(u64, reserved_asids);
0028 static cpumask_t tlb_flush_pending;
0029
0030 static unsigned long max_pinned_asids;
0031 static unsigned long nr_pinned_asids;
0032 static unsigned long *pinned_asid_map;
0033
0034 #define ASID_MASK       (~GENMASK(asid_bits - 1, 0))
0035 #define ASID_FIRST_VERSION  (1UL << asid_bits)
0036
0037 #define NUM_USER_ASIDS      ASID_FIRST_VERSION
0038 #define ctxid2asid(asid)    ((asid) & ~ASID_MASK)
0039 #define asid2ctxid(asid, genid) ((asid) | (genid))
0040
0041 /* Get the ASIDBits supported by the current CPU */
0042 static u32 get_cpu_asid_bits(void)
0043 {
0044     u32 asid;
0045     int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
0046                         ID_AA64MMFR0_ASID_SHIFT);
0047
0048     switch (fld) {
0049     default:
0050         pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
0051                     smp_processor_id(),  fld);
0052         fallthrough;
0053     case ID_AA64MMFR0_ASID_8:
0054         asid = 8;
0055         break;
0056     case ID_AA64MMFR0_ASID_16:
0057         asid = 16;
0058     }
0059
0060     return asid;
0061 }
0062
0063 /* Check if the current cpu's ASIDBits is compatible with asid_bits */
0064 void verify_cpu_asid_bits(void)
0065 {
0066     u32 asid = get_cpu_asid_bits();
0067
0068     if (asid < asid_bits) {
0069         /*
0070          * We cannot decrease the ASID size at runtime, so panic if we support
0071          * fewer ASID bits than the boot CPU.
0072          */
0073         pr_crit("CPU%d: smaller ASID size(%u) than boot CPU (%u)\n",
0074                 smp_processor_id(), asid, asid_bits);
0075         cpu_panic_kernel();
0076     }
0077 }
0078
0079 static void set_kpti_asid_bits(unsigned long *map)
0080 {
0081     unsigned int len = BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(unsigned long);
0082     /*
0083      * In case of KPTI kernel/user ASIDs are allocated in
0084      * pairs, the bottom bit distinguishes the two: if it
0085      * is set, then the ASID will map only userspace. Thus
0086      * mark even as reserved for kernel.
0087      */
0088     memset(map, 0xaa, len);
0089 }
0090
0091 static void set_reserved_asid_bits(void)
0092 {
0093     if (pinned_asid_map)
0094         bitmap_copy(asid_map, pinned_asid_map, NUM_USER_ASIDS);
0095     else if (arm64_kernel_unmapped_at_el0())
0096         set_kpti_asid_bits(asid_map);
0097     else
0098         bitmap_clear(asid_map, 0, NUM_USER_ASIDS);
0099 }
0100
0101 #define asid_gen_match(asid) \
0102     (!(((asid) ^ atomic64_read(&asid_generation)) >> asid_bits))
0103
0104 static void flush_context(void)
0105 {
0106     int i;
0107     u64 asid;
0108
0109     /* Update the list of reserved ASIDs and the ASID bitmap. */
0110     set_reserved_asid_bits();
0111
0112     for_each_possible_cpu(i) {
0113         asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0);
0114         /*
0115          * If this CPU has already been through a
0116          * rollover, but hasn't run another task in
0117          * the meantime, we must preserve its reserved
0118          * ASID, as this is the only trace we have of
0119          * the process it is still running.
0120          */
0121         if (asid == 0)
0122             asid = per_cpu(reserved_asids, i);
0123         __set_bit(ctxid2asid(asid), asid_map);
0124         per_cpu(reserved_asids, i) = asid;
0125     }
0126
0127     /*
0128      * Queue a TLB invalidation for each CPU to perform on next
0129      * context-switch
0130      */
0131     cpumask_setall(&tlb_flush_pending);
0132 }
0133
0134 static bool check_update_reserved_asid(u64 asid, u64 newasid)
0135 {
0136     int cpu;
0137     bool hit = false;
0138
0139     /*
0140      * Iterate over the set of reserved ASIDs looking for a match.
0141      * If we find one, then we can update our mm to use newasid
0142      * (i.e. the same ASID in the current generation) but we can't
0143      * exit the loop early, since we need to ensure that all copies
0144      * of the old ASID are updated to reflect the mm. Failure to do
0145      * so could result in us missing the reserved ASID in a future
0146      * generation.
0147      */
0148     for_each_possible_cpu(cpu) {
0149         if (per_cpu(reserved_asids, cpu) == asid) {
0150             hit = true;
0151             per_cpu(reserved_asids, cpu) = newasid;
0152         }
0153     }
0154
0155     return hit;
0156 }
0157
0158 static u64 new_context(struct mm_struct *mm)
0159 {
0160     static u32 cur_idx = 1;
0161     u64 asid = atomic64_read(&mm->context.id);
0162     u64 generation = atomic64_read(&asid_generation);
0163
0164     if (asid != 0) {
0165         u64 newasid = asid2ctxid(ctxid2asid(asid), generation);
0166
0167         /*
0168          * If our current ASID was active during a rollover, we
0169          * can continue to use it and this was just a false alarm.
0170          */
0171         if (check_update_reserved_asid(asid, newasid))
0172             return newasid;
0173
0174         /*
0175          * If it is pinned, we can keep using it. Note that reserved
0176          * takes priority, because even if it is also pinned, we need to
0177          * update the generation into the reserved_asids.
0178          */
0179         if (refcount_read(&mm->context.pinned))
0180             return newasid;
0181
0182         /*
0183          * We had a valid ASID in a previous life, so try to re-use
0184          * it if possible.
0185          */
0186         if (!__test_and_set_bit(ctxid2asid(asid), asid_map))
0187             return newasid;
0188     }
0189
0190     /*
0191      * Allocate a free ASID. If we can't find one, take a note of the
0192      * currently active ASIDs and mark the TLBs as requiring flushes.  We
0193      * always count from ASID #2 (index 1), as we use ASID #0 when setting
0194      * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd
0195      * pairs.
0196      */
0197     asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx);
0198     if (asid != NUM_USER_ASIDS)
0199         goto set_asid;
0200
0201     /* We're out of ASIDs, so increment the global generation count */
0202     generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION,
0203                          &asid_generation);
0204     flush_context();
0205
0206     /* We have more ASIDs than CPUs, so this will always succeed */
0207     asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
0208
0209 set_asid:
0210     __set_bit(asid, asid_map);
0211     cur_idx = asid;
0212     return asid2ctxid(asid, generation);
0213 }
0214
0215 void check_and_switch_context(struct mm_struct *mm)
0216 {
0217     unsigned long flags;
0218     unsigned int cpu;
0219     u64 asid, old_active_asid;
0220
0221     if (system_supports_cnp())
0222         cpu_set_reserved_ttbr0();
0223
0224     asid = atomic64_read(&mm->context.id);
0225
0226     /*
0227      * The memory ordering here is subtle.
0228      * If our active_asids is non-zero and the ASID matches the current
0229      * generation, then we update the active_asids entry with a relaxed
0230      * cmpxchg. Racing with a concurrent rollover means that either:
0231      *
0232      * - We get a zero back from the cmpxchg and end up waiting on the
0233      *   lock. Taking the lock synchronises with the rollover and so
0234      *   we are forced to see the updated generation.
0235      *
0236      * - We get a valid ASID back from the cmpxchg, which means the
0237      *   relaxed xchg in flush_context will treat us as reserved
0238      *   because atomic RmWs are totally ordered for a given location.
0239      */
0240     old_active_asid = atomic64_read(this_cpu_ptr(&active_asids));
0241     if (old_active_asid && asid_gen_match(asid) &&
0242         atomic64_cmpxchg_relaxed(this_cpu_ptr(&active_asids),
0243                      old_active_asid, asid))
0244         goto switch_mm_fastpath;
0245
0246     raw_spin_lock_irqsave(&cpu_asid_lock, flags);
0247     /* Check that our ASID belongs to the current generation. */
0248     asid = atomic64_read(&mm->context.id);
0249     if (!asid_gen_match(asid)) {
0250         asid = new_context(mm);
0251         atomic64_set(&mm->context.id, asid);
0252     }
0253
0254     cpu = smp_processor_id();
0255     if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
0256         local_flush_tlb_all();
0257
0258     atomic64_set(this_cpu_ptr(&active_asids), asid);
0259     raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
0260
0261 switch_mm_fastpath:
0262
0263     arm64_apply_bp_hardening();
0264
0265     /*
0266      * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
0267      * emulating PAN.
0268      */
0269     if (!system_uses_ttbr0_pan())
0270         cpu_switch_mm(mm->pgd, mm);
0271 }
0272
0273 unsigned long arm64_mm_context_get(struct mm_struct *mm)
0274 {
0275     unsigned long flags;
0276     u64 asid;
0277
0278     if (!pinned_asid_map)
0279         return 0;
0280
0281     raw_spin_lock_irqsave(&cpu_asid_lock, flags);
0282
0283     asid = atomic64_read(&mm->context.id);
0284
0285     if (refcount_inc_not_zero(&mm->context.pinned))
0286         goto out_unlock;
0287
0288     if (nr_pinned_asids >= max_pinned_asids) {
0289         asid = 0;
0290         goto out_unlock;
0291     }
0292
0293     if (!asid_gen_match(asid)) {
0294         /*
0295          * We went through one or more rollover since that ASID was
0296          * used. Ensure that it is still valid, or generate a new one.
0297          */
0298         asid = new_context(mm);
0299         atomic64_set(&mm->context.id, asid);
0300     }
0301
0302     nr_pinned_asids++;
0303     __set_bit(ctxid2asid(asid), pinned_asid_map);
0304     refcount_set(&mm->context.pinned, 1);
0305
0306 out_unlock:
0307     raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
0308
0309     asid = ctxid2asid(asid);
0310
0311     /* Set the equivalent of USER_ASID_BIT */
0312     if (asid && arm64_kernel_unmapped_at_el0())
0313         asid |= 1;
0314
0315     return asid;
0316 }
0317 EXPORT_SYMBOL_GPL(arm64_mm_context_get);
0318
0319 void arm64_mm_context_put(struct mm_struct *mm)
0320 {
0321     unsigned long flags;
0322     u64 asid = atomic64_read(&mm->context.id);
0323
0324     if (!pinned_asid_map)
0325         return;
0326
0327     raw_spin_lock_irqsave(&cpu_asid_lock, flags);
0328
0329     if (refcount_dec_and_test(&mm->context.pinned)) {
0330         __clear_bit(ctxid2asid(asid), pinned_asid_map);
0331         nr_pinned_asids--;
0332     }
0333
0334     raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
0335 }
0336 EXPORT_SYMBOL_GPL(arm64_mm_context_put);
0337
0338 /* Errata workaround post TTBRx_EL1 update. */
0339 asmlinkage void post_ttbr_update_workaround(void)
0340 {
0341     if (!IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456))
0342         return;
0343
0344     asm(ALTERNATIVE("nop; nop; nop",
0345             "ic iallu; dsb nsh; isb",
0346             ARM64_WORKAROUND_CAVIUM_27456));
0347 }
0348
0349 void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
0350 {
0351     unsigned long ttbr1 = read_sysreg(ttbr1_el1);
0352     unsigned long asid = ASID(mm);
0353     unsigned long ttbr0 = phys_to_ttbr(pgd_phys);
0354
0355     /* Skip CNP for the reserved ASID */
0356     if (system_supports_cnp() && asid)
0357         ttbr0 |= TTBR_CNP_BIT;
0358
0359     /* SW PAN needs a copy of the ASID in TTBR0 for entry */
0360     if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN))
0361         ttbr0 |= FIELD_PREP(TTBR_ASID_MASK, asid);
0362
0363     /* Set ASID in TTBR1 since TCR.A1 is set */
0364     ttbr1 &= ~TTBR_ASID_MASK;
0365     ttbr1 |= FIELD_PREP(TTBR_ASID_MASK, asid);
0366
0367     write_sysreg(ttbr1, ttbr1_el1);
0368     isb();
0369     write_sysreg(ttbr0, ttbr0_el1);
0370     isb();
0371     post_ttbr_update_workaround();
0372 }
0373
0374 static int asids_update_limit(void)
0375 {
0376     unsigned long num_available_asids = NUM_USER_ASIDS;
0377
0378     if (arm64_kernel_unmapped_at_el0()) {
0379         num_available_asids /= 2;
0380         if (pinned_asid_map)
0381             set_kpti_asid_bits(pinned_asid_map);
0382     }
0383     /*
0384      * Expect allocation after rollover to fail if we don't have at least
0385      * one more ASID than CPUs. ASID #0 is reserved for init_mm.
0386      */
0387     WARN_ON(num_available_asids - 1 <= num_possible_cpus());
0388     pr_info("ASID allocator initialised with %lu entries\n",
0389         num_available_asids);
0390
0391     /*
0392      * There must always be an ASID available after rollover. Ensure that,
0393      * even if all CPUs have a reserved ASID and the maximum number of ASIDs
0394      * are pinned, there still is at least one empty slot in the ASID map.
0395      */
0396     max_pinned_asids = num_available_asids - num_possible_cpus() - 2;
0397     return 0;
0398 }
0399 arch_initcall(asids_update_limit);
0400
0401 static int asids_init(void)
0402 {
0403     asid_bits = get_cpu_asid_bits();
0404     atomic64_set(&asid_generation, ASID_FIRST_VERSION);
0405     asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL);
0406     if (!asid_map)
0407         panic("Failed to allocate bitmap for %lu ASIDs\n",
0408               NUM_USER_ASIDS);
0409
0410     pinned_asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL);
0411     nr_pinned_asids = 0;
0412
0413     /*
0414      * We cannot call set_reserved_asid_bits() here because CPU
0415      * caps are not finalized yet, so it is safer to assume KPTI
0416      * and reserve kernel ASID's from beginning.
0417      */
0418     if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0))
0419         set_kpti_asid_bits(asid_map);
0420     return 0;
0421 }
0422 early_initcall(asids_init);