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0009 #include <linux/kvm_host.h>
0010 #include <linux/hw_breakpoint.h>
0011
0012 #include <asm/debug-monitors.h>
0013 #include <asm/kvm_asm.h>
0014 #include <asm/kvm_arm.h>
0015 #include <asm/kvm_emulate.h>
0016
0017 #include "trace.h"
0018
0019
0020 #define MDSCR_EL1_DEBUG_MASK (DBG_MDSCR_SS | \
0021 DBG_MDSCR_KDE | \
0022 DBG_MDSCR_MDE)
0023
0024 static DEFINE_PER_CPU(u64, mdcr_el2);
0025
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0034
0035
0036 static void save_guest_debug_regs(struct kvm_vcpu *vcpu)
0037 {
0038 u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
0039
0040 vcpu->arch.guest_debug_preserved.mdscr_el1 = val;
0041
0042 trace_kvm_arm_set_dreg32("Saved MDSCR_EL1",
0043 vcpu->arch.guest_debug_preserved.mdscr_el1);
0044 }
0045
0046 static void restore_guest_debug_regs(struct kvm_vcpu *vcpu)
0047 {
0048 u64 val = vcpu->arch.guest_debug_preserved.mdscr_el1;
0049
0050 vcpu_write_sys_reg(vcpu, val, MDSCR_EL1);
0051
0052 trace_kvm_arm_set_dreg32("Restored MDSCR_EL1",
0053 vcpu_read_sys_reg(vcpu, MDSCR_EL1));
0054 }
0055
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0057
0058
0059
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0061
0062
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0064
0065
0066 void kvm_arm_init_debug(void)
0067 {
0068 __this_cpu_write(mdcr_el2, kvm_call_hyp_ret(__kvm_get_mdcr_el2));
0069 }
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0071
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0082
0083
0084 static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu)
0085 {
0086
0087
0088
0089
0090 vcpu->arch.mdcr_el2 = __this_cpu_read(mdcr_el2) & MDCR_EL2_HPMN_MASK;
0091 vcpu->arch.mdcr_el2 |= (MDCR_EL2_TPM |
0092 MDCR_EL2_TPMS |
0093 MDCR_EL2_TTRF |
0094 MDCR_EL2_TPMCR |
0095 MDCR_EL2_TDRA |
0096 MDCR_EL2_TDOSA);
0097
0098
0099 if (vcpu->guest_debug)
0100
0101 vcpu->arch.mdcr_el2 |= MDCR_EL2_TDE;
0102
0103
0104
0105
0106
0107
0108
0109
0110 if ((vcpu->guest_debug & KVM_GUESTDBG_USE_HW) ||
0111 !vcpu_get_flag(vcpu, DEBUG_DIRTY) ||
0112 kvm_vcpu_os_lock_enabled(vcpu))
0113 vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA;
0114
0115 trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2);
0116 }
0117
0118
0119
0120
0121
0122
0123
0124
0125 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu)
0126 {
0127 preempt_disable();
0128 kvm_arm_setup_mdcr_el2(vcpu);
0129 preempt_enable();
0130 }
0131
0132
0133
0134
0135
0136 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu)
0137 {
0138 vcpu->arch.debug_ptr = &vcpu->arch.vcpu_debug_state;
0139 }
0140
0141
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0156
0157 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
0158 {
0159 unsigned long mdscr, orig_mdcr_el2 = vcpu->arch.mdcr_el2;
0160
0161 trace_kvm_arm_setup_debug(vcpu, vcpu->guest_debug);
0162
0163 kvm_arm_setup_mdcr_el2(vcpu);
0164
0165
0166 if (vcpu->guest_debug || kvm_vcpu_os_lock_enabled(vcpu)) {
0167
0168 save_guest_debug_regs(vcpu);
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0190 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
0191 *vcpu_cpsr(vcpu) |= DBG_SPSR_SS;
0192 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
0193 mdscr |= DBG_MDSCR_SS;
0194 vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
0195 } else {
0196 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
0197 mdscr &= ~DBG_MDSCR_SS;
0198 vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
0199 }
0200
0201 trace_kvm_arm_set_dreg32("SPSR_EL2", *vcpu_cpsr(vcpu));
0202
0203
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0210
0211 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
0212
0213 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
0214 mdscr |= DBG_MDSCR_MDE;
0215 vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
0216
0217 vcpu->arch.debug_ptr = &vcpu->arch.external_debug_state;
0218 vcpu_set_flag(vcpu, DEBUG_DIRTY);
0219
0220 trace_kvm_arm_set_regset("BKPTS", get_num_brps(),
0221 &vcpu->arch.debug_ptr->dbg_bcr[0],
0222 &vcpu->arch.debug_ptr->dbg_bvr[0]);
0223
0224 trace_kvm_arm_set_regset("WAPTS", get_num_wrps(),
0225 &vcpu->arch.debug_ptr->dbg_wcr[0],
0226 &vcpu->arch.debug_ptr->dbg_wvr[0]);
0227
0228
0229
0230
0231
0232
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0234
0235
0236 } else if (kvm_vcpu_os_lock_enabled(vcpu)) {
0237 mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);
0238 mdscr &= ~DBG_MDSCR_MDE;
0239 vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);
0240 }
0241 }
0242
0243 BUG_ON(!vcpu->guest_debug &&
0244 vcpu->arch.debug_ptr != &vcpu->arch.vcpu_debug_state);
0245
0246
0247 if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE))
0248 vcpu_set_flag(vcpu, DEBUG_DIRTY);
0249
0250
0251 if (has_vhe() && orig_mdcr_el2 != vcpu->arch.mdcr_el2)
0252 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
0253
0254 trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1));
0255 }
0256
0257 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu)
0258 {
0259 trace_kvm_arm_clear_debug(vcpu->guest_debug);
0260
0261
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0263
0264 if (vcpu->guest_debug || kvm_vcpu_os_lock_enabled(vcpu)) {
0265 restore_guest_debug_regs(vcpu);
0266
0267
0268
0269
0270
0271 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
0272 kvm_arm_reset_debug_ptr(vcpu);
0273
0274 trace_kvm_arm_set_regset("BKPTS", get_num_brps(),
0275 &vcpu->arch.debug_ptr->dbg_bcr[0],
0276 &vcpu->arch.debug_ptr->dbg_bvr[0]);
0277
0278 trace_kvm_arm_set_regset("WAPTS", get_num_wrps(),
0279 &vcpu->arch.debug_ptr->dbg_wcr[0],
0280 &vcpu->arch.debug_ptr->dbg_wvr[0]);
0281 }
0282 }
0283 }
0284
0285 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu)
0286 {
0287 u64 dfr0;
0288
0289
0290 if (has_vhe())
0291 return;
0292
0293 dfr0 = read_sysreg(id_aa64dfr0_el1);
0294
0295
0296
0297
0298 if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_PMSVER_SHIFT) &&
0299 !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT)))
0300 vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE);
0301
0302
0303 if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRBE_SHIFT) &&
0304 !(read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_PROG))
0305 vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_TRBE);
0306 }
0307
0308 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu)
0309 {
0310 vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_SPE);
0311 vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE);
0312 }