arm64/kernel/smp_spin_table.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Spin Table SMP initialisation
0004  *
0005  * Copyright (C) 2013 ARM Ltd.
0006  */
0007
0008 #include <linux/delay.h>
0009 #include <linux/init.h>
0010 #include <linux/of.h>
0011 #include <linux/smp.h>
0012 #include <linux/types.h>
0013 #include <linux/mm.h>
0014
0015 #include <asm/cacheflush.h>
0016 #include <asm/cpu_ops.h>
0017 #include <asm/cputype.h>
0018 #include <asm/io.h>
0019 #include <asm/smp_plat.h>
0020
0021 extern void secondary_holding_pen(void);
0022 volatile unsigned long __section(".mmuoff.data.read")
0023 secondary_holding_pen_release = INVALID_HWID;
0024
0025 static phys_addr_t cpu_release_addr[NR_CPUS];
0026
0027 /*
0028  * Write secondary_holding_pen_release in a way that is guaranteed to be
0029  * visible to all observers, irrespective of whether they're taking part
0030  * in coherency or not.  This is necessary for the hotplug code to work
0031  * reliably.
0032  */
0033 static void write_pen_release(u64 val)
0034 {
0035     void *start = (void *)&secondary_holding_pen_release;
0036     unsigned long size = sizeof(secondary_holding_pen_release);
0037
0038     secondary_holding_pen_release = val;
0039     dcache_clean_inval_poc((unsigned long)start, (unsigned long)start + size);
0040 }
0041
0042
0043 static int smp_spin_table_cpu_init(unsigned int cpu)
0044 {
0045     struct device_node *dn;
0046     int ret;
0047
0048     dn = of_get_cpu_node(cpu, NULL);
0049     if (!dn)
0050         return -ENODEV;
0051
0052     /*
0053      * Determine the address from which the CPU is polling.
0054      */
0055     ret = of_property_read_u64(dn, "cpu-release-addr",
0056                    &cpu_release_addr[cpu]);
0057     if (ret)
0058         pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
0059                cpu);
0060
0061     of_node_put(dn);
0062
0063     return ret;
0064 }
0065
0066 static int smp_spin_table_cpu_prepare(unsigned int cpu)
0067 {
0068     __le64 __iomem *release_addr;
0069     phys_addr_t pa_holding_pen = __pa_symbol(function_nocfi(secondary_holding_pen));
0070
0071     if (!cpu_release_addr[cpu])
0072         return -ENODEV;
0073
0074     /*
0075      * The cpu-release-addr may or may not be inside the linear mapping.
0076      * As ioremap_cache will either give us a new mapping or reuse the
0077      * existing linear mapping, we can use it to cover both cases. In
0078      * either case the memory will be MT_NORMAL.
0079      */
0080     release_addr = ioremap_cache(cpu_release_addr[cpu],
0081                      sizeof(*release_addr));
0082     if (!release_addr)
0083         return -ENOMEM;
0084
0085     /*
0086      * We write the release address as LE regardless of the native
0087      * endianness of the kernel. Therefore, any boot-loaders that
0088      * read this address need to convert this address to the
0089      * boot-loader's endianness before jumping. This is mandated by
0090      * the boot protocol.
0091      */
0092     writeq_relaxed(pa_holding_pen, release_addr);
0093     dcache_clean_inval_poc((__force unsigned long)release_addr,
0094                 (__force unsigned long)release_addr +
0095                     sizeof(*release_addr));
0096
0097     /*
0098      * Send an event to wake up the secondary CPU.
0099      */
0100     sev();
0101
0102     iounmap(release_addr);
0103
0104     return 0;
0105 }
0106
0107 static int smp_spin_table_cpu_boot(unsigned int cpu)
0108 {
0109     /*
0110      * Update the pen release flag.
0111      */
0112     write_pen_release(cpu_logical_map(cpu));
0113
0114     /*
0115      * Send an event, causing the secondaries to read pen_release.
0116      */
0117     sev();
0118
0119     return 0;
0120 }
0121
0122 const struct cpu_operations smp_spin_table_ops = {
0123     .name       = "spin-table",
0124     .cpu_init   = smp_spin_table_cpu_init,
0125     .cpu_prepare    = smp_spin_table_cpu_prepare,
0126     .cpu_boot   = smp_spin_table_cpu_boot,
0127 };