arm64/kernel/smccc-call.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015, Linaro Limited
0004  */
0005 #include <linux/linkage.h>
0006 #include <linux/arm-smccc.h>
0007
0008 #include <asm/asm-offsets.h>
0009 #include <asm/assembler.h>
0010 #include <asm/thread_info.h>
0011
0012 /*
0013  * If we have SMCCC v1.3 and (as is likely) no SVE state in
0014  * the registers then set the SMCCC hint bit to say there's no
0015  * need to preserve it.  Do this by directly adjusting the SMCCC
0016  * function value which is already stored in x0 ready to be called.
0017  */
0018 SYM_FUNC_START(__arm_smccc_sve_check)
0019
0020     ldr_l   x16, smccc_has_sve_hint
0021     cbz x16, 2f
0022
0023     get_current_task x16
0024     ldr x16, [x16, #TSK_TI_FLAGS]
0025     tbnz    x16, #TIF_FOREIGN_FPSTATE, 1f   // Any live FP state?
0026     tbnz    x16, #TIF_SVE, 2f       // Does that state include SVE?
0027
0028 1:  orr x0, x0, ARM_SMCCC_1_3_SVE_HINT
0029
0030 2:  ret
0031 SYM_FUNC_END(__arm_smccc_sve_check)
0032 EXPORT_SYMBOL(__arm_smccc_sve_check)
0033
0034     .macro SMCCC instr
0035     stp     x29, x30, [sp, #-16]!
0036     mov x29, sp
0037 alternative_if ARM64_SVE
0038     bl  __arm_smccc_sve_check
0039 alternative_else_nop_endif
0040     \instr  #0
0041     ldr x4, [sp, #16]
0042     stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
0043     stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
0044     ldr x4, [sp, #24]
0045     cbz x4, 1f /* no quirk structure */
0046     ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
0047     cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
0048     b.ne    1f
0049     str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
0050 1:  ldp     x29, x30, [sp], #16
0051     ret
0052     .endm
0053
0054 /*
0055  * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
0056  *        unsigned long a3, unsigned long a4, unsigned long a5,
0057  *        unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
0058  *        struct arm_smccc_quirk *quirk)
0059  */
0060 SYM_FUNC_START(__arm_smccc_smc)
0061     SMCCC   smc
0062 SYM_FUNC_END(__arm_smccc_smc)
0063 EXPORT_SYMBOL(__arm_smccc_smc)
0064
0065 /*
0066  * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
0067  *        unsigned long a3, unsigned long a4, unsigned long a5,
0068  *        unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
0069  *        struct arm_smccc_quirk *quirk)
0070  */
0071 SYM_FUNC_START(__arm_smccc_hvc)
0072     SMCCC   hvc
0073 SYM_FUNC_END(__arm_smccc_hvc)
0074 EXPORT_SYMBOL(__arm_smccc_hvc)
0075
0076     .macro SMCCC_1_2 instr
0077     /* Save `res` and free a GPR that won't be clobbered */
0078     stp     x1, x19, [sp, #-16]!
0079
0080     /* Ensure `args` won't be clobbered while loading regs in next step */
0081     mov x19, x0
0082
0083     /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
0084     ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
0085     ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
0086     ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
0087     ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
0088     ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
0089     ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
0090     ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
0091     ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
0092     ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
0093
0094     \instr #0
0095
0096     /* Load the `res` from the stack */
0097     ldr x19, [sp]
0098
0099     /* Store the registers x0 - x17 into the result structure */
0100     stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
0101     stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
0102     stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
0103     stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
0104     stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
0105     stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
0106     stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
0107     stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
0108     stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
0109
0110     /* Restore original x19 */
0111     ldp     xzr, x19, [sp], #16
0112     ret
0113 .endm
0114
0115 /*
0116  * void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,
0117  *            struct arm_smccc_1_2_regs *res);
0118  */
0119 SYM_FUNC_START(arm_smccc_1_2_hvc)
0120     SMCCC_1_2 hvc
0121 SYM_FUNC_END(arm_smccc_1_2_hvc)
0122 EXPORT_SYMBOL(arm_smccc_1_2_hvc)
0123
0124 /*
0125  * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
0126  *            struct arm_smccc_1_2_regs *res);
0127  */
0128 SYM_FUNC_START(arm_smccc_1_2_smc)
0129     SMCCC_1_2 smc
0130 SYM_FUNC_END(arm_smccc_1_2_smc)
0131 EXPORT_SYMBOL(arm_smccc_1_2_smc)