arm64/kernel/setup.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Based on arch/arm/kernel/setup.c
0004  *
0005  * Copyright (C) 1995-2001 Russell King
0006  * Copyright (C) 2012 ARM Ltd.
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <linux/export.h>
0011 #include <linux/kernel.h>
0012 #include <linux/stddef.h>
0013 #include <linux/ioport.h>
0014 #include <linux/delay.h>
0015 #include <linux/initrd.h>
0016 #include <linux/console.h>
0017 #include <linux/cache.h>
0018 #include <linux/screen_info.h>
0019 #include <linux/init.h>
0020 #include <linux/kexec.h>
0021 #include <linux/root_dev.h>
0022 #include <linux/cpu.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/smp.h>
0025 #include <linux/fs.h>
0026 #include <linux/panic_notifier.h>
0027 #include <linux/proc_fs.h>
0028 #include <linux/memblock.h>
0029 #include <linux/of_fdt.h>
0030 #include <linux/efi.h>
0031 #include <linux/psci.h>
0032 #include <linux/sched/task.h>
0033 #include <linux/mm.h>
0034
0035 #include <asm/acpi.h>
0036 #include <asm/fixmap.h>
0037 #include <asm/cpu.h>
0038 #include <asm/cputype.h>
0039 #include <asm/daifflags.h>
0040 #include <asm/elf.h>
0041 #include <asm/cpufeature.h>
0042 #include <asm/cpu_ops.h>
0043 #include <asm/kasan.h>
0044 #include <asm/numa.h>
0045 #include <asm/sections.h>
0046 #include <asm/setup.h>
0047 #include <asm/smp_plat.h>
0048 #include <asm/cacheflush.h>
0049 #include <asm/tlbflush.h>
0050 #include <asm/traps.h>
0051 #include <asm/efi.h>
0052 #include <asm/xen/hypervisor.h>
0053 #include <asm/mmu_context.h>
0054
0055 static int num_standard_resources;
0056 static struct resource *standard_resources;
0057
0058 phys_addr_t __fdt_pointer __initdata;
0059
0060 /*
0061  * Standard memory resources
0062  */
0063 static struct resource mem_res[] = {
0064     {
0065         .name = "Kernel code",
0066         .start = 0,
0067         .end = 0,
0068         .flags = IORESOURCE_SYSTEM_RAM
0069     },
0070     {
0071         .name = "Kernel data",
0072         .start = 0,
0073         .end = 0,
0074         .flags = IORESOURCE_SYSTEM_RAM
0075     }
0076 };
0077
0078 #define kernel_code mem_res[0]
0079 #define kernel_data mem_res[1]
0080
0081 /*
0082  * The recorded values of x0 .. x3 upon kernel entry.
0083  */
0084 u64 __cacheline_aligned boot_args[4];
0085
0086 void __init smp_setup_processor_id(void)
0087 {
0088     u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
0089     set_cpu_logical_map(0, mpidr);
0090
0091     pr_info("Booting Linux on physical CPU 0x%010lx [0x%08x]\n",
0092         (unsigned long)mpidr, read_cpuid_id());
0093 }
0094
0095 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
0096 {
0097     return phys_id == cpu_logical_map(cpu);
0098 }
0099
0100 struct mpidr_hash mpidr_hash;
0101 /**
0102  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
0103  *            level in order to build a linear index from an
0104  *            MPIDR value. Resulting algorithm is a collision
0105  *            free hash carried out through shifting and ORing
0106  */
0107 static void __init smp_build_mpidr_hash(void)
0108 {
0109     u32 i, affinity, fs[4], bits[4], ls;
0110     u64 mask = 0;
0111     /*
0112      * Pre-scan the list of MPIDRS and filter out bits that do
0113      * not contribute to affinity levels, ie they never toggle.
0114      */
0115     for_each_possible_cpu(i)
0116         mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
0117     pr_debug("mask of set bits %#llx\n", mask);
0118     /*
0119      * Find and stash the last and first bit set at all affinity levels to
0120      * check how many bits are required to represent them.
0121      */
0122     for (i = 0; i < 4; i++) {
0123         affinity = MPIDR_AFFINITY_LEVEL(mask, i);
0124         /*
0125          * Find the MSB bit and LSB bits position
0126          * to determine how many bits are required
0127          * to express the affinity level.
0128          */
0129         ls = fls(affinity);
0130         fs[i] = affinity ? ffs(affinity) - 1 : 0;
0131         bits[i] = ls - fs[i];
0132     }
0133     /*
0134      * An index can be created from the MPIDR_EL1 by isolating the
0135      * significant bits at each affinity level and by shifting
0136      * them in order to compress the 32 bits values space to a
0137      * compressed set of values. This is equivalent to hashing
0138      * the MPIDR_EL1 through shifting and ORing. It is a collision free
0139      * hash though not minimal since some levels might contain a number
0140      * of CPUs that is not an exact power of 2 and their bit
0141      * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
0142      */
0143     mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
0144     mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
0145     mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
0146                         (bits[1] + bits[0]);
0147     mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
0148                   fs[3] - (bits[2] + bits[1] + bits[0]);
0149     mpidr_hash.mask = mask;
0150     mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
0151     pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
0152         mpidr_hash.shift_aff[0],
0153         mpidr_hash.shift_aff[1],
0154         mpidr_hash.shift_aff[2],
0155         mpidr_hash.shift_aff[3],
0156         mpidr_hash.mask,
0157         mpidr_hash.bits);
0158     /*
0159      * 4x is an arbitrary value used to warn on a hash table much bigger
0160      * than expected on most systems.
0161      */
0162     if (mpidr_hash_size() > 4 * num_possible_cpus())
0163         pr_warn("Large number of MPIDR hash buckets detected\n");
0164 }
0165
0166 static void *early_fdt_ptr __initdata;
0167
0168 void __init *get_early_fdt_ptr(void)
0169 {
0170     return early_fdt_ptr;
0171 }
0172
0173 asmlinkage void __init early_fdt_map(u64 dt_phys)
0174 {
0175     int fdt_size;
0176
0177     early_fixmap_init();
0178     early_fdt_ptr = fixmap_remap_fdt(dt_phys, &fdt_size, PAGE_KERNEL);
0179 }
0180
0181 static void __init setup_machine_fdt(phys_addr_t dt_phys)
0182 {
0183     int size;
0184     void *dt_virt = fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL);
0185     const char *name;
0186
0187     if (dt_virt)
0188         memblock_reserve(dt_phys, size);
0189
0190     if (!dt_virt || !early_init_dt_scan(dt_virt)) {
0191         pr_crit("\n"
0192             "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n"
0193             "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
0194             "\nPlease check your bootloader.",
0195             &dt_phys, dt_virt);
0196
0197         /*
0198          * Note that in this _really_ early stage we cannot even BUG()
0199          * or oops, so the least terrible thing to do is cpu_relax(),
0200          * or else we could end-up printing non-initialized data, etc.
0201          */
0202         while (true)
0203             cpu_relax();
0204     }
0205
0206     /* Early fixups are done, map the FDT as read-only now */
0207     fixmap_remap_fdt(dt_phys, &size, PAGE_KERNEL_RO);
0208
0209     name = of_flat_dt_get_machine_name();
0210     if (!name)
0211         return;
0212
0213     pr_info("Machine model: %s\n", name);
0214     dump_stack_set_arch_desc("%s (DT)", name);
0215 }
0216
0217 static void __init request_standard_resources(void)
0218 {
0219     struct memblock_region *region;
0220     struct resource *res;
0221     unsigned long i = 0;
0222     size_t res_size;
0223
0224     kernel_code.start   = __pa_symbol(_stext);
0225     kernel_code.end     = __pa_symbol(__init_begin - 1);
0226     kernel_data.start   = __pa_symbol(_sdata);
0227     kernel_data.end     = __pa_symbol(_end - 1);
0228     insert_resource(&iomem_resource, &kernel_code);
0229     insert_resource(&iomem_resource, &kernel_data);
0230
0231     num_standard_resources = memblock.memory.cnt;
0232     res_size = num_standard_resources * sizeof(*standard_resources);
0233     standard_resources = memblock_alloc(res_size, SMP_CACHE_BYTES);
0234     if (!standard_resources)
0235         panic("%s: Failed to allocate %zu bytes\n", __func__, res_size);
0236
0237     for_each_mem_region(region) {
0238         res = &standard_resources[i++];
0239         if (memblock_is_nomap(region)) {
0240             res->name  = "reserved";
0241             res->flags = IORESOURCE_MEM;
0242             res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));
0243             res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;
0244         } else {
0245             res->name  = "System RAM";
0246             res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
0247             res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
0248             res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
0249         }
0250
0251         insert_resource(&iomem_resource, res);
0252     }
0253 }
0254
0255 static int __init reserve_memblock_reserved_regions(void)
0256 {
0257     u64 i, j;
0258
0259     for (i = 0; i < num_standard_resources; ++i) {
0260         struct resource *mem = &standard_resources[i];
0261         phys_addr_t r_start, r_end, mem_size = resource_size(mem);
0262
0263         if (!memblock_is_region_reserved(mem->start, mem_size))
0264             continue;
0265
0266         for_each_reserved_mem_range(j, &r_start, &r_end) {
0267             resource_size_t start, end;
0268
0269             start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);
0270             end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);
0271
0272             if (start > mem->end || end < mem->start)
0273                 continue;
0274
0275             reserve_region_with_split(mem, start, end, "reserved");
0276         }
0277     }
0278
0279     return 0;
0280 }
0281 arch_initcall(reserve_memblock_reserved_regions);
0282
0283 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
0284
0285 u64 cpu_logical_map(unsigned int cpu)
0286 {
0287     return __cpu_logical_map[cpu];
0288 }
0289
0290 void __init __no_sanitize_address setup_arch(char **cmdline_p)
0291 {
0292     setup_initial_init_mm(_stext, _etext, _edata, _end);
0293
0294     *cmdline_p = boot_command_line;
0295
0296     /*
0297      * If know now we are going to need KPTI then use non-global
0298      * mappings from the start, avoiding the cost of rewriting
0299      * everything later.
0300      */
0301     arm64_use_ng_mappings = kaslr_requires_kpti();
0302
0303     early_fixmap_init();
0304     early_ioremap_init();
0305
0306     setup_machine_fdt(__fdt_pointer);
0307
0308     /*
0309      * Initialise the static keys early as they may be enabled by the
0310      * cpufeature code and early parameters.
0311      */
0312     jump_label_init();
0313     parse_early_param();
0314
0315     /*
0316      * Unmask asynchronous aborts and fiq after bringing up possible
0317      * earlycon. (Report possible System Errors once we can report this
0318      * occurred).
0319      */
0320     local_daif_restore(DAIF_PROCCTX_NOIRQ);
0321
0322     /*
0323      * TTBR0 is only used for the identity mapping at this stage. Make it
0324      * point to zero page to avoid speculatively fetching new entries.
0325      */
0326     cpu_uninstall_idmap();
0327
0328     xen_early_init();
0329     efi_init();
0330
0331     if (!efi_enabled(EFI_BOOT) && ((u64)_text % MIN_KIMG_ALIGN) != 0)
0332          pr_warn(FW_BUG "Kernel image misaligned at boot, please fix your bootloader!");
0333
0334     arm64_memblock_init();
0335
0336     paging_init();
0337
0338     acpi_table_upgrade();
0339
0340     /* Parse the ACPI tables for possible boot-time configuration */
0341     acpi_boot_table_init();
0342
0343     if (acpi_disabled)
0344         unflatten_device_tree();
0345
0346     bootmem_init();
0347
0348     kasan_init();
0349
0350     request_standard_resources();
0351
0352     early_ioremap_reset();
0353
0354     if (acpi_disabled)
0355         psci_dt_init();
0356     else
0357         psci_acpi_init();
0358
0359     init_bootcpu_ops();
0360     smp_init_cpus();
0361     smp_build_mpidr_hash();
0362
0363     /* Init percpu seeds for random tags after cpus are set up. */
0364     kasan_init_sw_tags();
0365
0366 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
0367     /*
0368      * Make sure init_thread_info.ttbr0 always generates translation
0369      * faults in case uaccess_enable() is inadvertently called by the init
0370      * thread.
0371      */
0372     init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
0373 #endif
0374
0375     if (boot_args[1] || boot_args[2] || boot_args[3]) {
0376         pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
0377             "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
0378             "This indicates a broken bootloader or old kernel\n",
0379             boot_args[1], boot_args[2], boot_args[3]);
0380     }
0381 }
0382
0383 static inline bool cpu_can_disable(unsigned int cpu)
0384 {
0385 #ifdef CONFIG_HOTPLUG_CPU
0386     const struct cpu_operations *ops = get_cpu_ops(cpu);
0387
0388     if (ops && ops->cpu_can_disable)
0389         return ops->cpu_can_disable(cpu);
0390 #endif
0391     return false;
0392 }
0393
0394 static int __init topology_init(void)
0395 {
0396     int i;
0397
0398     for_each_possible_cpu(i) {
0399         struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
0400         cpu->hotpluggable = cpu_can_disable(i);
0401         register_cpu(cpu, i);
0402     }
0403
0404     return 0;
0405 }
0406 subsys_initcall(topology_init);
0407
0408 static void dump_kernel_offset(void)
0409 {
0410     const unsigned long offset = kaslr_offset();
0411
0412     if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && offset > 0) {
0413         pr_emerg("Kernel Offset: 0x%lx from 0x%lx\n",
0414              offset, KIMAGE_VADDR);
0415         pr_emerg("PHYS_OFFSET: 0x%llx\n", PHYS_OFFSET);
0416     } else {
0417         pr_emerg("Kernel Offset: disabled\n");
0418     }
0419 }
0420
0421 static int arm64_panic_block_dump(struct notifier_block *self,
0422                   unsigned long v, void *p)
0423 {
0424     dump_kernel_offset();
0425     dump_cpu_features();
0426     dump_mem_limit();
0427     return 0;
0428 }
0429
0430 static struct notifier_block arm64_panic_block = {
0431     .notifier_call = arm64_panic_block_dump
0432 };
0433
0434 static int __init register_arm64_panic_block(void)
0435 {
0436     atomic_notifier_chain_register(&panic_notifier_list,
0437                        &arm64_panic_block);
0438     return 0;
0439 }
0440 device_initcall(register_arm64_panic_block);