arm64/kernel/head.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Low-level CPU initialisation
0004  * Based on arch/arm/kernel/head.S
0005  *
0006  * Copyright (C) 1994-2002 Russell King
0007  * Copyright (C) 2003-2012 ARM Ltd.
0008  * Authors: Catalin Marinas <catalin.marinas@arm.com>
0009  *      Will Deacon <will.deacon@arm.com>
0010  */
0011
0012 #include <linux/linkage.h>
0013 #include <linux/init.h>
0014 #include <linux/pgtable.h>
0015
0016 #include <asm/asm_pointer_auth.h>
0017 #include <asm/assembler.h>
0018 #include <asm/boot.h>
0019 #include <asm/bug.h>
0020 #include <asm/ptrace.h>
0021 #include <asm/asm-offsets.h>
0022 #include <asm/cache.h>
0023 #include <asm/cputype.h>
0024 #include <asm/el2_setup.h>
0025 #include <asm/elf.h>
0026 #include <asm/image.h>
0027 #include <asm/kernel-pgtable.h>
0028 #include <asm/kvm_arm.h>
0029 #include <asm/memory.h>
0030 #include <asm/pgtable-hwdef.h>
0031 #include <asm/page.h>
0032 #include <asm/scs.h>
0033 #include <asm/smp.h>
0034 #include <asm/sysreg.h>
0035 #include <asm/thread_info.h>
0036 #include <asm/virt.h>
0037
0038 #include "efi-header.S"
0039
0040 #if (PAGE_OFFSET & 0x1fffff) != 0
0041 #error PAGE_OFFSET must be at least 2MB aligned
0042 #endif
0043
0044 /*
0045  * Kernel startup entry point.
0046  * ---------------------------
0047  *
0048  * The requirements are:
0049  *   MMU = off, D-cache = off, I-cache = on or off,
0050  *   x0 = physical address to the FDT blob.
0051  *
0052  * Note that the callee-saved registers are used for storing variables
0053  * that are useful before the MMU is enabled. The allocations are described
0054  * in the entry routines.
0055  */
0056     __HEAD
0057     /*
0058      * DO NOT MODIFY. Image header expected by Linux boot-loaders.
0059      */
0060     efi_signature_nop           // special NOP to identity as PE/COFF executable
0061     b   primary_entry           // branch to kernel start, magic
0062     .quad   0               // Image load offset from start of RAM, little-endian
0063     le64sym _kernel_size_le         // Effective size of kernel image, little-endian
0064     le64sym _kernel_flags_le        // Informative flags, little-endian
0065     .quad   0               // reserved
0066     .quad   0               // reserved
0067     .quad   0               // reserved
0068     .ascii  ARM64_IMAGE_MAGIC       // Magic number
0069     .long   .Lpe_header_offset      // Offset to the PE header.
0070
0071     __EFI_PE_HEADER
0072
0073     __INIT
0074
0075     /*
0076      * The following callee saved general purpose registers are used on the
0077      * primary lowlevel boot path:
0078      *
0079      *  Register   Scope                      Purpose
0080      *  x20        primary_entry() .. __primary_switch()    CPU boot mode
0081      *  x21        primary_entry() .. start_kernel()        FDT pointer passed at boot in x0
0082      *  x22        create_idmap() .. start_kernel()         ID map VA of the DT blob
0083      *  x23        primary_entry() .. start_kernel()        physical misalignment/KASLR offset
0084      *  x24        __primary_switch()                       linear map KASLR seed
0085      *  x25        primary_entry() .. start_kernel()        supported VA size
0086      *  x28        create_idmap()                           callee preserved temp register
0087      */
0088 SYM_CODE_START(primary_entry)
0089     bl  preserve_boot_args
0090     bl  init_kernel_el          // w0=cpu_boot_mode
0091     mov x20, x0
0092     bl  create_idmap
0093
0094     /*
0095      * The following calls CPU setup code, see arch/arm64/mm/proc.S for
0096      * details.
0097      * On return, the CPU will be ready for the MMU to be turned on and
0098      * the TCR will have been set.
0099      */
0100 #if VA_BITS > 48
0101     mrs_s   x0, SYS_ID_AA64MMFR2_EL1
0102     tst x0, #0xf << ID_AA64MMFR2_LVA_SHIFT
0103     mov x0, #VA_BITS
0104     mov x25, #VA_BITS_MIN
0105     csel    x25, x25, x0, eq
0106     mov x0, x25
0107 #endif
0108     bl  __cpu_setup         // initialise processor
0109     b   __primary_switch
0110 SYM_CODE_END(primary_entry)
0111
0112 /*
0113  * Preserve the arguments passed by the bootloader in x0 .. x3
0114  */
0115 SYM_CODE_START_LOCAL(preserve_boot_args)
0116     mov x21, x0             // x21=FDT
0117
0118     adr_l   x0, boot_args           // record the contents of
0119     stp x21, x1, [x0]           // x0 .. x3 at kernel entry
0120     stp x2, x3, [x0, #16]
0121
0122     dmb sy              // needed before dc ivac with
0123                         // MMU off
0124
0125     add x1, x0, #0x20           // 4 x 8 bytes
0126     b   dcache_inval_poc        // tail call
0127 SYM_CODE_END(preserve_boot_args)
0128
0129 SYM_FUNC_START_LOCAL(clear_page_tables)
0130     /*
0131      * Clear the init page tables.
0132      */
0133     adrp    x0, init_pg_dir
0134     adrp    x1, init_pg_end
0135     sub x2, x1, x0
0136     mov x1, xzr
0137     b   __pi_memset         // tail call
0138 SYM_FUNC_END(clear_page_tables)
0139
0140 /*
0141  * Macro to populate page table entries, these entries can be pointers to the next level
0142  * or last level entries pointing to physical memory.
0143  *
0144  *  tbl:    page table address
0145  *  rtbl:   pointer to page table or physical memory
0146  *  index:  start index to write
0147  *  eindex: end index to write - [index, eindex] written to
0148  *  flags:  flags for pagetable entry to or in
0149  *  inc:    increment to rtbl between each entry
0150  *  tmp1:   temporary variable
0151  *
0152  * Preserves:   tbl, eindex, flags, inc
0153  * Corrupts:    index, tmp1
0154  * Returns: rtbl
0155  */
0156     .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
0157 .Lpe\@: phys_to_pte \tmp1, \rtbl
0158     orr \tmp1, \tmp1, \flags    // tmp1 = table entry
0159     str \tmp1, [\tbl, \index, lsl #3]
0160     add \rtbl, \rtbl, \inc  // rtbl = pa next level
0161     add \index, \index, #1
0162     cmp \index, \eindex
0163     b.ls    .Lpe\@
0164     .endm
0165
0166 /*
0167  * Compute indices of table entries from virtual address range. If multiple entries
0168  * were needed in the previous page table level then the next page table level is assumed
0169  * to be composed of multiple pages. (This effectively scales the end index).
0170  *
0171  *  vstart: virtual address of start of range
0172  *  vend:   virtual address of end of range - we map [vstart, vend]
0173  *  shift:  shift used to transform virtual address into index
0174  *  order:  #imm 2log(number of entries in page table)
0175  *  istart: index in table corresponding to vstart
0176  *  iend:   index in table corresponding to vend
0177  *  count:  On entry: how many extra entries were required in previous level, scales
0178  *            our end index.
0179  *      On exit: returns how many extra entries required for next page table level
0180  *
0181  * Preserves:   vstart, vend
0182  * Returns: istart, iend, count
0183  */
0184     .macro compute_indices, vstart, vend, shift, order, istart, iend, count
0185     ubfx    \istart, \vstart, \shift, \order
0186     ubfx    \iend, \vend, \shift, \order
0187     add \iend, \iend, \count, lsl \order
0188     sub \count, \iend, \istart
0189     .endm
0190
0191 /*
0192  * Map memory for specified virtual address range. Each level of page table needed supports
0193  * multiple entries. If a level requires n entries the next page table level is assumed to be
0194  * formed from n pages.
0195  *
0196  *  tbl:    location of page table
0197  *  rtbl:   address to be used for first level page table entry (typically tbl + PAGE_SIZE)
0198  *  vstart: virtual address of start of range
0199  *  vend:   virtual address of end of range - we map [vstart, vend - 1]
0200  *  flags:  flags to use to map last level entries
0201  *  phys:   physical address corresponding to vstart - physical memory is contiguous
0202  *  order:  #imm 2log(number of entries in PGD table)
0203  *
0204  * If extra_shift is set, an extra level will be populated if the end address does
0205  * not fit in 'extra_shift' bits. This assumes vend is in the TTBR0 range.
0206  *
0207  * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
0208  * Preserves:   vstart, flags
0209  * Corrupts:    tbl, rtbl, vend, istart, iend, tmp, count, sv
0210  */
0211     .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv, extra_shift
0212     sub \vend, \vend, #1
0213     add \rtbl, \tbl, #PAGE_SIZE
0214     mov \count, #0
0215
0216     .ifnb   \extra_shift
0217     tst \vend, #~((1 << (\extra_shift)) - 1)
0218     b.eq    .L_\@
0219     compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count
0220     mov \sv, \rtbl
0221     populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
0222     mov \tbl, \sv
0223     .endif
0224 .L_\@:
0225     compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count
0226     mov \sv, \rtbl
0227     populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
0228     mov \tbl, \sv
0229
0230 #if SWAPPER_PGTABLE_LEVELS > 3
0231     compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
0232     mov \sv, \rtbl
0233     populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
0234     mov \tbl, \sv
0235 #endif
0236
0237 #if SWAPPER_PGTABLE_LEVELS > 2
0238     compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
0239     mov \sv, \rtbl
0240     populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
0241     mov \tbl, \sv
0242 #endif
0243
0244     compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
0245     bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1
0246     populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
0247     .endm
0248
0249 /*
0250  * Remap a subregion created with the map_memory macro with modified attributes
0251  * or output address. The entire remapped region must have been covered in the
0252  * invocation of map_memory.
0253  *
0254  * x0: last level table address (returned in first argument to map_memory)
0255  * x1: start VA of the existing mapping
0256  * x2: start VA of the region to update
0257  * x3: end VA of the region to update (exclusive)
0258  * x4: start PA associated with the region to update
0259  * x5: attributes to set on the updated region
0260  * x6: order of the last level mappings
0261  */
0262 SYM_FUNC_START_LOCAL(remap_region)
0263     sub x3, x3, #1      // make end inclusive
0264
0265     // Get the index offset for the start of the last level table
0266     lsr x1, x1, x6
0267     bfi x1, xzr, #0, #PAGE_SHIFT - 3
0268
0269     // Derive the start and end indexes into the last level table
0270     // associated with the provided region
0271     lsr x2, x2, x6
0272     lsr x3, x3, x6
0273     sub x2, x2, x1
0274     sub x3, x3, x1
0275
0276     mov x1, #1
0277     lsl x6, x1, x6      // block size at this level
0278
0279     populate_entries x0, x4, x2, x3, x5, x6, x7
0280     ret
0281 SYM_FUNC_END(remap_region)
0282
0283 SYM_FUNC_START_LOCAL(create_idmap)
0284     mov x28, lr
0285     /*
0286      * The ID map carries a 1:1 mapping of the physical address range
0287      * covered by the loaded image, which could be anywhere in DRAM. This
0288      * means that the required size of the VA (== PA) space is decided at
0289      * boot time, and could be more than the configured size of the VA
0290      * space for ordinary kernel and user space mappings.
0291      *
0292      * There are three cases to consider here:
0293      * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover
0294      *   the placement of the image. In this case, we configure one extra
0295      *   level of translation on the fly for the ID map only. (This case
0296      *   also covers 42-bit VA/52-bit PA on 64k pages).
0297      *
0298      * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can
0299      *   only happen when using 64k pages, in which case we need to extend
0300      *   the root level table rather than add a level. Note that we can
0301      *   treat this case as 'always extended' as long as we take care not
0302      *   to program an unsupported T0SZ value into the TCR register.
0303      *
0304      * - Combinations that would require two additional levels of
0305      *   translation are not supported, e.g., VA_BITS==36 on 16k pages, or
0306      *   VA_BITS==39/4k pages with 5-level paging, where the input address
0307      *   requires more than 47 or 48 bits, respectively.
0308      */
0309 #if (VA_BITS < 48)
0310 #define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT)
0311 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
0312
0313     /*
0314      * If VA_BITS < 48, we have to configure an additional table level.
0315      * First, we have to verify our assumption that the current value of
0316      * VA_BITS was chosen such that all translation levels are fully
0317      * utilised, and that lowering T0SZ will always result in an additional
0318      * translation level to be configured.
0319      */
0320 #if VA_BITS != EXTRA_SHIFT
0321 #error "Mismatch between VA_BITS and page size/number of translation levels"
0322 #endif
0323 #else
0324 #define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT)
0325 #define EXTRA_SHIFT
0326     /*
0327      * If VA_BITS == 48, we don't have to configure an additional
0328      * translation level, but the top-level table has more entries.
0329      */
0330 #endif
0331     adrp    x0, init_idmap_pg_dir
0332     adrp    x3, _text
0333     adrp    x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
0334     mov x7, SWAPPER_RX_MMUFLAGS
0335
0336     map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT
0337
0338     /* Remap the kernel page tables r/w in the ID map */
0339     adrp    x1, _text
0340     adrp    x2, init_pg_dir
0341     adrp    x3, init_pg_end
0342     bic x4, x2, #SWAPPER_BLOCK_SIZE - 1
0343     mov x5, SWAPPER_RW_MMUFLAGS
0344     mov x6, #SWAPPER_BLOCK_SHIFT
0345     bl  remap_region
0346
0347     /* Remap the FDT after the kernel image */
0348     adrp    x1, _text
0349     adrp    x22, _end + SWAPPER_BLOCK_SIZE
0350     bic x2, x22, #SWAPPER_BLOCK_SIZE - 1
0351     bfi x22, x21, #0, #SWAPPER_BLOCK_SHIFT      // remapped FDT address
0352     add x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
0353     bic x4, x21, #SWAPPER_BLOCK_SIZE - 1
0354     mov x5, SWAPPER_RW_MMUFLAGS
0355     mov x6, #SWAPPER_BLOCK_SHIFT
0356     bl  remap_region
0357
0358     /*
0359      * Since the page tables have been populated with non-cacheable
0360      * accesses (MMU disabled), invalidate those tables again to
0361      * remove any speculatively loaded cache lines.
0362      */
0363     dmb sy
0364
0365     adrp    x0, init_idmap_pg_dir
0366     adrp    x1, init_idmap_pg_end
0367     bl  dcache_inval_poc
0368     ret x28
0369 SYM_FUNC_END(create_idmap)
0370
0371 SYM_FUNC_START_LOCAL(create_kernel_mapping)
0372     adrp    x0, init_pg_dir
0373     mov_q   x5, KIMAGE_VADDR        // compile time __va(_text)
0374 #ifdef CONFIG_RELOCATABLE
0375     add x5, x5, x23         // add KASLR displacement
0376 #endif
0377     adrp    x6, _end            // runtime __pa(_end)
0378     adrp    x3, _text           // runtime __pa(_text)
0379     sub x6, x6, x3          // _end - _text
0380     add x6, x6, x5          // runtime __va(_end)
0381     mov x7, SWAPPER_RW_MMUFLAGS
0382
0383     map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
0384
0385     dsb ishst               // sync with page table walker
0386     ret
0387 SYM_FUNC_END(create_kernel_mapping)
0388
0389     /*
0390      * Initialize CPU registers with task-specific and cpu-specific context.
0391      *
0392      * Create a final frame record at task_pt_regs(current)->stackframe, so
0393      * that the unwinder can identify the final frame record of any task by
0394      * its location in the task stack. We reserve the entire pt_regs space
0395      * for consistency with user tasks and kthreads.
0396      */
0397     .macro  init_cpu_task tsk, tmp1, tmp2
0398     msr sp_el0, \tsk
0399
0400     ldr \tmp1, [\tsk, #TSK_STACK]
0401     add sp, \tmp1, #THREAD_SIZE
0402     sub sp, sp, #PT_REGS_SIZE
0403
0404     stp xzr, xzr, [sp, #S_STACKFRAME]
0405     add x29, sp, #S_STACKFRAME
0406
0407     scs_load \tsk
0408
0409     adr_l   \tmp1, __per_cpu_offset
0410     ldr w\tmp2, [\tsk, #TSK_TI_CPU]
0411     ldr \tmp1, [\tmp1, \tmp2, lsl #3]
0412     set_this_cpu_offset \tmp1
0413     .endm
0414
0415 /*
0416  * The following fragment of code is executed with the MMU enabled.
0417  *
0418  *   x0 = __pa(KERNEL_START)
0419  */
0420 SYM_FUNC_START_LOCAL(__primary_switched)
0421     adr_l   x4, init_task
0422     init_cpu_task x4, x5, x6
0423
0424     adr_l   x8, vectors         // load VBAR_EL1 with virtual
0425     msr vbar_el1, x8            // vector table address
0426     isb
0427
0428     stp x29, x30, [sp, #-16]!
0429     mov x29, sp
0430
0431     str_l   x21, __fdt_pointer, x5      // Save FDT pointer
0432
0433     ldr_l   x4, kimage_vaddr        // Save the offset between
0434     sub x4, x4, x0          // the kernel virtual and
0435     str_l   x4, kimage_voffset, x5      // physical mappings
0436
0437     mov x0, x20
0438     bl  set_cpu_boot_mode_flag
0439
0440     // Clear BSS
0441     adr_l   x0, __bss_start
0442     mov x1, xzr
0443     adr_l   x2, __bss_stop
0444     sub x2, x2, x0
0445     bl  __pi_memset
0446     dsb ishst               // Make zero page visible to PTW
0447
0448 #if VA_BITS > 48
0449     adr_l   x8, vabits_actual       // Set this early so KASAN early init
0450     str x25, [x8]           // ... observes the correct value
0451     dc  civac, x8           // Make visible to booting secondaries
0452 #endif
0453
0454 #ifdef CONFIG_RANDOMIZE_BASE
0455     adrp    x5, memstart_offset_seed    // Save KASLR linear map seed
0456     strh    w24, [x5, :lo12:memstart_offset_seed]
0457 #endif
0458 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
0459     bl  kasan_early_init
0460 #endif
0461     mov x0, x21             // pass FDT address in x0
0462     bl  early_fdt_map           // Try mapping the FDT early
0463     mov x0, x20             // pass the full boot status
0464     bl  init_feature_override       // Parse cpu feature overrides
0465     mov x0, x20
0466     bl  finalise_el2            // Prefer VHE if possible
0467     ldp x29, x30, [sp], #16
0468     bl  start_kernel
0469     ASM_BUG()
0470 SYM_FUNC_END(__primary_switched)
0471
0472 /*
0473  * end early head section, begin head code that is also used for
0474  * hotplug and needs to have the same protections as the text region
0475  */
0476     .section ".idmap.text","awx"
0477
0478 /*
0479  * Starting from EL2 or EL1, configure the CPU to execute at the highest
0480  * reachable EL supported by the kernel in a chosen default state. If dropping
0481  * from EL2 to EL1, configure EL2 before configuring EL1.
0482  *
0483  * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
0484  * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
0485  *
0486  * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if
0487  * booted in EL1 or EL2 respectively, with the top 32 bits containing
0488  * potential context flags. These flags are *not* stored in __boot_cpu_mode.
0489  */
0490 SYM_FUNC_START(init_kernel_el)
0491     mrs x0, CurrentEL
0492     cmp x0, #CurrentEL_EL2
0493     b.eq    init_el2
0494
0495 SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
0496     mov_q   x0, INIT_SCTLR_EL1_MMU_OFF
0497     msr sctlr_el1, x0
0498     isb
0499     mov_q   x0, INIT_PSTATE_EL1
0500     msr spsr_el1, x0
0501     msr elr_el1, lr
0502     mov w0, #BOOT_CPU_MODE_EL1
0503     eret
0504
0505 SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
0506     mov_q   x0, HCR_HOST_NVHE_FLAGS
0507     msr hcr_el2, x0
0508     isb
0509
0510     init_el2_state
0511
0512     /* Hypervisor stub */
0513     adr_l   x0, __hyp_stub_vectors
0514     msr vbar_el2, x0
0515     isb
0516
0517     mov_q   x1, INIT_SCTLR_EL1_MMU_OFF
0518
0519     /*
0520      * Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
0521      * making it impossible to start in nVHE mode. Is that
0522      * compliant with the architecture? Absolutely not!
0523      */
0524     mrs x0, hcr_el2
0525     and x0, x0, #HCR_E2H
0526     cbz x0, 1f
0527
0528     /* Set a sane SCTLR_EL1, the VHE way */
0529     msr_s   SYS_SCTLR_EL12, x1
0530     mov x2, #BOOT_CPU_FLAG_E2H
0531     b   2f
0532
0533 1:
0534     msr sctlr_el1, x1
0535     mov x2, xzr
0536 2:
0537     msr elr_el2, lr
0538     mov w0, #BOOT_CPU_MODE_EL2
0539     orr x0, x0, x2
0540     eret
0541 SYM_FUNC_END(init_kernel_el)
0542
0543 /*
0544  * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
0545  * in w0. See arch/arm64/include/asm/virt.h for more info.
0546  */
0547 SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
0548     adr_l   x1, __boot_cpu_mode
0549     cmp w0, #BOOT_CPU_MODE_EL2
0550     b.ne    1f
0551     add x1, x1, #4
0552 1:  str w0, [x1]            // Save CPU boot mode
0553     ret
0554 SYM_FUNC_END(set_cpu_boot_mode_flag)
0555
0556     /*
0557      * This provides a "holding pen" for platforms to hold all secondary
0558      * cores are held until we're ready for them to initialise.
0559      */
0560 SYM_FUNC_START(secondary_holding_pen)
0561     bl  init_kernel_el          // w0=cpu_boot_mode
0562     mrs x2, mpidr_el1
0563     mov_q   x1, MPIDR_HWID_BITMASK
0564     and x2, x2, x1
0565     adr_l   x3, secondary_holding_pen_release
0566 pen:    ldr x4, [x3]
0567     cmp x4, x2
0568     b.eq    secondary_startup
0569     wfe
0570     b   pen
0571 SYM_FUNC_END(secondary_holding_pen)
0572
0573     /*
0574      * Secondary entry point that jumps straight into the kernel. Only to
0575      * be used where CPUs are brought online dynamically by the kernel.
0576      */
0577 SYM_FUNC_START(secondary_entry)
0578     bl  init_kernel_el          // w0=cpu_boot_mode
0579     b   secondary_startup
0580 SYM_FUNC_END(secondary_entry)
0581
0582 SYM_FUNC_START_LOCAL(secondary_startup)
0583     /*
0584      * Common entry point for secondary CPUs.
0585      */
0586     mov x20, x0             // preserve boot mode
0587     bl  finalise_el2
0588     bl  __cpu_secondary_check52bitva
0589 #if VA_BITS > 48
0590     ldr_l   x0, vabits_actual
0591 #endif
0592     bl  __cpu_setup         // initialise processor
0593     adrp    x1, swapper_pg_dir
0594     adrp    x2, idmap_pg_dir
0595     bl  __enable_mmu
0596     ldr x8, =__secondary_switched
0597     br  x8
0598 SYM_FUNC_END(secondary_startup)
0599
0600 SYM_FUNC_START_LOCAL(__secondary_switched)
0601     mov x0, x20
0602     bl  set_cpu_boot_mode_flag
0603     str_l   xzr, __early_cpu_boot_status, x3
0604     adr_l   x5, vectors
0605     msr vbar_el1, x5
0606     isb
0607
0608     adr_l   x0, secondary_data
0609     ldr x2, [x0, #CPU_BOOT_TASK]
0610     cbz x2, __secondary_too_slow
0611
0612     init_cpu_task x2, x1, x3
0613
0614 #ifdef CONFIG_ARM64_PTR_AUTH
0615     ptrauth_keys_init_cpu x2, x3, x4, x5
0616 #endif
0617
0618     bl  secondary_start_kernel
0619     ASM_BUG()
0620 SYM_FUNC_END(__secondary_switched)
0621
0622 SYM_FUNC_START_LOCAL(__secondary_too_slow)
0623     wfe
0624     wfi
0625     b   __secondary_too_slow
0626 SYM_FUNC_END(__secondary_too_slow)
0627
0628 /*
0629  * The booting CPU updates the failed status @__early_cpu_boot_status,
0630  * with MMU turned off.
0631  *
0632  * update_early_cpu_boot_status tmp, status
0633  *  - Corrupts tmp1, tmp2
0634  *  - Writes 'status' to __early_cpu_boot_status and makes sure
0635  *    it is committed to memory.
0636  */
0637
0638     .macro  update_early_cpu_boot_status status, tmp1, tmp2
0639     mov \tmp2, #\status
0640     adr_l   \tmp1, __early_cpu_boot_status
0641     str \tmp2, [\tmp1]
0642     dmb sy
0643     dc  ivac, \tmp1         // Invalidate potentially stale cache line
0644     .endm
0645
0646 /*
0647  * Enable the MMU.
0648  *
0649  *  x0  = SCTLR_EL1 value for turning on the MMU.
0650  *  x1  = TTBR1_EL1 value
0651  *  x2  = ID map root table address
0652  *
0653  * Returns to the caller via x30/lr. This requires the caller to be covered
0654  * by the .idmap.text section.
0655  *
0656  * Checks if the selected granule size is supported by the CPU.
0657  * If it isn't, park the CPU
0658  */
0659 SYM_FUNC_START(__enable_mmu)
0660     mrs x3, ID_AA64MMFR0_EL1
0661     ubfx    x3, x3, #ID_AA64MMFR0_TGRAN_SHIFT, 4
0662     cmp     x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN
0663     b.lt    __no_granule_support
0664     cmp     x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX
0665     b.gt    __no_granule_support
0666     phys_to_ttbr x2, x2
0667     msr ttbr0_el1, x2           // load TTBR0
0668     load_ttbr1 x1, x1, x3
0669
0670     set_sctlr_el1   x0
0671
0672     ret
0673 SYM_FUNC_END(__enable_mmu)
0674
0675 SYM_FUNC_START(__cpu_secondary_check52bitva)
0676 #if VA_BITS > 48
0677     ldr_l   x0, vabits_actual
0678     cmp x0, #52
0679     b.ne    2f
0680
0681     mrs_s   x0, SYS_ID_AA64MMFR2_EL1
0682     and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT)
0683     cbnz    x0, 2f
0684
0685     update_early_cpu_boot_status \
0686         CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
0687 1:  wfe
0688     wfi
0689     b   1b
0690
0691 #endif
0692 2:  ret
0693 SYM_FUNC_END(__cpu_secondary_check52bitva)
0694
0695 SYM_FUNC_START_LOCAL(__no_granule_support)
0696     /* Indicate that this CPU can't boot and is stuck in the kernel */
0697     update_early_cpu_boot_status \
0698         CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
0699 1:
0700     wfe
0701     wfi
0702     b   1b
0703 SYM_FUNC_END(__no_granule_support)
0704
0705 #ifdef CONFIG_RELOCATABLE
0706 SYM_FUNC_START_LOCAL(__relocate_kernel)
0707     /*
0708      * Iterate over each entry in the relocation table, and apply the
0709      * relocations in place.
0710      */
0711     adr_l   x9, __rela_start
0712     adr_l   x10, __rela_end
0713     mov_q   x11, KIMAGE_VADDR       // default virtual offset
0714     add x11, x11, x23           // actual virtual offset
0715
0716 0:  cmp x9, x10
0717     b.hs    1f
0718     ldp x12, x13, [x9], #24
0719     ldr x14, [x9, #-8]
0720     cmp w13, #R_AARCH64_RELATIVE
0721     b.ne    0b
0722     add x14, x14, x23           // relocate
0723     str x14, [x12, x23]
0724     b   0b
0725
0726 1:
0727 #ifdef CONFIG_RELR
0728     /*
0729      * Apply RELR relocations.
0730      *
0731      * RELR is a compressed format for storing relative relocations. The
0732      * encoded sequence of entries looks like:
0733      * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ]
0734      *
0735      * i.e. start with an address, followed by any number of bitmaps. The
0736      * address entry encodes 1 relocation. The subsequent bitmap entries
0737      * encode up to 63 relocations each, at subsequent offsets following
0738      * the last address entry.
0739      *
0740      * The bitmap entries must have 1 in the least significant bit. The
0741      * assumption here is that an address cannot have 1 in lsb. Odd
0742      * addresses are not supported. Any odd addresses are stored in the RELA
0743      * section, which is handled above.
0744      *
0745      * Excluding the least significant bit in the bitmap, each non-zero
0746      * bit in the bitmap represents a relocation to be applied to
0747      * a corresponding machine word that follows the base address
0748      * word. The second least significant bit represents the machine
0749      * word immediately following the initial address, and each bit
0750      * that follows represents the next word, in linear order. As such,
0751      * a single bitmap can encode up to 63 relocations in a 64-bit object.
0752      *
0753      * In this implementation we store the address of the next RELR table
0754      * entry in x9, the address being relocated by the current address or
0755      * bitmap entry in x13 and the address being relocated by the current
0756      * bit in x14.
0757      */
0758     adr_l   x9, __relr_start
0759     adr_l   x10, __relr_end
0760
0761 2:  cmp x9, x10
0762     b.hs    7f
0763     ldr x11, [x9], #8
0764     tbnz    x11, #0, 3f         // branch to handle bitmaps
0765     add x13, x11, x23
0766     ldr x12, [x13]          // relocate address entry
0767     add x12, x12, x23
0768     str x12, [x13], #8          // adjust to start of bitmap
0769     b   2b
0770
0771 3:  mov x14, x13
0772 4:  lsr x11, x11, #1
0773     cbz x11, 6f
0774     tbz x11, #0, 5f         // skip bit if not set
0775     ldr x12, [x14]          // relocate bit
0776     add x12, x12, x23
0777     str x12, [x14]
0778
0779 5:  add x14, x14, #8            // move to next bit's address
0780     b   4b
0781
0782 6:  /*
0783      * Move to the next bitmap's address. 8 is the word size, and 63 is the
0784      * number of significant bits in a bitmap entry.
0785      */
0786     add x13, x13, #(8 * 63)
0787     b   2b
0788
0789 7:
0790 #endif
0791     ret
0792
0793 SYM_FUNC_END(__relocate_kernel)
0794 #endif
0795
0796 SYM_FUNC_START_LOCAL(__primary_switch)
0797     adrp    x1, reserved_pg_dir
0798     adrp    x2, init_idmap_pg_dir
0799     bl  __enable_mmu
0800 #ifdef CONFIG_RELOCATABLE
0801     adrp    x23, KERNEL_START
0802     and x23, x23, MIN_KIMG_ALIGN - 1
0803 #ifdef CONFIG_RANDOMIZE_BASE
0804     mov x0, x22
0805     adrp    x1, init_pg_end
0806     mov sp, x1
0807     mov x29, xzr
0808     bl  __pi_kaslr_early_init
0809     and x24, x0, #SZ_2M - 1     // capture memstart offset seed
0810     bic x0, x0, #SZ_2M - 1
0811     orr x23, x23, x0            // record kernel offset
0812 #endif
0813 #endif
0814     bl  clear_page_tables
0815     bl  create_kernel_mapping
0816
0817     adrp    x1, init_pg_dir
0818     load_ttbr1 x1, x1, x2
0819 #ifdef CONFIG_RELOCATABLE
0820     bl  __relocate_kernel
0821 #endif
0822     ldr x8, =__primary_switched
0823     adrp    x0, KERNEL_START        // __pa(KERNEL_START)
0824     br  x8
0825 SYM_FUNC_END(__primary_switch)