uapi/asm/ptrace.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * Based on arch/arm/include/asm/ptrace.h
0004  *
0005  * Copyright (C) 1996-2003 Russell King
0006  * Copyright (C) 2012 ARM Ltd.
0007  *
0008  * This program is free software; you can redistribute it and/or modify
0009  * it under the terms of the GNU General Public License version 2 as
0010  * published by the Free Software Foundation.
0011  *
0012  * This program is distributed in the hope that it will be useful,
0013  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0014  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0015  * GNU General Public License for more details.
0016  *
0017  * You should have received a copy of the GNU General Public License
0018  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
0019  */
0020 #ifndef _UAPI__ASM_PTRACE_H
0021 #define _UAPI__ASM_PTRACE_H
0022
0023 #include <linux/types.h>
0024
0025 #include <asm/hwcap.h>
0026 #include <asm/sve_context.h>
0027
0028
0029 /*
0030  * PSR bits
0031  */
0032 #define PSR_MODE_EL0t   0x00000000
0033 #define PSR_MODE_EL1t   0x00000004
0034 #define PSR_MODE_EL1h   0x00000005
0035 #define PSR_MODE_EL2t   0x00000008
0036 #define PSR_MODE_EL2h   0x00000009
0037 #define PSR_MODE_EL3t   0x0000000c
0038 #define PSR_MODE_EL3h   0x0000000d
0039 #define PSR_MODE_MASK   0x0000000f
0040
0041 /* AArch32 CPSR bits */
0042 #define PSR_MODE32_BIT      0x00000010
0043
0044 /* AArch64 SPSR bits */
0045 #define PSR_F_BIT   0x00000040
0046 #define PSR_I_BIT   0x00000080
0047 #define PSR_A_BIT   0x00000100
0048 #define PSR_D_BIT   0x00000200
0049 #define PSR_BTYPE_MASK  0x00000c00
0050 #define PSR_SSBS_BIT    0x00001000
0051 #define PSR_PAN_BIT 0x00400000
0052 #define PSR_UAO_BIT 0x00800000
0053 #define PSR_DIT_BIT 0x01000000
0054 #define PSR_TCO_BIT 0x02000000
0055 #define PSR_V_BIT   0x10000000
0056 #define PSR_C_BIT   0x20000000
0057 #define PSR_Z_BIT   0x40000000
0058 #define PSR_N_BIT   0x80000000
0059
0060 #define PSR_BTYPE_SHIFT     10
0061
0062 /*
0063  * Groups of PSR bits
0064  */
0065 #define PSR_f       0xff000000  /* Flags        */
0066 #define PSR_s       0x00ff0000  /* Status       */
0067 #define PSR_x       0x0000ff00  /* Extension        */
0068 #define PSR_c       0x000000ff  /* Control      */
0069
0070 /* Convenience names for the values of PSTATE.BTYPE */
0071 #define PSR_BTYPE_NONE      (0b00 << PSR_BTYPE_SHIFT)
0072 #define PSR_BTYPE_JC        (0b01 << PSR_BTYPE_SHIFT)
0073 #define PSR_BTYPE_C     (0b10 << PSR_BTYPE_SHIFT)
0074 #define PSR_BTYPE_J     (0b11 << PSR_BTYPE_SHIFT)
0075
0076 /* syscall emulation path in ptrace */
0077 #define PTRACE_SYSEMU         31
0078 #define PTRACE_SYSEMU_SINGLESTEP  32
0079 /* MTE allocation tag access */
0080 #define PTRACE_PEEKMTETAGS    33
0081 #define PTRACE_POKEMTETAGS    34
0082
0083 #ifndef __ASSEMBLY__
0084
0085 /*
0086  * User structures for general purpose, floating point and debug registers.
0087  */
0088 struct user_pt_regs {
0089     __u64       regs[31];
0090     __u64       sp;
0091     __u64       pc;
0092     __u64       pstate;
0093 };
0094
0095 struct user_fpsimd_state {
0096     __uint128_t vregs[32];
0097     __u32       fpsr;
0098     __u32       fpcr;
0099     __u32       __reserved[2];
0100 };
0101
0102 struct user_hwdebug_state {
0103     __u32       dbg_info;
0104     __u32       pad;
0105     struct {
0106         __u64   addr;
0107         __u32   ctrl;
0108         __u32   pad;
0109     }       dbg_regs[16];
0110 };
0111
0112 /* SVE/FP/SIMD state (NT_ARM_SVE & NT_ARM_SSVE) */
0113
0114 struct user_sve_header {
0115     __u32 size; /* total meaningful regset content in bytes */
0116     __u32 max_size; /* maxmium possible size for this thread */
0117     __u16 vl; /* current vector length */
0118     __u16 max_vl; /* maximum possible vector length */
0119     __u16 flags;
0120     __u16 __reserved;
0121 };
0122
0123 /* Definitions for user_sve_header.flags: */
0124 #define SVE_PT_REGS_MASK        (1 << 0)
0125
0126 #define SVE_PT_REGS_FPSIMD      0
0127 #define SVE_PT_REGS_SVE         SVE_PT_REGS_MASK
0128
0129 /*
0130  * Common SVE_PT_* flags:
0131  * These must be kept in sync with prctl interface in <linux/prctl.h>
0132  */
0133 #define SVE_PT_VL_INHERIT       ((1 << 17) /* PR_SVE_VL_INHERIT */ >> 16)
0134 #define SVE_PT_VL_ONEXEC        ((1 << 18) /* PR_SVE_SET_VL_ONEXEC */ >> 16)
0135
0136
0137 /*
0138  * The remainder of the SVE state follows struct user_sve_header.  The
0139  * total size of the SVE state (including header) depends on the
0140  * metadata in the header:  SVE_PT_SIZE(vq, flags) gives the total size
0141  * of the state in bytes, including the header.
0142  *
0143  * Refer to <asm/sigcontext.h> for details of how to pass the correct
0144  * "vq" argument to these macros.
0145  */
0146
0147 /* Offset from the start of struct user_sve_header to the register data */
0148 #define SVE_PT_REGS_OFFSET                      \
0149     ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1))    \
0150         / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
0151
0152 /*
0153  * The register data content and layout depends on the value of the
0154  * flags field.
0155  */
0156
0157 /*
0158  * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case:
0159  *
0160  * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type
0161  * struct user_fpsimd_state.  Additional data might be appended in the
0162  * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size.
0163  * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than
0164  * sizeof(struct user_fpsimd_state).
0165  */
0166
0167 #define SVE_PT_FPSIMD_OFFSET        SVE_PT_REGS_OFFSET
0168
0169 #define SVE_PT_FPSIMD_SIZE(vq, flags)   (sizeof(struct user_fpsimd_state))
0170
0171 /*
0172  * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case:
0173  *
0174  * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size
0175  * SVE_PT_SVE_SIZE(vq, flags).
0176  *
0177  * Additional macros describe the contents and layout of the payload.
0178  * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to
0179  * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is
0180  * the size in bytes:
0181  *
0182  *  x   type                description
0183  *  -   ----                -----------
0184  *  ZREGS       \
0185  *  ZREG        |
0186  *  PREGS       | refer to <asm/sigcontext.h>
0187  *  PREG        |
0188  *  FFR     /
0189  *
0190  *  FPSR    uint32_t            FPSR
0191  *  FPCR    uint32_t            FPCR
0192  *
0193  * Additional data might be appended in the future.
0194  *
0195  * The Z-, P- and FFR registers are represented in memory in an endianness-
0196  * invariant layout which differs from the layout used for the FPSIMD
0197  * V-registers on big-endian systems: see sigcontext.h for more explanation.
0198  */
0199
0200 #define SVE_PT_SVE_ZREG_SIZE(vq)    __SVE_ZREG_SIZE(vq)
0201 #define SVE_PT_SVE_PREG_SIZE(vq)    __SVE_PREG_SIZE(vq)
0202 #define SVE_PT_SVE_FFR_SIZE(vq)     __SVE_FFR_SIZE(vq)
0203 #define SVE_PT_SVE_FPSR_SIZE        sizeof(__u32)
0204 #define SVE_PT_SVE_FPCR_SIZE        sizeof(__u32)
0205
0206 #define SVE_PT_SVE_OFFSET       SVE_PT_REGS_OFFSET
0207
0208 #define SVE_PT_SVE_ZREGS_OFFSET \
0209     (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
0210 #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \
0211     (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
0212 #define SVE_PT_SVE_ZREGS_SIZE(vq) \
0213     (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
0214
0215 #define SVE_PT_SVE_PREGS_OFFSET(vq) \
0216     (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
0217 #define SVE_PT_SVE_PREG_OFFSET(vq, n) \
0218     (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
0219 #define SVE_PT_SVE_PREGS_SIZE(vq) \
0220     (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - \
0221         SVE_PT_SVE_PREGS_OFFSET(vq))
0222
0223 /* For streaming mode SVE (SSVE) FFR must be read and written as zero */
0224 #define SVE_PT_SVE_FFR_OFFSET(vq) \
0225     (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
0226
0227 #define SVE_PT_SVE_FPSR_OFFSET(vq)              \
0228     ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \
0229             (__SVE_VQ_BYTES - 1))           \
0230         / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
0231 #define SVE_PT_SVE_FPCR_OFFSET(vq) \
0232     (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
0233
0234 /*
0235  * Any future extension appended after FPCR must be aligned to the next
0236  * 128-bit boundary.
0237  */
0238
0239 #define SVE_PT_SVE_SIZE(vq, flags)                  \
0240     ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE     \
0241             - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) \
0242         / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
0243
0244 #define SVE_PT_SIZE(vq, flags)                        \
0245      (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ?       \
0246           SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags)      \
0247         : ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ?  \
0248             SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) \
0249           : SVE_PT_REGS_OFFSET)))
0250
0251 /* pointer authentication masks (NT_ARM_PAC_MASK) */
0252
0253 struct user_pac_mask {
0254     __u64       data_mask;
0255     __u64       insn_mask;
0256 };
0257
0258 /* pointer authentication keys (NT_ARM_PACA_KEYS, NT_ARM_PACG_KEYS) */
0259
0260 struct user_pac_address_keys {
0261     __uint128_t apiakey;
0262     __uint128_t apibkey;
0263     __uint128_t apdakey;
0264     __uint128_t apdbkey;
0265 };
0266
0267 struct user_pac_generic_keys {
0268     __uint128_t apgakey;
0269 };
0270
0271 /* ZA state (NT_ARM_ZA) */
0272
0273 struct user_za_header {
0274     __u32 size; /* total meaningful regset content in bytes */
0275     __u32 max_size; /* maxmium possible size for this thread */
0276     __u16 vl; /* current vector length */
0277     __u16 max_vl; /* maximum possible vector length */
0278     __u16 flags;
0279     __u16 __reserved;
0280 };
0281
0282 /*
0283  * Common ZA_PT_* flags:
0284  * These must be kept in sync with prctl interface in <linux/prctl.h>
0285  */
0286 #define ZA_PT_VL_INHERIT        ((1 << 17) /* PR_SME_VL_INHERIT */ >> 16)
0287 #define ZA_PT_VL_ONEXEC         ((1 << 18) /* PR_SME_SET_VL_ONEXEC */ >> 16)
0288
0289
0290 /*
0291  * The remainder of the ZA state follows struct user_za_header.  The
0292  * total size of the ZA state (including header) depends on the
0293  * metadata in the header:  ZA_PT_SIZE(vq, flags) gives the total size
0294  * of the state in bytes, including the header.
0295  *
0296  * Refer to <asm/sigcontext.h> for details of how to pass the correct
0297  * "vq" argument to these macros.
0298  */
0299
0300 /* Offset from the start of struct user_za_header to the register data */
0301 #define ZA_PT_ZA_OFFSET                     \
0302     ((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1)) \
0303         / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
0304
0305 /*
0306  * The payload starts at offset ZA_PT_ZA_OFFSET, and is of size
0307  * ZA_PT_ZA_SIZE(vq, flags).
0308  *
0309  * The ZA array is stored as a sequence of horizontal vectors ZAV of SVL/8
0310  * bytes each, starting from vector 0.
0311  *
0312  * Additional data might be appended in the future.
0313  *
0314  * The ZA matrix is represented in memory in an endianness-invariant layout
0315  * which differs from the layout used for the FPSIMD V-registers on big-endian
0316  * systems: see sigcontext.h for more explanation.
0317  */
0318
0319 #define ZA_PT_ZAV_OFFSET(vq, n) \
0320     (ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
0321
0322 #define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
0323
0324 #define ZA_PT_SIZE(vq)                      \
0325     (ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
0326
0327 #endif /* __ASSEMBLY__ */
0328
0329 #endif /* _UAPI__ASM_PTRACE_H */