include/asm/traps.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Based on arch/arm/include/asm/traps.h
0004  *
0005  * Copyright (C) 2012 ARM Ltd.
0006  */
0007 #ifndef __ASM_TRAP_H
0008 #define __ASM_TRAP_H
0009
0010 #include <linux/list.h>
0011 #include <asm/esr.h>
0012 #include <asm/sections.h>
0013
0014 struct pt_regs;
0015
0016 struct undef_hook {
0017     struct list_head node;
0018     u32 instr_mask;
0019     u32 instr_val;
0020     u64 pstate_mask;
0021     u64 pstate_val;
0022     int (*fn)(struct pt_regs *regs, u32 instr);
0023 };
0024
0025 void register_undef_hook(struct undef_hook *hook);
0026 void unregister_undef_hook(struct undef_hook *hook);
0027 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);
0028 void arm64_notify_segfault(unsigned long addr);
0029 void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
0030 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
0031 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
0032
0033 /*
0034  * Move regs->pc to next instruction and do necessary setup before it
0035  * is executed.
0036  */
0037 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
0038
0039 static inline int __in_irqentry_text(unsigned long ptr)
0040 {
0041     return ptr >= (unsigned long)&__irqentry_text_start &&
0042            ptr < (unsigned long)&__irqentry_text_end;
0043 }
0044
0045 static inline int in_entry_text(unsigned long ptr)
0046 {
0047     return ptr >= (unsigned long)&__entry_text_start &&
0048            ptr < (unsigned long)&__entry_text_end;
0049 }
0050
0051 /*
0052  * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
0053  * to indicate whether this ESR has a RAS encoding. CPUs without this feature
0054  * have a ISS-Valid bit in the same position.
0055  * If this bit is set, we know its not a RAS SError.
0056  * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
0057  * errors share the same encoding as an all-zeros encoding from a CPU that
0058  * doesn't support RAS.
0059  */
0060 static inline bool arm64_is_ras_serror(unsigned long esr)
0061 {
0062     WARN_ON(preemptible());
0063
0064     if (esr & ESR_ELx_IDS)
0065         return false;
0066
0067     if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
0068         return true;
0069     else
0070         return false;
0071 }
0072
0073 /*
0074  * Return the AET bits from a RAS SError's ESR.
0075  *
0076  * It is implementation defined whether Uncategorized errors are containable.
0077  * We treat them as Uncontainable.
0078  * Non-RAS SError's are reported as Uncontained/Uncategorized.
0079  */
0080 static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
0081 {
0082     unsigned long aet = esr & ESR_ELx_AET;
0083
0084     if (!arm64_is_ras_serror(esr)) {
0085         /* Not a RAS error, we can't interpret the ESR. */
0086         return ESR_ELx_AET_UC;
0087     }
0088
0089     /*
0090      * AET is RES0 if 'the value returned in the DFSC field is not
0091      * [ESR_ELx_FSC_SERROR]'
0092      */
0093     if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
0094         /* No severity information : Uncategorized */
0095         return ESR_ELx_AET_UC;
0096     }
0097
0098     return aet;
0099 }
0100
0101 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
0102 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
0103 #endif