include/asm/ptrace.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Based on arch/arm/include/asm/ptrace.h
0004  *
0005  * Copyright (C) 1996-2003 Russell King
0006  * Copyright (C) 2012 ARM Ltd.
0007  */
0008 #ifndef __ASM_PTRACE_H
0009 #define __ASM_PTRACE_H
0010
0011 #include <asm/cpufeature.h>
0012
0013 #include <uapi/asm/ptrace.h>
0014
0015 /* Current Exception Level values, as contained in CurrentEL */
0016 #define CurrentEL_EL1       (1 << 2)
0017 #define CurrentEL_EL2       (2 << 2)
0018
0019 #define INIT_PSTATE_EL1 \
0020     (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
0021 #define INIT_PSTATE_EL2 \
0022     (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
0023
0024 /*
0025  * PMR values used to mask/unmask interrupts.
0026  *
0027  * GIC priority masking works as follows: if an IRQ's priority is a higher value
0028  * than the value held in PMR, that IRQ is masked. Lowering the value of PMR
0029  * means masking more IRQs (or at least that the same IRQs remain masked).
0030  *
0031  * To mask interrupts, we clear the most significant bit of PMR.
0032  *
0033  * Some code sections either automatically switch back to PSR.I or explicitly
0034  * require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included
0035  * in the priority mask, it indicates that PSR.I should be set and
0036  * interrupt disabling temporarily does not rely on IRQ priorities.
0037  */
0038 #define GIC_PRIO_IRQON          0xe0
0039 #define __GIC_PRIO_IRQOFF       (GIC_PRIO_IRQON & ~0x80)
0040 #define __GIC_PRIO_IRQOFF_NS        0xa0
0041 #define GIC_PRIO_PSR_I_SET      (1 << 4)
0042
0043 #define GIC_PRIO_IRQOFF                         \
0044     ({                              \
0045         extern struct static_key_false gic_nonsecure_priorities;\
0046         u8 __prio = __GIC_PRIO_IRQOFF;              \
0047                                     \
0048         if (static_branch_unlikely(&gic_nonsecure_priorities))  \
0049             __prio = __GIC_PRIO_IRQOFF_NS;          \
0050                                     \
0051         __prio;                         \
0052     })
0053
0054 /* Additional SPSR bits not exposed in the UABI */
0055 #define PSR_MODE_THREAD_BIT (1 << 0)
0056 #define PSR_IL_BIT      (1 << 20)
0057
0058 /* AArch32-specific ptrace requests */
0059 #define COMPAT_PTRACE_GETREGS       12
0060 #define COMPAT_PTRACE_SETREGS       13
0061 #define COMPAT_PTRACE_GET_THREAD_AREA   22
0062 #define COMPAT_PTRACE_SET_SYSCALL   23
0063 #define COMPAT_PTRACE_GETVFPREGS    27
0064 #define COMPAT_PTRACE_SETVFPREGS    28
0065 #define COMPAT_PTRACE_GETHBPREGS    29
0066 #define COMPAT_PTRACE_SETHBPREGS    30
0067
0068 /* SPSR_ELx bits for exceptions taken from AArch32 */
0069 #define PSR_AA32_MODE_MASK  0x0000001f
0070 #define PSR_AA32_MODE_USR   0x00000010
0071 #define PSR_AA32_MODE_FIQ   0x00000011
0072 #define PSR_AA32_MODE_IRQ   0x00000012
0073 #define PSR_AA32_MODE_SVC   0x00000013
0074 #define PSR_AA32_MODE_ABT   0x00000017
0075 #define PSR_AA32_MODE_HYP   0x0000001a
0076 #define PSR_AA32_MODE_UND   0x0000001b
0077 #define PSR_AA32_MODE_SYS   0x0000001f
0078 #define PSR_AA32_T_BIT      0x00000020
0079 #define PSR_AA32_F_BIT      0x00000040
0080 #define PSR_AA32_I_BIT      0x00000080
0081 #define PSR_AA32_A_BIT      0x00000100
0082 #define PSR_AA32_E_BIT      0x00000200
0083 #define PSR_AA32_PAN_BIT    0x00400000
0084 #define PSR_AA32_SSBS_BIT   0x00800000
0085 #define PSR_AA32_DIT_BIT    0x01000000
0086 #define PSR_AA32_Q_BIT      0x08000000
0087 #define PSR_AA32_V_BIT      0x10000000
0088 #define PSR_AA32_C_BIT      0x20000000
0089 #define PSR_AA32_Z_BIT      0x40000000
0090 #define PSR_AA32_N_BIT      0x80000000
0091 #define PSR_AA32_IT_MASK    0x0600fc00  /* If-Then execution state mask */
0092 #define PSR_AA32_GE_MASK    0x000f0000
0093
0094 #ifdef CONFIG_CPU_BIG_ENDIAN
0095 #define PSR_AA32_ENDSTATE   PSR_AA32_E_BIT
0096 #else
0097 #define PSR_AA32_ENDSTATE   0
0098 #endif
0099
0100 /* AArch32 CPSR bits, as seen in AArch32 */
0101 #define COMPAT_PSR_DIT_BIT  0x00200000
0102
0103 /*
0104  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
0105  * process is located in memory.
0106  */
0107 #define COMPAT_PT_TEXT_ADDR     0x10000
0108 #define COMPAT_PT_DATA_ADDR     0x10004
0109 #define COMPAT_PT_TEXT_END_ADDR     0x10008
0110
0111 /*
0112  * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
0113  * a syscall -- i.e., its most recent entry into the kernel from
0114  * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
0115  *
0116  * This must have the value -1, for ABI compatibility with ptrace etc.
0117  */
0118 #define NO_SYSCALL (-1)
0119
0120 #ifndef __ASSEMBLY__
0121 #include <linux/bug.h>
0122 #include <linux/types.h>
0123
0124 /* sizeof(struct user) for AArch32 */
0125 #define COMPAT_USER_SZ  296
0126
0127 /* Architecturally defined mapping between AArch32 and AArch64 registers */
0128 #define compat_usr(x)   regs[(x)]
0129 #define compat_fp   regs[11]
0130 #define compat_sp   regs[13]
0131 #define compat_lr   regs[14]
0132 #define compat_sp_hyp   regs[15]
0133 #define compat_lr_irq   regs[16]
0134 #define compat_sp_irq   regs[17]
0135 #define compat_lr_svc   regs[18]
0136 #define compat_sp_svc   regs[19]
0137 #define compat_lr_abt   regs[20]
0138 #define compat_sp_abt   regs[21]
0139 #define compat_lr_und   regs[22]
0140 #define compat_sp_und   regs[23]
0141 #define compat_r8_fiq   regs[24]
0142 #define compat_r9_fiq   regs[25]
0143 #define compat_r10_fiq  regs[26]
0144 #define compat_r11_fiq  regs[27]
0145 #define compat_r12_fiq  regs[28]
0146 #define compat_sp_fiq   regs[29]
0147 #define compat_lr_fiq   regs[30]
0148
0149 static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
0150 {
0151     unsigned long pstate;
0152
0153     pstate = psr & ~COMPAT_PSR_DIT_BIT;
0154
0155     if (psr & COMPAT_PSR_DIT_BIT)
0156         pstate |= PSR_AA32_DIT_BIT;
0157
0158     return pstate;
0159 }
0160
0161 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
0162 {
0163     unsigned long psr;
0164
0165     psr = pstate & ~PSR_AA32_DIT_BIT;
0166
0167     if (pstate & PSR_AA32_DIT_BIT)
0168         psr |= COMPAT_PSR_DIT_BIT;
0169
0170     return psr;
0171 }
0172
0173 /*
0174  * This struct defines the way the registers are stored on the stack during an
0175  * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
0176  * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
0177  */
0178 struct pt_regs {
0179     union {
0180         struct user_pt_regs user_regs;
0181         struct {
0182             u64 regs[31];
0183             u64 sp;
0184             u64 pc;
0185             u64 pstate;
0186         };
0187     };
0188     u64 orig_x0;
0189 #ifdef __AARCH64EB__
0190     u32 unused2;
0191     s32 syscallno;
0192 #else
0193     s32 syscallno;
0194     u32 unused2;
0195 #endif
0196     u64 sdei_ttbr1;
0197     /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */
0198     u64 pmr_save;
0199     u64 stackframe[2];
0200
0201     /* Only valid for some EL1 exceptions. */
0202     u64 lockdep_hardirqs;
0203     u64 exit_rcu;
0204 };
0205
0206 static inline bool in_syscall(struct pt_regs const *regs)
0207 {
0208     return regs->syscallno != NO_SYSCALL;
0209 }
0210
0211 static inline void forget_syscall(struct pt_regs *regs)
0212 {
0213     regs->syscallno = NO_SYSCALL;
0214 }
0215
0216 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
0217
0218 #define arch_has_single_step()  (1)
0219
0220 #ifdef CONFIG_COMPAT
0221 #define compat_thumb_mode(regs) \
0222     (((regs)->pstate & PSR_AA32_T_BIT))
0223 #else
0224 #define compat_thumb_mode(regs) (0)
0225 #endif
0226
0227 #define user_mode(regs) \
0228     (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
0229
0230 #define compat_user_mode(regs)  \
0231     (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
0232      (PSR_MODE32_BIT | PSR_MODE_EL0t))
0233
0234 #define processor_mode(regs) \
0235     ((regs)->pstate & PSR_MODE_MASK)
0236
0237 #define irqs_priority_unmasked(regs)                    \
0238     (system_uses_irq_prio_masking() ?               \
0239         (regs)->pmr_save == GIC_PRIO_IRQON :            \
0240         true)
0241
0242 #define interrupts_enabled(regs)            \
0243     (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
0244
0245 #define fast_interrupts_enabled(regs) \
0246     (!((regs)->pstate & PSR_F_BIT))
0247
0248 static inline unsigned long user_stack_pointer(struct pt_regs *regs)
0249 {
0250     if (compat_user_mode(regs))
0251         return regs->compat_sp;
0252     return regs->sp;
0253 }
0254
0255 extern int regs_query_register_offset(const char *name);
0256 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
0257                            unsigned int n);
0258
0259 /**
0260  * regs_get_register() - get register value from its offset
0261  * @regs:   pt_regs from which register value is gotten
0262  * @offset: offset of the register.
0263  *
0264  * regs_get_register returns the value of a register whose offset from @regs.
0265  * The @offset is the offset of the register in struct pt_regs.
0266  * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
0267  */
0268 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
0269 {
0270     u64 val = 0;
0271
0272     WARN_ON(offset & 7);
0273
0274     offset >>= 3;
0275     switch (offset) {
0276     case 0 ... 30:
0277         val = regs->regs[offset];
0278         break;
0279     case offsetof(struct pt_regs, sp) >> 3:
0280         val = regs->sp;
0281         break;
0282     case offsetof(struct pt_regs, pc) >> 3:
0283         val = regs->pc;
0284         break;
0285     case offsetof(struct pt_regs, pstate) >> 3:
0286         val = regs->pstate;
0287         break;
0288     default:
0289         val = 0;
0290     }
0291
0292     return val;
0293 }
0294
0295 /*
0296  * Read a register given an architectural register index r.
0297  * This handles the common case where 31 means XZR, not SP.
0298  */
0299 static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
0300 {
0301     return (r == 31) ? 0 : regs->regs[r];
0302 }
0303
0304 /*
0305  * Write a register given an architectural register index r.
0306  * This handles the common case where 31 means XZR, not SP.
0307  */
0308 static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
0309                      unsigned long val)
0310 {
0311     if (r != 31)
0312         regs->regs[r] = val;
0313 }
0314
0315 /* Valid only for Kernel mode traps. */
0316 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
0317 {
0318     return regs->sp;
0319 }
0320
0321 static inline unsigned long regs_return_value(struct pt_regs *regs)
0322 {
0323     unsigned long val = regs->regs[0];
0324
0325     /*
0326      * Audit currently uses regs_return_value() instead of
0327      * syscall_get_return_value(). Apply the same sign-extension here until
0328      * audit is updated to use syscall_get_return_value().
0329      */
0330     if (compat_user_mode(regs))
0331         val = sign_extend64(val, 31);
0332
0333     return val;
0334 }
0335
0336 static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
0337 {
0338     regs->regs[0] = rc;
0339 }
0340
0341 /**
0342  * regs_get_kernel_argument() - get Nth function argument in kernel
0343  * @regs:   pt_regs of that context
0344  * @n:      function argument number (start from 0)
0345  *
0346  * regs_get_argument() returns @n th argument of the function call.
0347  *
0348  * Note that this chooses the most likely register mapping. In very rare
0349  * cases this may not return correct data, for example, if one of the
0350  * function parameters is 16 bytes or bigger. In such cases, we cannot
0351  * get access the parameter correctly and the register assignment of
0352  * subsequent parameters will be shifted.
0353  */
0354 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
0355                              unsigned int n)
0356 {
0357 #define NR_REG_ARGUMENTS 8
0358     if (n < NR_REG_ARGUMENTS)
0359         return pt_regs_read_reg(regs, n);
0360     return 0;
0361 }
0362
0363 /* We must avoid circular header include via sched.h */
0364 struct task_struct;
0365 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
0366
0367 static inline unsigned long instruction_pointer(struct pt_regs *regs)
0368 {
0369     return regs->pc;
0370 }
0371 static inline void instruction_pointer_set(struct pt_regs *regs,
0372         unsigned long val)
0373 {
0374     regs->pc = val;
0375 }
0376
0377 static inline unsigned long frame_pointer(struct pt_regs *regs)
0378 {
0379     return regs->regs[29];
0380 }
0381
0382 #define procedure_link_pointer(regs)    ((regs)->regs[30])
0383
0384 static inline void procedure_link_pointer_set(struct pt_regs *regs,
0385                        unsigned long val)
0386 {
0387     procedure_link_pointer(regs) = val;
0388 }
0389
0390 extern unsigned long profile_pc(struct pt_regs *regs);
0391
0392 #endif /* __ASSEMBLY__ */
0393 #endif