include/asm/pgtable-hwdef.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 ARM Ltd.
0004  */
0005 #ifndef __ASM_PGTABLE_HWDEF_H
0006 #define __ASM_PGTABLE_HWDEF_H
0007
0008 #include <asm/memory.h>
0009
0010 /*
0011  * Number of page-table levels required to address 'va_bits' wide
0012  * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
0013  * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
0014  *
0015  *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
0016  *
0017  * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
0018  *
0019  * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
0020  * due to build issues. So we open code DIV_ROUND_UP here:
0021  *
0022  *  ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
0023  *
0024  * which gets simplified as :
0025  */
0026 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
0027
0028 /*
0029  * Size mapped by an entry at level n ( 0 <= n <= 3)
0030  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
0031  * in the final page. The maximum number of translation levels supported by
0032  * the architecture is 4. Hence, starting at level n, we have further
0033  * ((4 - n) - 1) levels of translation excluding the offset within the page.
0034  * So, the total number of bits mapped by an entry at level n is :
0035  *
0036  *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
0037  *
0038  * Rearranging it a bit we get :
0039  *   (4 - n) * (PAGE_SHIFT - 3) + 3
0040  */
0041 #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
0042
0043 #define PTRS_PER_PTE        (1 << (PAGE_SHIFT - 3))
0044
0045 /*
0046  * PMD_SHIFT determines the size a level 2 page table entry can map.
0047  */
0048 #if CONFIG_PGTABLE_LEVELS > 2
0049 #define PMD_SHIFT       ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
0050 #define PMD_SIZE        (_AC(1, UL) << PMD_SHIFT)
0051 #define PMD_MASK        (~(PMD_SIZE-1))
0052 #define PTRS_PER_PMD        (1 << (PAGE_SHIFT - 3))
0053 #endif
0054
0055 /*
0056  * PUD_SHIFT determines the size a level 1 page table entry can map.
0057  */
0058 #if CONFIG_PGTABLE_LEVELS > 3
0059 #define PUD_SHIFT       ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
0060 #define PUD_SIZE        (_AC(1, UL) << PUD_SHIFT)
0061 #define PUD_MASK        (~(PUD_SIZE-1))
0062 #define PTRS_PER_PUD        (1 << (PAGE_SHIFT - 3))
0063 #endif
0064
0065 /*
0066  * PGDIR_SHIFT determines the size a top-level page table entry can map
0067  * (depending on the configuration, this level can be 0, 1 or 2).
0068  */
0069 #define PGDIR_SHIFT     ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
0070 #define PGDIR_SIZE      (_AC(1, UL) << PGDIR_SHIFT)
0071 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
0072 #define PTRS_PER_PGD        (1 << (VA_BITS - PGDIR_SHIFT))
0073
0074 /*
0075  * Contiguous page definitions.
0076  */
0077 #define CONT_PTE_SHIFT      (CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
0078 #define CONT_PTES       (1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
0079 #define CONT_PTE_SIZE       (CONT_PTES * PAGE_SIZE)
0080 #define CONT_PTE_MASK       (~(CONT_PTE_SIZE - 1))
0081
0082 #define CONT_PMD_SHIFT      (CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
0083 #define CONT_PMDS       (1 << (CONT_PMD_SHIFT - PMD_SHIFT))
0084 #define CONT_PMD_SIZE       (CONT_PMDS * PMD_SIZE)
0085 #define CONT_PMD_MASK       (~(CONT_PMD_SIZE - 1))
0086
0087 /*
0088  * Hardware page table definitions.
0089  *
0090  * Level 0 descriptor (P4D).
0091  */
0092 #define P4D_TYPE_TABLE      (_AT(p4dval_t, 3) << 0)
0093 #define P4D_TABLE_BIT       (_AT(p4dval_t, 1) << 1)
0094 #define P4D_TYPE_MASK       (_AT(p4dval_t, 3) << 0)
0095 #define P4D_TYPE_SECT       (_AT(p4dval_t, 1) << 0)
0096 #define P4D_SECT_RDONLY     (_AT(p4dval_t, 1) << 7)     /* AP[2] */
0097 #define P4D_TABLE_PXN       (_AT(p4dval_t, 1) << 59)
0098 #define P4D_TABLE_UXN       (_AT(p4dval_t, 1) << 60)
0099
0100 /*
0101  * Level 1 descriptor (PUD).
0102  */
0103 #define PUD_TYPE_TABLE      (_AT(pudval_t, 3) << 0)
0104 #define PUD_TABLE_BIT       (_AT(pudval_t, 1) << 1)
0105 #define PUD_TYPE_MASK       (_AT(pudval_t, 3) << 0)
0106 #define PUD_TYPE_SECT       (_AT(pudval_t, 1) << 0)
0107 #define PUD_SECT_RDONLY     (_AT(pudval_t, 1) << 7)     /* AP[2] */
0108 #define PUD_TABLE_PXN       (_AT(pudval_t, 1) << 59)
0109 #define PUD_TABLE_UXN       (_AT(pudval_t, 1) << 60)
0110
0111 /*
0112  * Level 2 descriptor (PMD).
0113  */
0114 #define PMD_TYPE_MASK       (_AT(pmdval_t, 3) << 0)
0115 #define PMD_TYPE_TABLE      (_AT(pmdval_t, 3) << 0)
0116 #define PMD_TYPE_SECT       (_AT(pmdval_t, 1) << 0)
0117 #define PMD_TABLE_BIT       (_AT(pmdval_t, 1) << 1)
0118
0119 /*
0120  * Section
0121  */
0122 #define PMD_SECT_VALID      (_AT(pmdval_t, 1) << 0)
0123 #define PMD_SECT_USER       (_AT(pmdval_t, 1) << 6)     /* AP[1] */
0124 #define PMD_SECT_RDONLY     (_AT(pmdval_t, 1) << 7)     /* AP[2] */
0125 #define PMD_SECT_S      (_AT(pmdval_t, 3) << 8)
0126 #define PMD_SECT_AF     (_AT(pmdval_t, 1) << 10)
0127 #define PMD_SECT_NG     (_AT(pmdval_t, 1) << 11)
0128 #define PMD_SECT_CONT       (_AT(pmdval_t, 1) << 52)
0129 #define PMD_SECT_PXN        (_AT(pmdval_t, 1) << 53)
0130 #define PMD_SECT_UXN        (_AT(pmdval_t, 1) << 54)
0131 #define PMD_TABLE_PXN       (_AT(pmdval_t, 1) << 59)
0132 #define PMD_TABLE_UXN       (_AT(pmdval_t, 1) << 60)
0133
0134 /*
0135  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
0136  */
0137 #define PMD_ATTRINDX(t)     (_AT(pmdval_t, (t)) << 2)
0138 #define PMD_ATTRINDX_MASK   (_AT(pmdval_t, 7) << 2)
0139
0140 /*
0141  * Level 3 descriptor (PTE).
0142  */
0143 #define PTE_VALID       (_AT(pteval_t, 1) << 0)
0144 #define PTE_TYPE_MASK       (_AT(pteval_t, 3) << 0)
0145 #define PTE_TYPE_PAGE       (_AT(pteval_t, 3) << 0)
0146 #define PTE_TABLE_BIT       (_AT(pteval_t, 1) << 1)
0147 #define PTE_USER        (_AT(pteval_t, 1) << 6)     /* AP[1] */
0148 #define PTE_RDONLY      (_AT(pteval_t, 1) << 7)     /* AP[2] */
0149 #define PTE_SHARED      (_AT(pteval_t, 3) << 8)     /* SH[1:0], inner shareable */
0150 #define PTE_AF          (_AT(pteval_t, 1) << 10)    /* Access Flag */
0151 #define PTE_NG          (_AT(pteval_t, 1) << 11)    /* nG */
0152 #define PTE_GP          (_AT(pteval_t, 1) << 50)    /* BTI guarded */
0153 #define PTE_DBM         (_AT(pteval_t, 1) << 51)    /* Dirty Bit Management */
0154 #define PTE_CONT        (_AT(pteval_t, 1) << 52)    /* Contiguous range */
0155 #define PTE_PXN         (_AT(pteval_t, 1) << 53)    /* Privileged XN */
0156 #define PTE_UXN         (_AT(pteval_t, 1) << 54)    /* User XN */
0157
0158 #define PTE_ADDR_LOW        (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
0159 #ifdef CONFIG_ARM64_PA_BITS_52
0160 #define PTE_ADDR_HIGH       (_AT(pteval_t, 0xf) << 12)
0161 #define PTE_ADDR_MASK       (PTE_ADDR_LOW | PTE_ADDR_HIGH)
0162 #else
0163 #define PTE_ADDR_MASK       PTE_ADDR_LOW
0164 #endif
0165
0166 /*
0167  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
0168  */
0169 #define PTE_ATTRINDX(t)     (_AT(pteval_t, (t)) << 2)
0170 #define PTE_ATTRINDX_MASK   (_AT(pteval_t, 7) << 2)
0171
0172 /*
0173  * Memory Attribute override for Stage-2 (MemAttr[3:0])
0174  */
0175 #define PTE_S2_MEMATTR(t)   (_AT(pteval_t, (t)) << 2)
0176
0177 /*
0178  * Highest possible physical address supported.
0179  */
0180 #define PHYS_MASK_SHIFT     (CONFIG_ARM64_PA_BITS)
0181 #define PHYS_MASK       ((UL(1) << PHYS_MASK_SHIFT) - 1)
0182
0183 #define TTBR_CNP_BIT        (UL(1) << 0)
0184
0185 /*
0186  * TCR flags.
0187  */
0188 #define TCR_T0SZ_OFFSET     0
0189 #define TCR_T1SZ_OFFSET     16
0190 #define TCR_T0SZ(x)     ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
0191 #define TCR_T1SZ(x)     ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
0192 #define TCR_TxSZ(x)     (TCR_T0SZ(x) | TCR_T1SZ(x))
0193 #define TCR_TxSZ_WIDTH      6
0194 #define TCR_T0SZ_MASK       (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
0195 #define TCR_T1SZ_MASK       (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
0196
0197 #define TCR_EPD0_SHIFT      7
0198 #define TCR_EPD0_MASK       (UL(1) << TCR_EPD0_SHIFT)
0199 #define TCR_IRGN0_SHIFT     8
0200 #define TCR_IRGN0_MASK      (UL(3) << TCR_IRGN0_SHIFT)
0201 #define TCR_IRGN0_NC        (UL(0) << TCR_IRGN0_SHIFT)
0202 #define TCR_IRGN0_WBWA      (UL(1) << TCR_IRGN0_SHIFT)
0203 #define TCR_IRGN0_WT        (UL(2) << TCR_IRGN0_SHIFT)
0204 #define TCR_IRGN0_WBnWA     (UL(3) << TCR_IRGN0_SHIFT)
0205
0206 #define TCR_EPD1_SHIFT      23
0207 #define TCR_EPD1_MASK       (UL(1) << TCR_EPD1_SHIFT)
0208 #define TCR_IRGN1_SHIFT     24
0209 #define TCR_IRGN1_MASK      (UL(3) << TCR_IRGN1_SHIFT)
0210 #define TCR_IRGN1_NC        (UL(0) << TCR_IRGN1_SHIFT)
0211 #define TCR_IRGN1_WBWA      (UL(1) << TCR_IRGN1_SHIFT)
0212 #define TCR_IRGN1_WT        (UL(2) << TCR_IRGN1_SHIFT)
0213 #define TCR_IRGN1_WBnWA     (UL(3) << TCR_IRGN1_SHIFT)
0214
0215 #define TCR_IRGN_NC     (TCR_IRGN0_NC | TCR_IRGN1_NC)
0216 #define TCR_IRGN_WBWA       (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
0217 #define TCR_IRGN_WT     (TCR_IRGN0_WT | TCR_IRGN1_WT)
0218 #define TCR_IRGN_WBnWA      (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
0219 #define TCR_IRGN_MASK       (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
0220
0221
0222 #define TCR_ORGN0_SHIFT     10
0223 #define TCR_ORGN0_MASK      (UL(3) << TCR_ORGN0_SHIFT)
0224 #define TCR_ORGN0_NC        (UL(0) << TCR_ORGN0_SHIFT)
0225 #define TCR_ORGN0_WBWA      (UL(1) << TCR_ORGN0_SHIFT)
0226 #define TCR_ORGN0_WT        (UL(2) << TCR_ORGN0_SHIFT)
0227 #define TCR_ORGN0_WBnWA     (UL(3) << TCR_ORGN0_SHIFT)
0228
0229 #define TCR_ORGN1_SHIFT     26
0230 #define TCR_ORGN1_MASK      (UL(3) << TCR_ORGN1_SHIFT)
0231 #define TCR_ORGN1_NC        (UL(0) << TCR_ORGN1_SHIFT)
0232 #define TCR_ORGN1_WBWA      (UL(1) << TCR_ORGN1_SHIFT)
0233 #define TCR_ORGN1_WT        (UL(2) << TCR_ORGN1_SHIFT)
0234 #define TCR_ORGN1_WBnWA     (UL(3) << TCR_ORGN1_SHIFT)
0235
0236 #define TCR_ORGN_NC     (TCR_ORGN0_NC | TCR_ORGN1_NC)
0237 #define TCR_ORGN_WBWA       (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
0238 #define TCR_ORGN_WT     (TCR_ORGN0_WT | TCR_ORGN1_WT)
0239 #define TCR_ORGN_WBnWA      (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
0240 #define TCR_ORGN_MASK       (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
0241
0242 #define TCR_SH0_SHIFT       12
0243 #define TCR_SH0_MASK        (UL(3) << TCR_SH0_SHIFT)
0244 #define TCR_SH0_INNER       (UL(3) << TCR_SH0_SHIFT)
0245
0246 #define TCR_SH1_SHIFT       28
0247 #define TCR_SH1_MASK        (UL(3) << TCR_SH1_SHIFT)
0248 #define TCR_SH1_INNER       (UL(3) << TCR_SH1_SHIFT)
0249 #define TCR_SHARED      (TCR_SH0_INNER | TCR_SH1_INNER)
0250
0251 #define TCR_TG0_SHIFT       14
0252 #define TCR_TG0_MASK        (UL(3) << TCR_TG0_SHIFT)
0253 #define TCR_TG0_4K      (UL(0) << TCR_TG0_SHIFT)
0254 #define TCR_TG0_64K     (UL(1) << TCR_TG0_SHIFT)
0255 #define TCR_TG0_16K     (UL(2) << TCR_TG0_SHIFT)
0256
0257 #define TCR_TG1_SHIFT       30
0258 #define TCR_TG1_MASK        (UL(3) << TCR_TG1_SHIFT)
0259 #define TCR_TG1_16K     (UL(1) << TCR_TG1_SHIFT)
0260 #define TCR_TG1_4K      (UL(2) << TCR_TG1_SHIFT)
0261 #define TCR_TG1_64K     (UL(3) << TCR_TG1_SHIFT)
0262
0263 #define TCR_IPS_SHIFT       32
0264 #define TCR_IPS_MASK        (UL(7) << TCR_IPS_SHIFT)
0265 #define TCR_A1          (UL(1) << 22)
0266 #define TCR_ASID16      (UL(1) << 36)
0267 #define TCR_TBI0        (UL(1) << 37)
0268 #define TCR_TBI1        (UL(1) << 38)
0269 #define TCR_HA          (UL(1) << 39)
0270 #define TCR_HD          (UL(1) << 40)
0271 #define TCR_TBID1       (UL(1) << 52)
0272 #define TCR_NFD0        (UL(1) << 53)
0273 #define TCR_NFD1        (UL(1) << 54)
0274 #define TCR_E0PD0       (UL(1) << 55)
0275 #define TCR_E0PD1       (UL(1) << 56)
0276 #define TCR_TCMA0       (UL(1) << 57)
0277 #define TCR_TCMA1       (UL(1) << 58)
0278
0279 /*
0280  * TTBR.
0281  */
0282 #ifdef CONFIG_ARM64_PA_BITS_52
0283 /*
0284  * TTBR_ELx[1] is RES0 in this configuration.
0285  */
0286 #define TTBR_BADDR_MASK_52  GENMASK_ULL(47, 2)
0287 #endif
0288
0289 #ifdef CONFIG_ARM64_VA_BITS_52
0290 /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
0291 #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
0292                  (UL(1) << (48 - PGDIR_SHIFT))) * 8)
0293 #endif
0294
0295 #endif