include/asm/mmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 ARM Ltd.
0004  */
0005 #ifndef __ASM_MMU_H
0006 #define __ASM_MMU_H
0007
0008 #include <asm/cputype.h>
0009
0010 #define MMCF_AARCH32    0x1 /* mm context flag for AArch32 executables */
0011 #define USER_ASID_BIT   48
0012 #define USER_ASID_FLAG  (UL(1) << USER_ASID_BIT)
0013 #define TTBR_ASID_MASK  (UL(0xffff) << 48)
0014
0015 #ifndef __ASSEMBLY__
0016
0017 #include <linux/refcount.h>
0018 #include <asm/cpufeature.h>
0019
0020 typedef struct {
0021     atomic64_t  id;
0022 #ifdef CONFIG_COMPAT
0023     void        *sigpage;
0024 #endif
0025     refcount_t  pinned;
0026     void        *vdso;
0027     unsigned long   flags;
0028 } mm_context_t;
0029
0030 /*
0031  * We use atomic64_read() here because the ASID for an 'mm_struct' can
0032  * be reallocated when scheduling one of its threads following a
0033  * rollover event (see new_context() and flush_context()). In this case,
0034  * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
0035  * may use a stale ASID. This is fine in principle as the new ASID is
0036  * guaranteed to be clean in the TLB, but the TLBI routines have to take
0037  * care to handle the following race:
0038  *
0039  *    CPU 0                    CPU 1                          CPU 2
0040  *
0041  *    // ptep_clear_flush(mm)
0042  *    xchg_relaxed(pte, 0)
0043  *    DSB ISHST
0044  *    old = ASID(mm)
0045  *         |                                                  <rollover>
0046  *         |                   new = new_context(mm)
0047  *         \-----------------> atomic_set(mm->context.id, new)
0048  *                             cpu_switch_mm(mm)
0049  *                             // Hardware walk of pte using new ASID
0050  *    TLBI(old)
0051  *
0052  * In this scenario, the barrier on CPU 0 and the dependency on CPU 1
0053  * ensure that the page-table walker on CPU 1 *must* see the invalid PTE
0054  * written by CPU 0.
0055  */
0056 #define ASID(mm)    (atomic64_read(&(mm)->context.id) & 0xffff)
0057
0058 static inline bool arm64_kernel_unmapped_at_el0(void)
0059 {
0060     return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
0061 }
0062
0063 extern void arm64_memblock_init(void);
0064 extern void paging_init(void);
0065 extern void bootmem_init(void);
0066 extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
0067 extern void init_mem_pgprot(void);
0068 extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
0069                    unsigned long virt, phys_addr_t size,
0070                    pgprot_t prot, bool page_mappings_only);
0071 extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
0072 extern void mark_linear_text_alias_ro(void);
0073 extern bool kaslr_requires_kpti(void);
0074
0075 #define INIT_MM_CONTEXT(name)   \
0076     .pgd = init_pg_dir,
0077
0078 #endif  /* !__ASSEMBLY__ */
0079 #endif