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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012,2013 - ARM Ltd
0004  * Author: Marc Zyngier <marc.zyngier@arm.com>
0005  *
0006  * Derived from arch/arm/include/kvm_emulate.h
0007  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
0008  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
0009  */
0010 
0011 #ifndef __ARM64_KVM_EMULATE_H__
0012 #define __ARM64_KVM_EMULATE_H__
0013 
0014 #include <linux/kvm_host.h>
0015 
0016 #include <asm/debug-monitors.h>
0017 #include <asm/esr.h>
0018 #include <asm/kvm_arm.h>
0019 #include <asm/kvm_hyp.h>
0020 #include <asm/ptrace.h>
0021 #include <asm/cputype.h>
0022 #include <asm/virt.h>
0023 
0024 #define CURRENT_EL_SP_EL0_VECTOR    0x0
0025 #define CURRENT_EL_SP_ELx_VECTOR    0x200
0026 #define LOWER_EL_AArch64_VECTOR     0x400
0027 #define LOWER_EL_AArch32_VECTOR     0x600
0028 
0029 enum exception_type {
0030     except_type_sync    = 0,
0031     except_type_irq     = 0x80,
0032     except_type_fiq     = 0x100,
0033     except_type_serror  = 0x180,
0034 };
0035 
0036 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
0037 void kvm_skip_instr32(struct kvm_vcpu *vcpu);
0038 
0039 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
0040 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
0041 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
0042 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
0043 void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
0044 
0045 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
0046 
0047 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
0048 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
0049 {
0050     return !(vcpu->arch.hcr_el2 & HCR_RW);
0051 }
0052 #else
0053 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
0054 {
0055     struct kvm *kvm = vcpu->kvm;
0056 
0057     WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED,
0058                    &kvm->arch.flags));
0059 
0060     return test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags);
0061 }
0062 #endif
0063 
0064 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
0065 {
0066     vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
0067     if (is_kernel_in_hyp_mode())
0068         vcpu->arch.hcr_el2 |= HCR_E2H;
0069     if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
0070         /* route synchronous external abort exceptions to EL2 */
0071         vcpu->arch.hcr_el2 |= HCR_TEA;
0072         /* trap error record accesses */
0073         vcpu->arch.hcr_el2 |= HCR_TERR;
0074     }
0075 
0076     if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
0077         vcpu->arch.hcr_el2 |= HCR_FWB;
0078     } else {
0079         /*
0080          * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
0081          * get set in SCTLR_EL1 such that we can detect when the guest
0082          * MMU gets turned on and do the necessary cache maintenance
0083          * then.
0084          */
0085         vcpu->arch.hcr_el2 |= HCR_TVM;
0086     }
0087 
0088     if (vcpu_el1_is_32bit(vcpu))
0089         vcpu->arch.hcr_el2 &= ~HCR_RW;
0090 
0091     if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
0092         vcpu_el1_is_32bit(vcpu))
0093         vcpu->arch.hcr_el2 |= HCR_TID2;
0094 
0095     if (kvm_has_mte(vcpu->kvm))
0096         vcpu->arch.hcr_el2 |= HCR_ATA;
0097 }
0098 
0099 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
0100 {
0101     return (unsigned long *)&vcpu->arch.hcr_el2;
0102 }
0103 
0104 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
0105 {
0106     vcpu->arch.hcr_el2 &= ~HCR_TWE;
0107     if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
0108         vcpu->kvm->arch.vgic.nassgireq)
0109         vcpu->arch.hcr_el2 &= ~HCR_TWI;
0110     else
0111         vcpu->arch.hcr_el2 |= HCR_TWI;
0112 }
0113 
0114 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
0115 {
0116     vcpu->arch.hcr_el2 |= HCR_TWE;
0117     vcpu->arch.hcr_el2 |= HCR_TWI;
0118 }
0119 
0120 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
0121 {
0122     vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
0123 }
0124 
0125 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
0126 {
0127     vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
0128 }
0129 
0130 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
0131 {
0132     return vcpu->arch.vsesr_el2;
0133 }
0134 
0135 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
0136 {
0137     vcpu->arch.vsesr_el2 = vsesr;
0138 }
0139 
0140 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
0141 {
0142     return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
0143 }
0144 
0145 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
0146 {
0147     return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
0148 }
0149 
0150 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
0151 {
0152     return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
0153 }
0154 
0155 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
0156 {
0157     if (vcpu_mode_is_32bit(vcpu))
0158         return kvm_condition_valid32(vcpu);
0159 
0160     return true;
0161 }
0162 
0163 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
0164 {
0165     *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
0166 }
0167 
0168 /*
0169  * vcpu_get_reg and vcpu_set_reg should always be passed a register number
0170  * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
0171  * AArch32 with banked registers.
0172  */
0173 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
0174                      u8 reg_num)
0175 {
0176     return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
0177 }
0178 
0179 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
0180                 unsigned long val)
0181 {
0182     if (reg_num != 31)
0183         vcpu_gp_regs(vcpu)->regs[reg_num] = val;
0184 }
0185 
0186 /*
0187  * The layout of SPSR for an AArch32 state is different when observed from an
0188  * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
0189  * view given an AArch64 view.
0190  *
0191  * In ARM DDI 0487E.a see:
0192  *
0193  * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
0194  * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
0195  * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
0196  *
0197  * Which show the following differences:
0198  *
0199  * | Bit | AA64 | AA32 | Notes                       |
0200  * +-----+------+------+-----------------------------|
0201  * | 24  | DIT  | J    | J is RES0 in ARMv8          |
0202  * | 21  | SS   | DIT  | SS doesn't exist in AArch32 |
0203  *
0204  * ... and all other bits are (currently) common.
0205  */
0206 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
0207 {
0208     const unsigned long overlap = BIT(24) | BIT(21);
0209     unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
0210 
0211     spsr &= ~overlap;
0212 
0213     spsr |= dit << 21;
0214 
0215     return spsr;
0216 }
0217 
0218 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
0219 {
0220     u32 mode;
0221 
0222     if (vcpu_mode_is_32bit(vcpu)) {
0223         mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
0224         return mode > PSR_AA32_MODE_USR;
0225     }
0226 
0227     mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
0228 
0229     return mode != PSR_MODE_EL0t;
0230 }
0231 
0232 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
0233 {
0234     return vcpu->arch.fault.esr_el2;
0235 }
0236 
0237 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
0238 {
0239     u64 esr = kvm_vcpu_get_esr(vcpu);
0240 
0241     if (esr & ESR_ELx_CV)
0242         return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
0243 
0244     return -1;
0245 }
0246 
0247 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
0248 {
0249     return vcpu->arch.fault.far_el2;
0250 }
0251 
0252 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
0253 {
0254     return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
0255 }
0256 
0257 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
0258 {
0259     return vcpu->arch.fault.disr_el1;
0260 }
0261 
0262 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
0263 {
0264     return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
0265 }
0266 
0267 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
0268 {
0269     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
0270 }
0271 
0272 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
0273 {
0274     return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
0275 }
0276 
0277 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
0278 {
0279     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
0280 }
0281 
0282 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
0283 {
0284     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
0285 }
0286 
0287 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
0288 {
0289     return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
0290 }
0291 
0292 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
0293 {
0294     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
0295 }
0296 
0297 /* Always check for S1PTW *before* using this. */
0298 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
0299 {
0300     return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
0301 }
0302 
0303 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
0304 {
0305     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
0306 }
0307 
0308 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
0309 {
0310     return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
0311 }
0312 
0313 /* This one is not specific to Data Abort */
0314 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
0315 {
0316     return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
0317 }
0318 
0319 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
0320 {
0321     return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
0322 }
0323 
0324 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
0325 {
0326     return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
0327 }
0328 
0329 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
0330 {
0331     return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
0332 }
0333 
0334 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
0335 {
0336     return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
0337 }
0338 
0339 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
0340 {
0341     return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;
0342 }
0343 
0344 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu)
0345 {
0346     return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL;
0347 }
0348 
0349 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
0350 {
0351     switch (kvm_vcpu_trap_get_fault(vcpu)) {
0352     case FSC_SEA:
0353     case FSC_SEA_TTW0:
0354     case FSC_SEA_TTW1:
0355     case FSC_SEA_TTW2:
0356     case FSC_SEA_TTW3:
0357     case FSC_SECC:
0358     case FSC_SECC_TTW0:
0359     case FSC_SECC_TTW1:
0360     case FSC_SECC_TTW2:
0361     case FSC_SECC_TTW3:
0362         return true;
0363     default:
0364         return false;
0365     }
0366 }
0367 
0368 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
0369 {
0370     u64 esr = kvm_vcpu_get_esr(vcpu);
0371     return ESR_ELx_SYS64_ISS_RT(esr);
0372 }
0373 
0374 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
0375 {
0376     if (kvm_vcpu_abt_iss1tw(vcpu))
0377         return true;
0378 
0379     if (kvm_vcpu_trap_is_iabt(vcpu))
0380         return false;
0381 
0382     return kvm_vcpu_dabt_iswrite(vcpu);
0383 }
0384 
0385 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
0386 {
0387     return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
0388 }
0389 
0390 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
0391 {
0392     if (vcpu_mode_is_32bit(vcpu)) {
0393         *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
0394     } else {
0395         u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
0396         sctlr |= SCTLR_ELx_EE;
0397         vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
0398     }
0399 }
0400 
0401 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
0402 {
0403     if (vcpu_mode_is_32bit(vcpu))
0404         return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
0405 
0406     if (vcpu_mode_priv(vcpu))
0407         return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
0408     else
0409         return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
0410 }
0411 
0412 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
0413                             unsigned long data,
0414                             unsigned int len)
0415 {
0416     if (kvm_vcpu_is_be(vcpu)) {
0417         switch (len) {
0418         case 1:
0419             return data & 0xff;
0420         case 2:
0421             return be16_to_cpu(data & 0xffff);
0422         case 4:
0423             return be32_to_cpu(data & 0xffffffff);
0424         default:
0425             return be64_to_cpu(data);
0426         }
0427     } else {
0428         switch (len) {
0429         case 1:
0430             return data & 0xff;
0431         case 2:
0432             return le16_to_cpu(data & 0xffff);
0433         case 4:
0434             return le32_to_cpu(data & 0xffffffff);
0435         default:
0436             return le64_to_cpu(data);
0437         }
0438     }
0439 
0440     return data;        /* Leave LE untouched */
0441 }
0442 
0443 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
0444                             unsigned long data,
0445                             unsigned int len)
0446 {
0447     if (kvm_vcpu_is_be(vcpu)) {
0448         switch (len) {
0449         case 1:
0450             return data & 0xff;
0451         case 2:
0452             return cpu_to_be16(data & 0xffff);
0453         case 4:
0454             return cpu_to_be32(data & 0xffffffff);
0455         default:
0456             return cpu_to_be64(data);
0457         }
0458     } else {
0459         switch (len) {
0460         case 1:
0461             return data & 0xff;
0462         case 2:
0463             return cpu_to_le16(data & 0xffff);
0464         case 4:
0465             return cpu_to_le32(data & 0xffffffff);
0466         default:
0467             return cpu_to_le64(data);
0468         }
0469     }
0470 
0471     return data;        /* Leave LE untouched */
0472 }
0473 
0474 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
0475 {
0476     WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION));
0477     vcpu_set_flag(vcpu, INCREMENT_PC);
0478 }
0479 
0480 #define kvm_pend_exception(v, e)                    \
0481     do {                                \
0482         WARN_ON(vcpu_get_flag((v), INCREMENT_PC));      \
0483         vcpu_set_flag((v), PENDING_EXCEPTION);          \
0484         vcpu_set_flag((v), e);                  \
0485     } while (0)
0486 
0487 
0488 static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
0489 {
0490     return test_bit(feature, vcpu->arch.features);
0491 }
0492 
0493 #endif /* __ARM64_KVM_EMULATE_H__ */
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