include/asm/kvm_arm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012,2013 - ARM Ltd
0004  * Author: Marc Zyngier <marc.zyngier@arm.com>
0005  */
0006
0007 #ifndef __ARM64_KVM_ARM_H__
0008 #define __ARM64_KVM_ARM_H__
0009
0010 #include <asm/esr.h>
0011 #include <asm/memory.h>
0012 #include <asm/types.h>
0013
0014 /* Hyp Configuration Register (HCR) bits */
0015
0016 #define HCR_TID5    (UL(1) << 58)
0017 #define HCR_DCT     (UL(1) << 57)
0018 #define HCR_ATA_SHIFT   56
0019 #define HCR_ATA     (UL(1) << HCR_ATA_SHIFT)
0020 #define HCR_AMVOFFEN    (UL(1) << 51)
0021 #define HCR_FIEN    (UL(1) << 47)
0022 #define HCR_FWB     (UL(1) << 46)
0023 #define HCR_API     (UL(1) << 41)
0024 #define HCR_APK     (UL(1) << 40)
0025 #define HCR_TEA     (UL(1) << 37)
0026 #define HCR_TERR    (UL(1) << 36)
0027 #define HCR_TLOR    (UL(1) << 35)
0028 #define HCR_E2H     (UL(1) << 34)
0029 #define HCR_ID      (UL(1) << 33)
0030 #define HCR_CD      (UL(1) << 32)
0031 #define HCR_RW_SHIFT    31
0032 #define HCR_RW      (UL(1) << HCR_RW_SHIFT)
0033 #define HCR_TRVM    (UL(1) << 30)
0034 #define HCR_HCD     (UL(1) << 29)
0035 #define HCR_TDZ     (UL(1) << 28)
0036 #define HCR_TGE     (UL(1) << 27)
0037 #define HCR_TVM     (UL(1) << 26)
0038 #define HCR_TTLB    (UL(1) << 25)
0039 #define HCR_TPU     (UL(1) << 24)
0040 #define HCR_TPC     (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
0041 #define HCR_TSW     (UL(1) << 22)
0042 #define HCR_TACR    (UL(1) << 21)
0043 #define HCR_TIDCP   (UL(1) << 20)
0044 #define HCR_TSC     (UL(1) << 19)
0045 #define HCR_TID3    (UL(1) << 18)
0046 #define HCR_TID2    (UL(1) << 17)
0047 #define HCR_TID1    (UL(1) << 16)
0048 #define HCR_TID0    (UL(1) << 15)
0049 #define HCR_TWE     (UL(1) << 14)
0050 #define HCR_TWI     (UL(1) << 13)
0051 #define HCR_DC      (UL(1) << 12)
0052 #define HCR_BSU     (3 << 10)
0053 #define HCR_BSU_IS  (UL(1) << 10)
0054 #define HCR_FB      (UL(1) << 9)
0055 #define HCR_VSE     (UL(1) << 8)
0056 #define HCR_VI      (UL(1) << 7)
0057 #define HCR_VF      (UL(1) << 6)
0058 #define HCR_AMO     (UL(1) << 5)
0059 #define HCR_IMO     (UL(1) << 4)
0060 #define HCR_FMO     (UL(1) << 3)
0061 #define HCR_PTW     (UL(1) << 2)
0062 #define HCR_SWIO    (UL(1) << 1)
0063 #define HCR_VM      (UL(1) << 0)
0064 #define HCR_RES0    ((UL(1) << 48) | (UL(1) << 39))
0065
0066 /*
0067  * The bits we set in HCR:
0068  * TLOR:    Trap LORegion register accesses
0069  * RW:      64bit by default, can be overridden for 32bit VMs
0070  * TACR:    Trap ACTLR
0071  * TSC:     Trap SMC
0072  * TSW:     Trap cache operations by set/way
0073  * TWE:     Trap WFE
0074  * TWI:     Trap WFI
0075  * TIDCP:   Trap L2CTLR/L2ECTLR
0076  * BSU_IS:  Upgrade barriers to the inner shareable domain
0077  * FB:      Force broadcast of all maintenance operations
0078  * AMO:     Override CPSR.A and enable signaling with VA
0079  * IMO:     Override CPSR.I and enable signaling with VI
0080  * FMO:     Override CPSR.F and enable signaling with VF
0081  * SWIO:    Turn set/way invalidates into set/way clean+invalidate
0082  * PTW:     Take a stage2 fault if a stage1 walk steps in device memory
0083  * TID3:    Trap EL1 reads of group 3 ID registers
0084  */
0085 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
0086              HCR_BSU_IS | HCR_FB | HCR_TACR | \
0087              HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
0088              HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 )
0089 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
0090 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
0091 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
0092 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
0093
0094 /* TCR_EL2 Registers bits */
0095 #define TCR_EL2_RES1        ((1U << 31) | (1 << 23))
0096 #define TCR_EL2_TBI     (1 << 20)
0097 #define TCR_EL2_PS_SHIFT    16
0098 #define TCR_EL2_PS_MASK     (7 << TCR_EL2_PS_SHIFT)
0099 #define TCR_EL2_PS_40B      (2 << TCR_EL2_PS_SHIFT)
0100 #define TCR_EL2_TG0_MASK    TCR_TG0_MASK
0101 #define TCR_EL2_SH0_MASK    TCR_SH0_MASK
0102 #define TCR_EL2_ORGN0_MASK  TCR_ORGN0_MASK
0103 #define TCR_EL2_IRGN0_MASK  TCR_IRGN0_MASK
0104 #define TCR_EL2_T0SZ_MASK   0x3f
0105 #define TCR_EL2_MASK    (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
0106              TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)
0107
0108 /* VTCR_EL2 Registers bits */
0109 #define VTCR_EL2_RES1       (1U << 31)
0110 #define VTCR_EL2_HD     (1 << 22)
0111 #define VTCR_EL2_HA     (1 << 21)
0112 #define VTCR_EL2_PS_SHIFT   TCR_EL2_PS_SHIFT
0113 #define VTCR_EL2_PS_MASK    TCR_EL2_PS_MASK
0114 #define VTCR_EL2_TG0_MASK   TCR_TG0_MASK
0115 #define VTCR_EL2_TG0_4K     TCR_TG0_4K
0116 #define VTCR_EL2_TG0_16K    TCR_TG0_16K
0117 #define VTCR_EL2_TG0_64K    TCR_TG0_64K
0118 #define VTCR_EL2_SH0_MASK   TCR_SH0_MASK
0119 #define VTCR_EL2_SH0_INNER  TCR_SH0_INNER
0120 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
0121 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
0122 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
0123 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
0124 #define VTCR_EL2_SL0_SHIFT  6
0125 #define VTCR_EL2_SL0_MASK   (3 << VTCR_EL2_SL0_SHIFT)
0126 #define VTCR_EL2_T0SZ_MASK  0x3f
0127 #define VTCR_EL2_VS_SHIFT   19
0128 #define VTCR_EL2_VS_8BIT    (0 << VTCR_EL2_VS_SHIFT)
0129 #define VTCR_EL2_VS_16BIT   (1 << VTCR_EL2_VS_SHIFT)
0130
0131 #define VTCR_EL2_T0SZ(x)    TCR_T0SZ(x)
0132
0133 /*
0134  * We configure the Stage-2 page tables to always restrict the IPA space to be
0135  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
0136  * not known to exist and will break with this configuration.
0137  *
0138  * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
0139  *
0140  * Note that when using 4K pages, we concatenate two first level page tables
0141  * together. With 16K pages, we concatenate 16 first level page tables.
0142  *
0143  */
0144
0145 #define VTCR_EL2_COMMON_BITS    (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
0146                  VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
0147
0148 /*
0149  * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
0150  * Interestingly, it depends on the page size.
0151  * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
0152  *
0153  *  -----------------------------------------
0154  *  | Entry level       |  4K  | 16K/64K |
0155  *  ------------------------------------------
0156  *  | Level: 0      |  2   |   -     |
0157  *  ------------------------------------------
0158  *  | Level: 1      |  1   |   2     |
0159  *  ------------------------------------------
0160  *  | Level: 2      |  0   |   1     |
0161  *  ------------------------------------------
0162  *  | Level: 3      |  -   |   0     |
0163  *  ------------------------------------------
0164  *
0165  * The table roughly translates to :
0166  *
0167  *  SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
0168  *
0169  * Where TGRAN_SL0_BASE is a magic number depending on the page size:
0170  *  TGRAN_SL0_BASE(4K) = 2
0171  *  TGRAN_SL0_BASE(16K) = 3
0172  *  TGRAN_SL0_BASE(64K) = 3
0173  * provided we take care of ruling out the unsupported cases and
0174  * Entry_Level = 4 - Number_of_levels.
0175  *
0176  */
0177 #ifdef CONFIG_ARM64_64K_PAGES
0178
0179 #define VTCR_EL2_TGRAN          VTCR_EL2_TG0_64K
0180 #define VTCR_EL2_TGRAN_SL0_BASE     3UL
0181
0182 #elif defined(CONFIG_ARM64_16K_PAGES)
0183
0184 #define VTCR_EL2_TGRAN          VTCR_EL2_TG0_16K
0185 #define VTCR_EL2_TGRAN_SL0_BASE     3UL
0186
0187 #else   /* 4K */
0188
0189 #define VTCR_EL2_TGRAN          VTCR_EL2_TG0_4K
0190 #define VTCR_EL2_TGRAN_SL0_BASE     2UL
0191
0192 #endif
0193
0194 #define VTCR_EL2_LVLS_TO_SL0(levels)    \
0195     ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
0196 #define VTCR_EL2_SL0_TO_LVLS(sl0)   \
0197     ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
0198 #define VTCR_EL2_LVLS(vtcr)     \
0199     VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
0200
0201 #define VTCR_EL2_FLAGS          (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
0202 #define VTCR_EL2_IPA(vtcr)      (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
0203
0204 /*
0205  * ARM VMSAv8-64 defines an algorithm for finding the translation table
0206  * descriptors in section D4.2.8 in ARM DDI 0487C.a.
0207  *
0208  * The algorithm defines the expectations on the translation table
0209  * addresses for each level, based on PAGE_SIZE, entry level
0210  * and the translation table size (T0SZ). The variable "x" in the
0211  * algorithm determines the alignment of a table base address at a given
0212  * level and thus determines the alignment of VTTBR:BADDR for stage2
0213  * page table entry level.
0214  * Since the number of bits resolved at the entry level could vary
0215  * depending on the T0SZ, the value of "x" is defined based on a
0216  * Magic constant for a given PAGE_SIZE and Entry Level. The
0217  * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
0218  * x = PAGE_SHIFT).
0219  *
0220  * The value of "x" for entry level is calculated as :
0221  *    x = Magic_N - T0SZ
0222  *
0223  * where Magic_N is an integer depending on the page size and the entry
0224  * level of the page table as below:
0225  *
0226  *  --------------------------------------------
0227  *  | Entry level       |  4K    16K   64K |
0228  *  --------------------------------------------
0229  *  | Level: 0 (4 levels)   | 28   |  -  |  -  |
0230  *  --------------------------------------------
0231  *  | Level: 1 (3 levels)   | 37   | 31  | 25  |
0232  *  --------------------------------------------
0233  *  | Level: 2 (2 levels)   | 46   | 42  | 38  |
0234  *  --------------------------------------------
0235  *  | Level: 3 (1 level)    | -    | 53  | 51  |
0236  *  --------------------------------------------
0237  *
0238  * We have a magic formula for the Magic_N below:
0239  *
0240  *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
0241  *
0242  * where Number_of_levels = (4 - Level). We are only interested in the
0243  * value for Entry_Level for the stage2 page table.
0244  *
0245  * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
0246  *
0247  *  x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
0248  *    = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
0249  *
0250  * Here is one way to explain the Magic Formula:
0251  *
0252  *  x = log2(Size_of_Entry_Level_Table)
0253  *
0254  * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
0255  * PAGE_SHIFT bits in the PTE, we have :
0256  *
0257  *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
0258  *           = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
0259  *  where n = number of levels, and since each pointer is 8bytes, we have:
0260  *
0261  *  x = Bits_Entry_Level + 3
0262  *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
0263  *
0264  * The only constraint here is that, we have to find the number of page table
0265  * levels for a given IPA size (which we do, see stage2_pt_levels())
0266  */
0267 #define ARM64_VTTBR_X(ipa, levels)  ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
0268
0269 #define VTTBR_CNP_BIT     (UL(1))
0270 #define VTTBR_VMID_SHIFT  (UL(48))
0271 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
0272
0273 /* Hyp System Trap Register */
0274 #define HSTR_EL2_T(x)   (1 << x)
0275
0276 /* Hyp Coprocessor Trap Register Shifts */
0277 #define CPTR_EL2_TFP_SHIFT 10
0278
0279 /* Hyp Coprocessor Trap Register */
0280 #define CPTR_EL2_TCPAC  (1U << 31)
0281 #define CPTR_EL2_TAM    (1 << 30)
0282 #define CPTR_EL2_TTA    (1 << 20)
0283 #define CPTR_EL2_TSM    (1 << 12)
0284 #define CPTR_EL2_TFP    (1 << CPTR_EL2_TFP_SHIFT)
0285 #define CPTR_EL2_TZ (1 << 8)
0286 #define CPTR_NVHE_EL2_RES1  0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */
0287 #define CPTR_EL2_DEFAULT    CPTR_NVHE_EL2_RES1
0288 #define CPTR_NVHE_EL2_RES0  (GENMASK(63, 32) |  \
0289                  GENMASK(29, 21) |  \
0290                  GENMASK(19, 14) |  \
0291                  BIT(11))
0292
0293 /* Hyp Debug Configuration Register bits */
0294 #define MDCR_EL2_E2TB_MASK  (UL(0x3))
0295 #define MDCR_EL2_E2TB_SHIFT (UL(24))
0296 #define MDCR_EL2_HPMFZS     (UL(1) << 36)
0297 #define MDCR_EL2_HPMFZO     (UL(1) << 29)
0298 #define MDCR_EL2_MTPME      (UL(1) << 28)
0299 #define MDCR_EL2_TDCC       (UL(1) << 27)
0300 #define MDCR_EL2_HLP        (UL(1) << 26)
0301 #define MDCR_EL2_HCCD       (UL(1) << 23)
0302 #define MDCR_EL2_TTRF       (UL(1) << 19)
0303 #define MDCR_EL2_HPMD       (UL(1) << 17)
0304 #define MDCR_EL2_TPMS       (UL(1) << 14)
0305 #define MDCR_EL2_E2PB_MASK  (UL(0x3))
0306 #define MDCR_EL2_E2PB_SHIFT (UL(12))
0307 #define MDCR_EL2_TDRA       (UL(1) << 11)
0308 #define MDCR_EL2_TDOSA      (UL(1) << 10)
0309 #define MDCR_EL2_TDA        (UL(1) << 9)
0310 #define MDCR_EL2_TDE        (UL(1) << 8)
0311 #define MDCR_EL2_HPME       (UL(1) << 7)
0312 #define MDCR_EL2_TPM        (UL(1) << 6)
0313 #define MDCR_EL2_TPMCR      (UL(1) << 5)
0314 #define MDCR_EL2_HPMN_MASK  (UL(0x1F))
0315 #define MDCR_EL2_RES0       (GENMASK(63, 37) |  \
0316                  GENMASK(35, 30) |  \
0317                  GENMASK(25, 24) |  \
0318                  GENMASK(22, 20) |  \
0319                  BIT(18) |      \
0320                  GENMASK(16, 15))
0321
0322 /* For compatibility with fault code shared with 32-bit */
0323 #define FSC_FAULT   ESR_ELx_FSC_FAULT
0324 #define FSC_ACCESS  ESR_ELx_FSC_ACCESS
0325 #define FSC_PERM    ESR_ELx_FSC_PERM
0326 #define FSC_SEA     ESR_ELx_FSC_EXTABT
0327 #define FSC_SEA_TTW0    (0x14)
0328 #define FSC_SEA_TTW1    (0x15)
0329 #define FSC_SEA_TTW2    (0x16)
0330 #define FSC_SEA_TTW3    (0x17)
0331 #define FSC_SECC    (0x18)
0332 #define FSC_SECC_TTW0   (0x1c)
0333 #define FSC_SECC_TTW1   (0x1d)
0334 #define FSC_SECC_TTW2   (0x1e)
0335 #define FSC_SECC_TTW3   (0x1f)
0336
0337 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
0338 #define HPFAR_MASK  (~UL(0xf))
0339 /*
0340  * We have
0341  *  PAR [PA_Shift - 1   : 12] = PA  [PA_Shift - 1 : 12]
0342  *  HPFAR   [PA_Shift - 9   : 4]  = FIPA    [PA_Shift - 1 : 12]
0343  */
0344 #define PAR_TO_HPFAR(par)       \
0345     (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
0346
0347 #define ECN(x) { ESR_ELx_EC_##x, #x }
0348
0349 #define kvm_arm_exception_class \
0350     ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
0351     ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
0352     ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
0353     ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
0354     ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
0355     ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
0356     ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
0357     ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
0358     ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
0359
0360 #define CPACR_EL1_TTA       (1 << 28)
0361 #define CPACR_EL1_DEFAULT   (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |\
0362                  CPACR_EL1_ZEN_EL1EN)
0363
0364 #endif /* __ARM64_KVM_ARM_H__ */