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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013 Huawei Ltd.
0004  * Author: Jiang Liu <liuj97@gmail.com>
0005  *
0006  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
0007  */
0008 #ifndef __ASM_INSN_H
0009 #define __ASM_INSN_H
0010 #include <linux/build_bug.h>
0011 #include <linux/types.h>
0012 
0013 #include <asm/insn-def.h>
0014 
0015 #ifndef __ASSEMBLY__
0016 /*
0017  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
0018  * Section C3.1 "A64 instruction index by encoding":
0019  * AArch64 main encoding table
0020  *  Bit position
0021  *   28 27 26 25    Encoding Group
0022  *   0  0  -  -     Unallocated
0023  *   1  0  0  -     Data processing, immediate
0024  *   1  0  1  -     Branch, exception generation and system instructions
0025  *   -  1  -  0     Loads and stores
0026  *   -  1  0  1     Data processing - register
0027  *   0  1  1  1     Data processing - SIMD and floating point
0028  *   1  1  1  1     Data processing - SIMD and floating point
0029  * "-" means "don't care"
0030  */
0031 enum aarch64_insn_encoding_class {
0032     AARCH64_INSN_CLS_UNKNOWN,   /* UNALLOCATED */
0033     AARCH64_INSN_CLS_SVE,       /* SVE instructions */
0034     AARCH64_INSN_CLS_DP_IMM,    /* Data processing - immediate */
0035     AARCH64_INSN_CLS_DP_REG,    /* Data processing - register */
0036     AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
0037     AARCH64_INSN_CLS_LDST,      /* Loads and stores */
0038     AARCH64_INSN_CLS_BR_SYS,    /* Branch, exception generation and
0039                      * system instructions */
0040 };
0041 
0042 enum aarch64_insn_hint_cr_op {
0043     AARCH64_INSN_HINT_NOP   = 0x0 << 5,
0044     AARCH64_INSN_HINT_YIELD = 0x1 << 5,
0045     AARCH64_INSN_HINT_WFE   = 0x2 << 5,
0046     AARCH64_INSN_HINT_WFI   = 0x3 << 5,
0047     AARCH64_INSN_HINT_SEV   = 0x4 << 5,
0048     AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
0049 
0050     AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
0051     AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
0052     AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
0053     AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
0054     AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
0055     AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
0056     AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
0057     AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
0058     AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
0059     AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
0060     AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
0061     AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
0062     AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
0063 
0064     AARCH64_INSN_HINT_ESB  = 0x10 << 5,
0065     AARCH64_INSN_HINT_PSB  = 0x11 << 5,
0066     AARCH64_INSN_HINT_TSB  = 0x12 << 5,
0067     AARCH64_INSN_HINT_CSDB = 0x14 << 5,
0068     AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
0069 
0070     AARCH64_INSN_HINT_BTI   = 0x20 << 5,
0071     AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
0072     AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
0073     AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
0074 };
0075 
0076 enum aarch64_insn_imm_type {
0077     AARCH64_INSN_IMM_ADR,
0078     AARCH64_INSN_IMM_26,
0079     AARCH64_INSN_IMM_19,
0080     AARCH64_INSN_IMM_16,
0081     AARCH64_INSN_IMM_14,
0082     AARCH64_INSN_IMM_12,
0083     AARCH64_INSN_IMM_9,
0084     AARCH64_INSN_IMM_7,
0085     AARCH64_INSN_IMM_6,
0086     AARCH64_INSN_IMM_S,
0087     AARCH64_INSN_IMM_R,
0088     AARCH64_INSN_IMM_N,
0089     AARCH64_INSN_IMM_MAX
0090 };
0091 
0092 enum aarch64_insn_register_type {
0093     AARCH64_INSN_REGTYPE_RT,
0094     AARCH64_INSN_REGTYPE_RN,
0095     AARCH64_INSN_REGTYPE_RT2,
0096     AARCH64_INSN_REGTYPE_RM,
0097     AARCH64_INSN_REGTYPE_RD,
0098     AARCH64_INSN_REGTYPE_RA,
0099     AARCH64_INSN_REGTYPE_RS,
0100 };
0101 
0102 enum aarch64_insn_register {
0103     AARCH64_INSN_REG_0  = 0,
0104     AARCH64_INSN_REG_1  = 1,
0105     AARCH64_INSN_REG_2  = 2,
0106     AARCH64_INSN_REG_3  = 3,
0107     AARCH64_INSN_REG_4  = 4,
0108     AARCH64_INSN_REG_5  = 5,
0109     AARCH64_INSN_REG_6  = 6,
0110     AARCH64_INSN_REG_7  = 7,
0111     AARCH64_INSN_REG_8  = 8,
0112     AARCH64_INSN_REG_9  = 9,
0113     AARCH64_INSN_REG_10 = 10,
0114     AARCH64_INSN_REG_11 = 11,
0115     AARCH64_INSN_REG_12 = 12,
0116     AARCH64_INSN_REG_13 = 13,
0117     AARCH64_INSN_REG_14 = 14,
0118     AARCH64_INSN_REG_15 = 15,
0119     AARCH64_INSN_REG_16 = 16,
0120     AARCH64_INSN_REG_17 = 17,
0121     AARCH64_INSN_REG_18 = 18,
0122     AARCH64_INSN_REG_19 = 19,
0123     AARCH64_INSN_REG_20 = 20,
0124     AARCH64_INSN_REG_21 = 21,
0125     AARCH64_INSN_REG_22 = 22,
0126     AARCH64_INSN_REG_23 = 23,
0127     AARCH64_INSN_REG_24 = 24,
0128     AARCH64_INSN_REG_25 = 25,
0129     AARCH64_INSN_REG_26 = 26,
0130     AARCH64_INSN_REG_27 = 27,
0131     AARCH64_INSN_REG_28 = 28,
0132     AARCH64_INSN_REG_29 = 29,
0133     AARCH64_INSN_REG_FP = 29, /* Frame pointer */
0134     AARCH64_INSN_REG_30 = 30,
0135     AARCH64_INSN_REG_LR = 30, /* Link register */
0136     AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
0137     AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
0138 };
0139 
0140 enum aarch64_insn_special_register {
0141     AARCH64_INSN_SPCLREG_SPSR_EL1   = 0xC200,
0142     AARCH64_INSN_SPCLREG_ELR_EL1    = 0xC201,
0143     AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
0144     AARCH64_INSN_SPCLREG_SPSEL  = 0xC210,
0145     AARCH64_INSN_SPCLREG_CURRENTEL  = 0xC212,
0146     AARCH64_INSN_SPCLREG_DAIF   = 0xDA11,
0147     AARCH64_INSN_SPCLREG_NZCV   = 0xDA10,
0148     AARCH64_INSN_SPCLREG_FPCR   = 0xDA20,
0149     AARCH64_INSN_SPCLREG_DSPSR_EL0  = 0xDA28,
0150     AARCH64_INSN_SPCLREG_DLR_EL0    = 0xDA29,
0151     AARCH64_INSN_SPCLREG_SPSR_EL2   = 0xE200,
0152     AARCH64_INSN_SPCLREG_ELR_EL2    = 0xE201,
0153     AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
0154     AARCH64_INSN_SPCLREG_SPSR_INQ   = 0xE218,
0155     AARCH64_INSN_SPCLREG_SPSR_ABT   = 0xE219,
0156     AARCH64_INSN_SPCLREG_SPSR_UND   = 0xE21A,
0157     AARCH64_INSN_SPCLREG_SPSR_FIQ   = 0xE21B,
0158     AARCH64_INSN_SPCLREG_SPSR_EL3   = 0xF200,
0159     AARCH64_INSN_SPCLREG_ELR_EL3    = 0xF201,
0160     AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
0161 };
0162 
0163 enum aarch64_insn_variant {
0164     AARCH64_INSN_VARIANT_32BIT,
0165     AARCH64_INSN_VARIANT_64BIT
0166 };
0167 
0168 enum aarch64_insn_condition {
0169     AARCH64_INSN_COND_EQ = 0x0, /* == */
0170     AARCH64_INSN_COND_NE = 0x1, /* != */
0171     AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
0172     AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
0173     AARCH64_INSN_COND_MI = 0x4, /* < 0 */
0174     AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
0175     AARCH64_INSN_COND_VS = 0x6, /* overflow */
0176     AARCH64_INSN_COND_VC = 0x7, /* no overflow */
0177     AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
0178     AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
0179     AARCH64_INSN_COND_GE = 0xa, /* signed >= */
0180     AARCH64_INSN_COND_LT = 0xb, /* signed < */
0181     AARCH64_INSN_COND_GT = 0xc, /* signed > */
0182     AARCH64_INSN_COND_LE = 0xd, /* signed <= */
0183     AARCH64_INSN_COND_AL = 0xe, /* always */
0184 };
0185 
0186 enum aarch64_insn_branch_type {
0187     AARCH64_INSN_BRANCH_NOLINK,
0188     AARCH64_INSN_BRANCH_LINK,
0189     AARCH64_INSN_BRANCH_RETURN,
0190     AARCH64_INSN_BRANCH_COMP_ZERO,
0191     AARCH64_INSN_BRANCH_COMP_NONZERO,
0192 };
0193 
0194 enum aarch64_insn_size_type {
0195     AARCH64_INSN_SIZE_8,
0196     AARCH64_INSN_SIZE_16,
0197     AARCH64_INSN_SIZE_32,
0198     AARCH64_INSN_SIZE_64,
0199 };
0200 
0201 enum aarch64_insn_ldst_type {
0202     AARCH64_INSN_LDST_LOAD_REG_OFFSET,
0203     AARCH64_INSN_LDST_STORE_REG_OFFSET,
0204     AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
0205     AARCH64_INSN_LDST_STORE_IMM_OFFSET,
0206     AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
0207     AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
0208     AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
0209     AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
0210     AARCH64_INSN_LDST_LOAD_EX,
0211     AARCH64_INSN_LDST_LOAD_ACQ_EX,
0212     AARCH64_INSN_LDST_STORE_EX,
0213     AARCH64_INSN_LDST_STORE_REL_EX,
0214 };
0215 
0216 enum aarch64_insn_adsb_type {
0217     AARCH64_INSN_ADSB_ADD,
0218     AARCH64_INSN_ADSB_SUB,
0219     AARCH64_INSN_ADSB_ADD_SETFLAGS,
0220     AARCH64_INSN_ADSB_SUB_SETFLAGS
0221 };
0222 
0223 enum aarch64_insn_movewide_type {
0224     AARCH64_INSN_MOVEWIDE_ZERO,
0225     AARCH64_INSN_MOVEWIDE_KEEP,
0226     AARCH64_INSN_MOVEWIDE_INVERSE
0227 };
0228 
0229 enum aarch64_insn_bitfield_type {
0230     AARCH64_INSN_BITFIELD_MOVE,
0231     AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
0232     AARCH64_INSN_BITFIELD_MOVE_SIGNED
0233 };
0234 
0235 enum aarch64_insn_data1_type {
0236     AARCH64_INSN_DATA1_REVERSE_16,
0237     AARCH64_INSN_DATA1_REVERSE_32,
0238     AARCH64_INSN_DATA1_REVERSE_64,
0239 };
0240 
0241 enum aarch64_insn_data2_type {
0242     AARCH64_INSN_DATA2_UDIV,
0243     AARCH64_INSN_DATA2_SDIV,
0244     AARCH64_INSN_DATA2_LSLV,
0245     AARCH64_INSN_DATA2_LSRV,
0246     AARCH64_INSN_DATA2_ASRV,
0247     AARCH64_INSN_DATA2_RORV,
0248 };
0249 
0250 enum aarch64_insn_data3_type {
0251     AARCH64_INSN_DATA3_MADD,
0252     AARCH64_INSN_DATA3_MSUB,
0253 };
0254 
0255 enum aarch64_insn_logic_type {
0256     AARCH64_INSN_LOGIC_AND,
0257     AARCH64_INSN_LOGIC_BIC,
0258     AARCH64_INSN_LOGIC_ORR,
0259     AARCH64_INSN_LOGIC_ORN,
0260     AARCH64_INSN_LOGIC_EOR,
0261     AARCH64_INSN_LOGIC_EON,
0262     AARCH64_INSN_LOGIC_AND_SETFLAGS,
0263     AARCH64_INSN_LOGIC_BIC_SETFLAGS
0264 };
0265 
0266 enum aarch64_insn_prfm_type {
0267     AARCH64_INSN_PRFM_TYPE_PLD,
0268     AARCH64_INSN_PRFM_TYPE_PLI,
0269     AARCH64_INSN_PRFM_TYPE_PST,
0270 };
0271 
0272 enum aarch64_insn_prfm_target {
0273     AARCH64_INSN_PRFM_TARGET_L1,
0274     AARCH64_INSN_PRFM_TARGET_L2,
0275     AARCH64_INSN_PRFM_TARGET_L3,
0276 };
0277 
0278 enum aarch64_insn_prfm_policy {
0279     AARCH64_INSN_PRFM_POLICY_KEEP,
0280     AARCH64_INSN_PRFM_POLICY_STRM,
0281 };
0282 
0283 enum aarch64_insn_adr_type {
0284     AARCH64_INSN_ADR_TYPE_ADRP,
0285     AARCH64_INSN_ADR_TYPE_ADR,
0286 };
0287 
0288 enum aarch64_insn_mem_atomic_op {
0289     AARCH64_INSN_MEM_ATOMIC_ADD,
0290     AARCH64_INSN_MEM_ATOMIC_CLR,
0291     AARCH64_INSN_MEM_ATOMIC_EOR,
0292     AARCH64_INSN_MEM_ATOMIC_SET,
0293     AARCH64_INSN_MEM_ATOMIC_SWP,
0294 };
0295 
0296 enum aarch64_insn_mem_order_type {
0297     AARCH64_INSN_MEM_ORDER_NONE,
0298     AARCH64_INSN_MEM_ORDER_ACQ,
0299     AARCH64_INSN_MEM_ORDER_REL,
0300     AARCH64_INSN_MEM_ORDER_ACQREL,
0301 };
0302 
0303 enum aarch64_insn_mb_type {
0304     AARCH64_INSN_MB_SY,
0305     AARCH64_INSN_MB_ST,
0306     AARCH64_INSN_MB_LD,
0307     AARCH64_INSN_MB_ISH,
0308     AARCH64_INSN_MB_ISHST,
0309     AARCH64_INSN_MB_ISHLD,
0310     AARCH64_INSN_MB_NSH,
0311     AARCH64_INSN_MB_NSHST,
0312     AARCH64_INSN_MB_NSHLD,
0313     AARCH64_INSN_MB_OSH,
0314     AARCH64_INSN_MB_OSHST,
0315     AARCH64_INSN_MB_OSHLD,
0316 };
0317 
0318 #define __AARCH64_INSN_FUNCS(abbr, mask, val)               \
0319 static __always_inline bool aarch64_insn_is_##abbr(u32 code)        \
0320 {                                   \
0321     BUILD_BUG_ON(~(mask) & (val));                  \
0322     return (code & (mask)) == (val);                \
0323 }                                   \
0324 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)    \
0325 {                                   \
0326     return (val);                           \
0327 }
0328 
0329 __AARCH64_INSN_FUNCS(adr,   0x9F000000, 0x10000000)
0330 __AARCH64_INSN_FUNCS(adrp,  0x9F000000, 0x90000000)
0331 __AARCH64_INSN_FUNCS(prfm,  0x3FC00000, 0x39800000)
0332 __AARCH64_INSN_FUNCS(prfm_lit,  0xFF000000, 0xD8000000)
0333 __AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
0334 __AARCH64_INSN_FUNCS(load_imm,  0x3FC00000, 0x39400000)
0335 __AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
0336 __AARCH64_INSN_FUNCS(load_pre,  0x3FE00C00, 0x38400C00)
0337 __AARCH64_INSN_FUNCS(store_post,    0x3FE00C00, 0x38000400)
0338 __AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
0339 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
0340 __AARCH64_INSN_FUNCS(str_imm,   0x3FC00000, 0x39000000)
0341 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
0342 __AARCH64_INSN_FUNCS(ldclr, 0x3F20FC00, 0x38201000)
0343 __AARCH64_INSN_FUNCS(ldeor, 0x3F20FC00, 0x38202000)
0344 __AARCH64_INSN_FUNCS(ldset, 0x3F20FC00, 0x38203000)
0345 __AARCH64_INSN_FUNCS(swp,   0x3F20FC00, 0x38208000)
0346 __AARCH64_INSN_FUNCS(cas,   0x3FA07C00, 0x08A07C00)
0347 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
0348 __AARCH64_INSN_FUNCS(ldr_imm,   0x3FC00000, 0x39400000)
0349 __AARCH64_INSN_FUNCS(ldr_lit,   0xBF000000, 0x18000000)
0350 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
0351 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
0352 __AARCH64_INSN_FUNCS(load_ex,   0x3F400000, 0x08400000)
0353 __AARCH64_INSN_FUNCS(store_ex,  0x3F400000, 0x08000000)
0354 __AARCH64_INSN_FUNCS(stp,   0x7FC00000, 0x29000000)
0355 __AARCH64_INSN_FUNCS(ldp,   0x7FC00000, 0x29400000)
0356 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
0357 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
0358 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
0359 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
0360 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
0361 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
0362 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
0363 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
0364 __AARCH64_INSN_FUNCS(movn,  0x7F800000, 0x12800000)
0365 __AARCH64_INSN_FUNCS(sbfm,  0x7F800000, 0x13000000)
0366 __AARCH64_INSN_FUNCS(bfm,   0x7F800000, 0x33000000)
0367 __AARCH64_INSN_FUNCS(movz,  0x7F800000, 0x52800000)
0368 __AARCH64_INSN_FUNCS(ubfm,  0x7F800000, 0x53000000)
0369 __AARCH64_INSN_FUNCS(movk,  0x7F800000, 0x72800000)
0370 __AARCH64_INSN_FUNCS(add,   0x7F200000, 0x0B000000)
0371 __AARCH64_INSN_FUNCS(adds,  0x7F200000, 0x2B000000)
0372 __AARCH64_INSN_FUNCS(sub,   0x7F200000, 0x4B000000)
0373 __AARCH64_INSN_FUNCS(subs,  0x7F200000, 0x6B000000)
0374 __AARCH64_INSN_FUNCS(madd,  0x7FE08000, 0x1B000000)
0375 __AARCH64_INSN_FUNCS(msub,  0x7FE08000, 0x1B008000)
0376 __AARCH64_INSN_FUNCS(udiv,  0x7FE0FC00, 0x1AC00800)
0377 __AARCH64_INSN_FUNCS(sdiv,  0x7FE0FC00, 0x1AC00C00)
0378 __AARCH64_INSN_FUNCS(lslv,  0x7FE0FC00, 0x1AC02000)
0379 __AARCH64_INSN_FUNCS(lsrv,  0x7FE0FC00, 0x1AC02400)
0380 __AARCH64_INSN_FUNCS(asrv,  0x7FE0FC00, 0x1AC02800)
0381 __AARCH64_INSN_FUNCS(rorv,  0x7FE0FC00, 0x1AC02C00)
0382 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
0383 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
0384 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
0385 __AARCH64_INSN_FUNCS(and,   0x7F200000, 0x0A000000)
0386 __AARCH64_INSN_FUNCS(bic,   0x7F200000, 0x0A200000)
0387 __AARCH64_INSN_FUNCS(orr,   0x7F200000, 0x2A000000)
0388 __AARCH64_INSN_FUNCS(mov_reg,   0x7FE0FFE0, 0x2A0003E0)
0389 __AARCH64_INSN_FUNCS(orn,   0x7F200000, 0x2A200000)
0390 __AARCH64_INSN_FUNCS(eor,   0x7F200000, 0x4A000000)
0391 __AARCH64_INSN_FUNCS(eon,   0x7F200000, 0x4A200000)
0392 __AARCH64_INSN_FUNCS(ands,  0x7F200000, 0x6A000000)
0393 __AARCH64_INSN_FUNCS(bics,  0x7F200000, 0x6A200000)
0394 __AARCH64_INSN_FUNCS(and_imm,   0x7F800000, 0x12000000)
0395 __AARCH64_INSN_FUNCS(orr_imm,   0x7F800000, 0x32000000)
0396 __AARCH64_INSN_FUNCS(eor_imm,   0x7F800000, 0x52000000)
0397 __AARCH64_INSN_FUNCS(ands_imm,  0x7F800000, 0x72000000)
0398 __AARCH64_INSN_FUNCS(extr,  0x7FA00000, 0x13800000)
0399 __AARCH64_INSN_FUNCS(b,     0xFC000000, 0x14000000)
0400 __AARCH64_INSN_FUNCS(bl,    0xFC000000, 0x94000000)
0401 __AARCH64_INSN_FUNCS(cbz,   0x7F000000, 0x34000000)
0402 __AARCH64_INSN_FUNCS(cbnz,  0x7F000000, 0x35000000)
0403 __AARCH64_INSN_FUNCS(tbz,   0x7F000000, 0x36000000)
0404 __AARCH64_INSN_FUNCS(tbnz,  0x7F000000, 0x37000000)
0405 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
0406 __AARCH64_INSN_FUNCS(svc,   0xFFE0001F, 0xD4000001)
0407 __AARCH64_INSN_FUNCS(hvc,   0xFFE0001F, 0xD4000002)
0408 __AARCH64_INSN_FUNCS(smc,   0xFFE0001F, 0xD4000003)
0409 __AARCH64_INSN_FUNCS(brk,   0xFFE0001F, 0xD4200000)
0410 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
0411 __AARCH64_INSN_FUNCS(hint,  0xFFFFF01F, 0xD503201F)
0412 __AARCH64_INSN_FUNCS(br,    0xFFFFFC1F, 0xD61F0000)
0413 __AARCH64_INSN_FUNCS(br_auth,   0xFEFFF800, 0xD61F0800)
0414 __AARCH64_INSN_FUNCS(blr,   0xFFFFFC1F, 0xD63F0000)
0415 __AARCH64_INSN_FUNCS(blr_auth,  0xFEFFF800, 0xD63F0800)
0416 __AARCH64_INSN_FUNCS(ret,   0xFFFFFC1F, 0xD65F0000)
0417 __AARCH64_INSN_FUNCS(ret_auth,  0xFFFFFBFF, 0xD65F0BFF)
0418 __AARCH64_INSN_FUNCS(eret,  0xFFFFFFFF, 0xD69F03E0)
0419 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
0420 __AARCH64_INSN_FUNCS(mrs,   0xFFF00000, 0xD5300000)
0421 __AARCH64_INSN_FUNCS(msr_imm,   0xFFF8F01F, 0xD500401F)
0422 __AARCH64_INSN_FUNCS(msr_reg,   0xFFF00000, 0xD5100000)
0423 __AARCH64_INSN_FUNCS(dmb,   0xFFFFF0FF, 0xD50330BF)
0424 __AARCH64_INSN_FUNCS(dsb_base,  0xFFFFF0FF, 0xD503309F)
0425 __AARCH64_INSN_FUNCS(dsb_nxs,   0xFFFFF3FF, 0xD503323F)
0426 __AARCH64_INSN_FUNCS(isb,   0xFFFFF0FF, 0xD50330DF)
0427 __AARCH64_INSN_FUNCS(sb,    0xFFFFFFFF, 0xD50330FF)
0428 __AARCH64_INSN_FUNCS(clrex, 0xFFFFF0FF, 0xD503305F)
0429 __AARCH64_INSN_FUNCS(ssbb,  0xFFFFFFFF, 0xD503309F)
0430 __AARCH64_INSN_FUNCS(pssbb, 0xFFFFFFFF, 0xD503349F)
0431 
0432 #undef  __AARCH64_INSN_FUNCS
0433 
0434 bool aarch64_insn_is_steppable_hint(u32 insn);
0435 bool aarch64_insn_is_branch_imm(u32 insn);
0436 
0437 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
0438 {
0439     return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
0440 }
0441 
0442 static inline bool aarch64_insn_is_dsb(u32 insn)
0443 {
0444     return aarch64_insn_is_dsb_base(insn) || aarch64_insn_is_dsb_nxs(insn);
0445 }
0446 
0447 static inline bool aarch64_insn_is_barrier(u32 insn)
0448 {
0449     return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) ||
0450            aarch64_insn_is_isb(insn) || aarch64_insn_is_sb(insn) ||
0451            aarch64_insn_is_clrex(insn) || aarch64_insn_is_ssbb(insn) ||
0452            aarch64_insn_is_pssbb(insn);
0453 }
0454 
0455 static inline bool aarch64_insn_is_store_single(u32 insn)
0456 {
0457     return aarch64_insn_is_store_imm(insn) ||
0458            aarch64_insn_is_store_pre(insn) ||
0459            aarch64_insn_is_store_post(insn);
0460 }
0461 
0462 static inline bool aarch64_insn_is_store_pair(u32 insn)
0463 {
0464     return aarch64_insn_is_stp(insn) ||
0465            aarch64_insn_is_stp_pre(insn) ||
0466            aarch64_insn_is_stp_post(insn);
0467 }
0468 
0469 static inline bool aarch64_insn_is_load_single(u32 insn)
0470 {
0471     return aarch64_insn_is_load_imm(insn) ||
0472            aarch64_insn_is_load_pre(insn) ||
0473            aarch64_insn_is_load_post(insn);
0474 }
0475 
0476 static inline bool aarch64_insn_is_load_pair(u32 insn)
0477 {
0478     return aarch64_insn_is_ldp(insn) ||
0479            aarch64_insn_is_ldp_pre(insn) ||
0480            aarch64_insn_is_ldp_post(insn);
0481 }
0482 
0483 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
0484 bool aarch64_insn_uses_literal(u32 insn);
0485 bool aarch64_insn_is_branch(u32 insn);
0486 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
0487 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
0488                   u32 insn, u64 imm);
0489 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
0490                      u32 insn);
0491 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
0492                 enum aarch64_insn_branch_type type);
0493 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
0494                      enum aarch64_insn_register reg,
0495                      enum aarch64_insn_variant variant,
0496                      enum aarch64_insn_branch_type type);
0497 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
0498                      enum aarch64_insn_condition cond);
0499 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
0500 u32 aarch64_insn_gen_nop(void);
0501 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
0502                 enum aarch64_insn_branch_type type);
0503 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
0504                     enum aarch64_insn_register base,
0505                     enum aarch64_insn_register offset,
0506                     enum aarch64_insn_size_type size,
0507                     enum aarch64_insn_ldst_type type);
0508 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
0509                     enum aarch64_insn_register base,
0510                     unsigned int imm,
0511                     enum aarch64_insn_size_type size,
0512                     enum aarch64_insn_ldst_type type);
0513 u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
0514                   enum aarch64_insn_register reg,
0515                   bool is64bit);
0516 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
0517                      enum aarch64_insn_register reg2,
0518                      enum aarch64_insn_register base,
0519                      int offset,
0520                      enum aarch64_insn_variant variant,
0521                      enum aarch64_insn_ldst_type type);
0522 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
0523                    enum aarch64_insn_register base,
0524                    enum aarch64_insn_register state,
0525                    enum aarch64_insn_size_type size,
0526                    enum aarch64_insn_ldst_type type);
0527 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
0528                  enum aarch64_insn_register src,
0529                  int imm, enum aarch64_insn_variant variant,
0530                  enum aarch64_insn_adsb_type type);
0531 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
0532              enum aarch64_insn_register reg,
0533              enum aarch64_insn_adr_type type);
0534 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
0535                   enum aarch64_insn_register src,
0536                   int immr, int imms,
0537                   enum aarch64_insn_variant variant,
0538                   enum aarch64_insn_bitfield_type type);
0539 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
0540                   int imm, int shift,
0541                   enum aarch64_insn_variant variant,
0542                   enum aarch64_insn_movewide_type type);
0543 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
0544                      enum aarch64_insn_register src,
0545                      enum aarch64_insn_register reg,
0546                      int shift,
0547                      enum aarch64_insn_variant variant,
0548                      enum aarch64_insn_adsb_type type);
0549 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
0550                enum aarch64_insn_register src,
0551                enum aarch64_insn_variant variant,
0552                enum aarch64_insn_data1_type type);
0553 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
0554                enum aarch64_insn_register src,
0555                enum aarch64_insn_register reg,
0556                enum aarch64_insn_variant variant,
0557                enum aarch64_insn_data2_type type);
0558 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
0559                enum aarch64_insn_register src,
0560                enum aarch64_insn_register reg1,
0561                enum aarch64_insn_register reg2,
0562                enum aarch64_insn_variant variant,
0563                enum aarch64_insn_data3_type type);
0564 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
0565                      enum aarch64_insn_register src,
0566                      enum aarch64_insn_register reg,
0567                      int shift,
0568                      enum aarch64_insn_variant variant,
0569                      enum aarch64_insn_logic_type type);
0570 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
0571                   enum aarch64_insn_register src,
0572                   enum aarch64_insn_variant variant);
0573 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
0574                        enum aarch64_insn_variant variant,
0575                        enum aarch64_insn_register Rn,
0576                        enum aarch64_insn_register Rd,
0577                        u64 imm);
0578 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
0579               enum aarch64_insn_register Rm,
0580               enum aarch64_insn_register Rn,
0581               enum aarch64_insn_register Rd,
0582               u8 lsb);
0583 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
0584                   enum aarch64_insn_prfm_type type,
0585                   enum aarch64_insn_prfm_target target,
0586                   enum aarch64_insn_prfm_policy policy);
0587 #ifdef CONFIG_ARM64_LSE_ATOMICS
0588 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
0589                   enum aarch64_insn_register address,
0590                   enum aarch64_insn_register value,
0591                   enum aarch64_insn_size_type size,
0592                   enum aarch64_insn_mem_atomic_op op,
0593                   enum aarch64_insn_mem_order_type order);
0594 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
0595              enum aarch64_insn_register address,
0596              enum aarch64_insn_register value,
0597              enum aarch64_insn_size_type size,
0598              enum aarch64_insn_mem_order_type order);
0599 #else
0600 static inline
0601 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
0602                   enum aarch64_insn_register address,
0603                   enum aarch64_insn_register value,
0604                   enum aarch64_insn_size_type size,
0605                   enum aarch64_insn_mem_atomic_op op,
0606                   enum aarch64_insn_mem_order_type order)
0607 {
0608     return AARCH64_BREAK_FAULT;
0609 }
0610 
0611 static inline
0612 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
0613              enum aarch64_insn_register address,
0614              enum aarch64_insn_register value,
0615              enum aarch64_insn_size_type size,
0616              enum aarch64_insn_mem_order_type order)
0617 {
0618     return AARCH64_BREAK_FAULT;
0619 }
0620 #endif
0621 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
0622 
0623 s32 aarch64_get_branch_offset(u32 insn);
0624 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
0625 
0626 s32 aarch64_insn_adrp_get_offset(u32 insn);
0627 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
0628 
0629 bool aarch32_insn_is_wide(u32 insn);
0630 
0631 #define A32_RN_OFFSET   16
0632 #define A32_RT_OFFSET   12
0633 #define A32_RT2_OFFSET   0
0634 
0635 u32 aarch64_insn_extract_system_reg(u32 insn);
0636 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
0637 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
0638 u32 aarch32_insn_mcr_extract_crm(u32 insn);
0639 
0640 typedef bool (pstate_check_t)(unsigned long);
0641 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
0642 
0643 #endif /* __ASSEMBLY__ */
0644 
0645 #endif  /* __ASM_INSN_H */
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