include/asm/esr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013 - ARM Ltd
0004  * Author: Marc Zyngier <marc.zyngier@arm.com>
0005  */
0006
0007 #ifndef __ASM_ESR_H
0008 #define __ASM_ESR_H
0009
0010 #include <asm/memory.h>
0011 #include <asm/sysreg.h>
0012
0013 #define ESR_ELx_EC_UNKNOWN  (0x00)
0014 #define ESR_ELx_EC_WFx      (0x01)
0015 /* Unallocated EC: 0x02 */
0016 #define ESR_ELx_EC_CP15_32  (0x03)
0017 #define ESR_ELx_EC_CP15_64  (0x04)
0018 #define ESR_ELx_EC_CP14_MR  (0x05)
0019 #define ESR_ELx_EC_CP14_LS  (0x06)
0020 #define ESR_ELx_EC_FP_ASIMD (0x07)
0021 #define ESR_ELx_EC_CP10_ID  (0x08)  /* EL2 only */
0022 #define ESR_ELx_EC_PAC      (0x09)  /* EL2 and above */
0023 /* Unallocated EC: 0x0A - 0x0B */
0024 #define ESR_ELx_EC_CP14_64  (0x0C)
0025 #define ESR_ELx_EC_BTI      (0x0D)
0026 #define ESR_ELx_EC_ILL      (0x0E)
0027 /* Unallocated EC: 0x0F - 0x10 */
0028 #define ESR_ELx_EC_SVC32    (0x11)
0029 #define ESR_ELx_EC_HVC32    (0x12)  /* EL2 only */
0030 #define ESR_ELx_EC_SMC32    (0x13)  /* EL2 and above */
0031 /* Unallocated EC: 0x14 */
0032 #define ESR_ELx_EC_SVC64    (0x15)
0033 #define ESR_ELx_EC_HVC64    (0x16)  /* EL2 and above */
0034 #define ESR_ELx_EC_SMC64    (0x17)  /* EL2 and above */
0035 #define ESR_ELx_EC_SYS64    (0x18)
0036 #define ESR_ELx_EC_SVE      (0x19)
0037 #define ESR_ELx_EC_ERET     (0x1a)  /* EL2 only */
0038 /* Unallocated EC: 0x1B */
0039 #define ESR_ELx_EC_FPAC     (0x1C)  /* EL1 and above */
0040 #define ESR_ELx_EC_SME      (0x1D)
0041 /* Unallocated EC: 0x1E */
0042 #define ESR_ELx_EC_IMP_DEF  (0x1f)  /* EL3 only */
0043 #define ESR_ELx_EC_IABT_LOW (0x20)
0044 #define ESR_ELx_EC_IABT_CUR (0x21)
0045 #define ESR_ELx_EC_PC_ALIGN (0x22)
0046 /* Unallocated EC: 0x23 */
0047 #define ESR_ELx_EC_DABT_LOW (0x24)
0048 #define ESR_ELx_EC_DABT_CUR (0x25)
0049 #define ESR_ELx_EC_SP_ALIGN (0x26)
0050 /* Unallocated EC: 0x27 */
0051 #define ESR_ELx_EC_FP_EXC32 (0x28)
0052 /* Unallocated EC: 0x29 - 0x2B */
0053 #define ESR_ELx_EC_FP_EXC64 (0x2C)
0054 /* Unallocated EC: 0x2D - 0x2E */
0055 #define ESR_ELx_EC_SERROR   (0x2F)
0056 #define ESR_ELx_EC_BREAKPT_LOW  (0x30)
0057 #define ESR_ELx_EC_BREAKPT_CUR  (0x31)
0058 #define ESR_ELx_EC_SOFTSTP_LOW  (0x32)
0059 #define ESR_ELx_EC_SOFTSTP_CUR  (0x33)
0060 #define ESR_ELx_EC_WATCHPT_LOW  (0x34)
0061 #define ESR_ELx_EC_WATCHPT_CUR  (0x35)
0062 /* Unallocated EC: 0x36 - 0x37 */
0063 #define ESR_ELx_EC_BKPT32   (0x38)
0064 /* Unallocated EC: 0x39 */
0065 #define ESR_ELx_EC_VECTOR32 (0x3A)  /* EL2 only */
0066 /* Unallocated EC: 0x3B */
0067 #define ESR_ELx_EC_BRK64    (0x3C)
0068 /* Unallocated EC: 0x3D - 0x3F */
0069 #define ESR_ELx_EC_MAX      (0x3F)
0070
0071 #define ESR_ELx_EC_SHIFT    (26)
0072 #define ESR_ELx_EC_WIDTH    (6)
0073 #define ESR_ELx_EC_MASK     (UL(0x3F) << ESR_ELx_EC_SHIFT)
0074 #define ESR_ELx_EC(esr)     (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
0075
0076 #define ESR_ELx_IL_SHIFT    (25)
0077 #define ESR_ELx_IL      (UL(1) << ESR_ELx_IL_SHIFT)
0078 #define ESR_ELx_ISS_MASK    (ESR_ELx_IL - 1)
0079 #define ESR_ELx_ISS(esr)    ((esr) & ESR_ELx_ISS_MASK)
0080
0081 /* ISS field definitions shared by different classes */
0082 #define ESR_ELx_WNR_SHIFT   (6)
0083 #define ESR_ELx_WNR     (UL(1) << ESR_ELx_WNR_SHIFT)
0084
0085 /* Asynchronous Error Type */
0086 #define ESR_ELx_IDS_SHIFT   (24)
0087 #define ESR_ELx_IDS     (UL(1) << ESR_ELx_IDS_SHIFT)
0088 #define ESR_ELx_AET_SHIFT   (10)
0089 #define ESR_ELx_AET     (UL(0x7) << ESR_ELx_AET_SHIFT)
0090
0091 #define ESR_ELx_AET_UC      (UL(0) << ESR_ELx_AET_SHIFT)
0092 #define ESR_ELx_AET_UEU     (UL(1) << ESR_ELx_AET_SHIFT)
0093 #define ESR_ELx_AET_UEO     (UL(2) << ESR_ELx_AET_SHIFT)
0094 #define ESR_ELx_AET_UER     (UL(3) << ESR_ELx_AET_SHIFT)
0095 #define ESR_ELx_AET_CE      (UL(6) << ESR_ELx_AET_SHIFT)
0096
0097 /* Shared ISS field definitions for Data/Instruction aborts */
0098 #define ESR_ELx_SET_SHIFT   (11)
0099 #define ESR_ELx_SET_MASK    (UL(3) << ESR_ELx_SET_SHIFT)
0100 #define ESR_ELx_FnV_SHIFT   (10)
0101 #define ESR_ELx_FnV     (UL(1) << ESR_ELx_FnV_SHIFT)
0102 #define ESR_ELx_EA_SHIFT    (9)
0103 #define ESR_ELx_EA      (UL(1) << ESR_ELx_EA_SHIFT)
0104 #define ESR_ELx_S1PTW_SHIFT (7)
0105 #define ESR_ELx_S1PTW       (UL(1) << ESR_ELx_S1PTW_SHIFT)
0106
0107 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
0108 #define ESR_ELx_FSC     (0x3F)
0109 #define ESR_ELx_FSC_TYPE    (0x3C)
0110 #define ESR_ELx_FSC_LEVEL   (0x03)
0111 #define ESR_ELx_FSC_EXTABT  (0x10)
0112 #define ESR_ELx_FSC_MTE     (0x11)
0113 #define ESR_ELx_FSC_SERROR  (0x11)
0114 #define ESR_ELx_FSC_ACCESS  (0x08)
0115 #define ESR_ELx_FSC_FAULT   (0x04)
0116 #define ESR_ELx_FSC_PERM    (0x0C)
0117
0118 /* ISS field definitions for Data Aborts */
0119 #define ESR_ELx_ISV_SHIFT   (24)
0120 #define ESR_ELx_ISV     (UL(1) << ESR_ELx_ISV_SHIFT)
0121 #define ESR_ELx_SAS_SHIFT   (22)
0122 #define ESR_ELx_SAS     (UL(3) << ESR_ELx_SAS_SHIFT)
0123 #define ESR_ELx_SSE_SHIFT   (21)
0124 #define ESR_ELx_SSE     (UL(1) << ESR_ELx_SSE_SHIFT)
0125 #define ESR_ELx_SRT_SHIFT   (16)
0126 #define ESR_ELx_SRT_MASK    (UL(0x1F) << ESR_ELx_SRT_SHIFT)
0127 #define ESR_ELx_SF_SHIFT    (15)
0128 #define ESR_ELx_SF      (UL(1) << ESR_ELx_SF_SHIFT)
0129 #define ESR_ELx_AR_SHIFT    (14)
0130 #define ESR_ELx_AR      (UL(1) << ESR_ELx_AR_SHIFT)
0131 #define ESR_ELx_CM_SHIFT    (8)
0132 #define ESR_ELx_CM      (UL(1) << ESR_ELx_CM_SHIFT)
0133
0134 /* ISS field definitions for exceptions taken in to Hyp */
0135 #define ESR_ELx_CV      (UL(1) << 24)
0136 #define ESR_ELx_COND_SHIFT  (20)
0137 #define ESR_ELx_COND_MASK   (UL(0xF) << ESR_ELx_COND_SHIFT)
0138 #define ESR_ELx_WFx_ISS_RN  (UL(0x1F) << 5)
0139 #define ESR_ELx_WFx_ISS_RV  (UL(1) << 2)
0140 #define ESR_ELx_WFx_ISS_TI  (UL(3) << 0)
0141 #define ESR_ELx_WFx_ISS_WFxT    (UL(2) << 0)
0142 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
0143 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
0144 #define ESR_ELx_xVC_IMM_MASK    ((UL(1) << 16) - 1)
0145
0146 #define DISR_EL1_IDS        (UL(1) << 24)
0147 /*
0148  * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
0149  * different things in the future...
0150  */
0151 #define DISR_EL1_ESR_MASK   (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
0152
0153 /* ESR value templates for specific events */
0154 #define ESR_ELx_WFx_MASK    (ESR_ELx_EC_MASK |          \
0155                  (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
0156 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
0157                  ESR_ELx_WFx_ISS_WFI)
0158
0159 /* BRK instruction trap from AArch64 state */
0160 #define ESR_ELx_BRK64_ISS_COMMENT_MASK  0xffff
0161
0162 /* ISS field definitions for System instruction traps */
0163 #define ESR_ELx_SYS64_ISS_RES0_SHIFT    22
0164 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
0165 #define ESR_ELx_SYS64_ISS_DIR_MASK  0x1
0166 #define ESR_ELx_SYS64_ISS_DIR_READ  0x1
0167 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
0168
0169 #define ESR_ELx_SYS64_ISS_RT_SHIFT  5
0170 #define ESR_ELx_SYS64_ISS_RT_MASK   (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
0171 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
0172 #define ESR_ELx_SYS64_ISS_CRM_MASK  (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
0173 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
0174 #define ESR_ELx_SYS64_ISS_CRN_MASK  (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
0175 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
0176 #define ESR_ELx_SYS64_ISS_OP1_MASK  (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
0177 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
0178 #define ESR_ELx_SYS64_ISS_OP2_MASK  (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
0179 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
0180 #define ESR_ELx_SYS64_ISS_OP0_MASK  (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
0181 #define ESR_ELx_SYS64_ISS_SYS_MASK  (ESR_ELx_SYS64_ISS_OP0_MASK | \
0182                      ESR_ELx_SYS64_ISS_OP1_MASK | \
0183                      ESR_ELx_SYS64_ISS_OP2_MASK | \
0184                      ESR_ELx_SYS64_ISS_CRN_MASK | \
0185                      ESR_ELx_SYS64_ISS_CRM_MASK)
0186 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
0187                     (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
0188                      ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
0189                      ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
0190                      ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
0191                      ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
0192
0193 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK   (ESR_ELx_SYS64_ISS_SYS_MASK | \
0194                      ESR_ELx_SYS64_ISS_DIR_MASK)
0195 #define ESR_ELx_SYS64_ISS_RT(esr) \
0196     (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
0197 /*
0198  * User space cache operations have the following sysreg encoding
0199  * in System instructions.
0200  * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
0201  */
0202 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC  14
0203 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP  13
0204 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP   12
0205 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU   11
0206 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC   10
0207 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU   5
0208
0209 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
0210                          ESR_ELx_SYS64_ISS_OP1_MASK | \
0211                          ESR_ELx_SYS64_ISS_OP2_MASK | \
0212                          ESR_ELx_SYS64_ISS_CRN_MASK | \
0213                          ESR_ELx_SYS64_ISS_DIR_MASK)
0214 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
0215                 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
0216                  ESR_ELx_SYS64_ISS_DIR_WRITE)
0217 /*
0218  * User space MRS operations which are supported for emulation
0219  * have the following sysreg encoding in System instructions.
0220  * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
0221  */
0222 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK   (ESR_ELx_SYS64_ISS_OP0_MASK | \
0223                          ESR_ELx_SYS64_ISS_OP1_MASK | \
0224                          ESR_ELx_SYS64_ISS_CRN_MASK | \
0225                          ESR_ELx_SYS64_ISS_DIR_MASK)
0226 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
0227                 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
0228                  ESR_ELx_SYS64_ISS_DIR_READ)
0229
0230 #define ESR_ELx_SYS64_ISS_SYS_CTR   ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
0231 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ  (ESR_ELx_SYS64_ISS_SYS_CTR | \
0232                      ESR_ELx_SYS64_ISS_DIR_READ)
0233
0234 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT    (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
0235                      ESR_ELx_SYS64_ISS_DIR_READ)
0236
0237 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS  (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
0238                      ESR_ELx_SYS64_ISS_DIR_READ)
0239
0240 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ    (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
0241                      ESR_ELx_SYS64_ISS_DIR_READ)
0242
0243 #define esr_sys64_to_sysreg(e)                  \
0244     sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>      \
0245          ESR_ELx_SYS64_ISS_OP0_SHIFT),          \
0246         (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>      \
0247          ESR_ELx_SYS64_ISS_OP1_SHIFT),          \
0248         (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>      \
0249          ESR_ELx_SYS64_ISS_CRN_SHIFT),          \
0250         (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>      \
0251          ESR_ELx_SYS64_ISS_CRM_SHIFT),          \
0252         (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>      \
0253          ESR_ELx_SYS64_ISS_OP2_SHIFT))
0254
0255 #define esr_cp15_to_sysreg(e)                   \
0256     sys_reg(3,                      \
0257         (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>      \
0258          ESR_ELx_SYS64_ISS_OP1_SHIFT),          \
0259         (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>      \
0260          ESR_ELx_SYS64_ISS_CRN_SHIFT),          \
0261         (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>      \
0262          ESR_ELx_SYS64_ISS_CRM_SHIFT),          \
0263         (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>      \
0264          ESR_ELx_SYS64_ISS_OP2_SHIFT))
0265
0266 /*
0267  * ISS field definitions for floating-point exception traps
0268  * (FP_EXC_32/FP_EXC_64).
0269  *
0270  * (The FPEXC_* constants are used instead for common bits.)
0271  */
0272
0273 #define ESR_ELx_FP_EXC_TFV  (UL(1) << 23)
0274
0275 /*
0276  * ISS field definitions for CP15 accesses
0277  */
0278 #define ESR_ELx_CP15_32_ISS_DIR_MASK    0x1
0279 #define ESR_ELx_CP15_32_ISS_DIR_READ    0x1
0280 #define ESR_ELx_CP15_32_ISS_DIR_WRITE   0x0
0281
0282 #define ESR_ELx_CP15_32_ISS_RT_SHIFT    5
0283 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
0284 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT   1
0285 #define ESR_ELx_CP15_32_ISS_CRM_MASK    (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
0286 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT   10
0287 #define ESR_ELx_CP15_32_ISS_CRN_MASK    (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
0288 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT   14
0289 #define ESR_ELx_CP15_32_ISS_OP1_MASK    (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
0290 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT   17
0291 #define ESR_ELx_CP15_32_ISS_OP2_MASK    (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
0292
0293 #define ESR_ELx_CP15_32_ISS_SYS_MASK    (ESR_ELx_CP15_32_ISS_OP1_MASK | \
0294                      ESR_ELx_CP15_32_ISS_OP2_MASK | \
0295                      ESR_ELx_CP15_32_ISS_CRN_MASK | \
0296                      ESR_ELx_CP15_32_ISS_CRM_MASK | \
0297                      ESR_ELx_CP15_32_ISS_DIR_MASK)
0298 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
0299                     (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
0300                      ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
0301                      ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
0302                      ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
0303
0304 #define ESR_ELx_CP15_64_ISS_DIR_MASK    0x1
0305 #define ESR_ELx_CP15_64_ISS_DIR_READ    0x1
0306 #define ESR_ELx_CP15_64_ISS_DIR_WRITE   0x0
0307
0308 #define ESR_ELx_CP15_64_ISS_RT_SHIFT    5
0309 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
0310
0311 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT   10
0312 #define ESR_ELx_CP15_64_ISS_RT2_MASK    (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
0313
0314 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT   16
0315 #define ESR_ELx_CP15_64_ISS_OP1_MASK    (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
0316 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT   1
0317 #define ESR_ELx_CP15_64_ISS_CRM_MASK    (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
0318
0319 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
0320                     (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
0321                      ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
0322
0323 #define ESR_ELx_CP15_64_ISS_SYS_MASK    (ESR_ELx_CP15_64_ISS_OP1_MASK | \
0324                      ESR_ELx_CP15_64_ISS_CRM_MASK | \
0325                      ESR_ELx_CP15_64_ISS_DIR_MASK)
0326
0327 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT  (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
0328                      ESR_ELx_CP15_64_ISS_DIR_READ)
0329
0330 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
0331                      ESR_ELx_CP15_64_ISS_DIR_READ)
0332
0333 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ  (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
0334                      ESR_ELx_CP15_32_ISS_DIR_READ)
0335
0336 /*
0337  * ISS values for SME traps
0338  */
0339
0340 #define ESR_ELx_SME_ISS_SME_DISABLED    0
0341 #define ESR_ELx_SME_ISS_ILL     1
0342 #define ESR_ELx_SME_ISS_SM_DISABLED 2
0343 #define ESR_ELx_SME_ISS_ZA_DISABLED 3
0344
0345 #ifndef __ASSEMBLY__
0346 #include <asm/types.h>
0347
0348 static inline bool esr_is_data_abort(unsigned long esr)
0349 {
0350     const unsigned long ec = ESR_ELx_EC(esr);
0351
0352     return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
0353 }
0354
0355 const char *esr_get_class_string(unsigned long esr);
0356 #endif /* __ASSEMBLY */
0357
0358 #endif /* __ASM_ESR_H */