include/asm/arm_dsu_pmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ARM DynamIQ Shared Unit (DSU) PMU Low level register access routines.
0004  *
0005  * Copyright (C) ARM Limited, 2017.
0006  *
0007  * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
0008  */
0009
0010 #include <linux/bitops.h>
0011 #include <linux/build_bug.h>
0012 #include <linux/compiler.h>
0013 #include <linux/types.h>
0014 #include <asm/barrier.h>
0015 #include <asm/sysreg.h>
0016
0017
0018 #define CLUSTERPMCR_EL1         sys_reg(3, 0, 15, 5, 0)
0019 #define CLUSTERPMCNTENSET_EL1       sys_reg(3, 0, 15, 5, 1)
0020 #define CLUSTERPMCNTENCLR_EL1       sys_reg(3, 0, 15, 5, 2)
0021 #define CLUSTERPMOVSSET_EL1     sys_reg(3, 0, 15, 5, 3)
0022 #define CLUSTERPMOVSCLR_EL1     sys_reg(3, 0, 15, 5, 4)
0023 #define CLUSTERPMSELR_EL1       sys_reg(3, 0, 15, 5, 5)
0024 #define CLUSTERPMINTENSET_EL1       sys_reg(3, 0, 15, 5, 6)
0025 #define CLUSTERPMINTENCLR_EL1       sys_reg(3, 0, 15, 5, 7)
0026 #define CLUSTERPMCCNTR_EL1      sys_reg(3, 0, 15, 6, 0)
0027 #define CLUSTERPMXEVTYPER_EL1       sys_reg(3, 0, 15, 6, 1)
0028 #define CLUSTERPMXEVCNTR_EL1        sys_reg(3, 0, 15, 6, 2)
0029 #define CLUSTERPMMDCR_EL1       sys_reg(3, 0, 15, 6, 3)
0030 #define CLUSTERPMCEID0_EL1      sys_reg(3, 0, 15, 6, 4)
0031 #define CLUSTERPMCEID1_EL1      sys_reg(3, 0, 15, 6, 5)
0032
0033 static inline u32 __dsu_pmu_read_pmcr(void)
0034 {
0035     return read_sysreg_s(CLUSTERPMCR_EL1);
0036 }
0037
0038 static inline void __dsu_pmu_write_pmcr(u32 val)
0039 {
0040     write_sysreg_s(val, CLUSTERPMCR_EL1);
0041     isb();
0042 }
0043
0044 static inline u32 __dsu_pmu_get_reset_overflow(void)
0045 {
0046     u32 val = read_sysreg_s(CLUSTERPMOVSCLR_EL1);
0047     /* Clear the bit */
0048     write_sysreg_s(val, CLUSTERPMOVSCLR_EL1);
0049     isb();
0050     return val;
0051 }
0052
0053 static inline void __dsu_pmu_select_counter(int counter)
0054 {
0055     write_sysreg_s(counter, CLUSTERPMSELR_EL1);
0056     isb();
0057 }
0058
0059 static inline u64 __dsu_pmu_read_counter(int counter)
0060 {
0061     __dsu_pmu_select_counter(counter);
0062     return read_sysreg_s(CLUSTERPMXEVCNTR_EL1);
0063 }
0064
0065 static inline void __dsu_pmu_write_counter(int counter, u64 val)
0066 {
0067     __dsu_pmu_select_counter(counter);
0068     write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1);
0069     isb();
0070 }
0071
0072 static inline void __dsu_pmu_set_event(int counter, u32 event)
0073 {
0074     __dsu_pmu_select_counter(counter);
0075     write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1);
0076     isb();
0077 }
0078
0079 static inline u64 __dsu_pmu_read_pmccntr(void)
0080 {
0081     return read_sysreg_s(CLUSTERPMCCNTR_EL1);
0082 }
0083
0084 static inline void __dsu_pmu_write_pmccntr(u64 val)
0085 {
0086     write_sysreg_s(val, CLUSTERPMCCNTR_EL1);
0087     isb();
0088 }
0089
0090 static inline void __dsu_pmu_disable_counter(int counter)
0091 {
0092     write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1);
0093     isb();
0094 }
0095
0096 static inline void __dsu_pmu_enable_counter(int counter)
0097 {
0098     write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1);
0099     isb();
0100 }
0101
0102 static inline void __dsu_pmu_counter_interrupt_enable(int counter)
0103 {
0104     write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1);
0105     isb();
0106 }
0107
0108 static inline void __dsu_pmu_counter_interrupt_disable(int counter)
0109 {
0110     write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1);
0111     isb();
0112 }
0113
0114
0115 static inline u32 __dsu_pmu_read_pmceid(int n)
0116 {
0117     switch (n) {
0118     case 0:
0119         return read_sysreg_s(CLUSTERPMCEID0_EL1);
0120     case 1:
0121         return read_sysreg_s(CLUSTERPMCEID1_EL1);
0122     default:
0123         BUILD_BUG();
0124         return 0;
0125     }
0126 }