0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
0004 *
0005 * (C) Copyright 2015 - 2021, Xilinx, Inc.
0006 *
0007 * Michal Simek <michal.simek@xilinx.com>
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "zynqmp.dtsi"
0013 #include "zynqmp-clk-ccf.dtsi"
0014 #include <dt-bindings/gpio/gpio.h>
0015 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0016
0017 / {
0018 model = "ZynqMP zc1751-xm016-dc2 RevA";
0019 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
0020
0021 aliases {
0022 ethernet0 = &gem2;
0023 i2c0 = &i2c0;
0024 rtc0 = &rtc;
0025 serial0 = &uart0;
0026 serial1 = &uart1;
0027 spi0 = &spi0;
0028 spi1 = &spi1;
0029 usb0 = &usb1;
0030 };
0031
0032 chosen {
0033 bootargs = "earlycon";
0034 stdout-path = "serial0:115200n8";
0035 };
0036
0037 memory@0 {
0038 device_type = "memory";
0039 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
0040 };
0041 };
0042
0043 &can0 {
0044 status = "okay";
0045 pinctrl-names = "default";
0046 pinctrl-0 = <&pinctrl_can0_default>;
0047 };
0048
0049 &can1 {
0050 status = "okay";
0051 pinctrl-names = "default";
0052 pinctrl-0 = <&pinctrl_can1_default>;
0053 };
0054
0055 &fpd_dma_chan1 {
0056 status = "okay";
0057 };
0058
0059 &fpd_dma_chan2 {
0060 status = "okay";
0061 };
0062
0063 &fpd_dma_chan3 {
0064 status = "okay";
0065 };
0066
0067 &fpd_dma_chan4 {
0068 status = "okay";
0069 };
0070
0071 &fpd_dma_chan5 {
0072 status = "okay";
0073 };
0074
0075 &fpd_dma_chan6 {
0076 status = "okay";
0077 };
0078
0079 &fpd_dma_chan7 {
0080 status = "okay";
0081 };
0082
0083 &fpd_dma_chan8 {
0084 status = "okay";
0085 };
0086
0087 &gem2 {
0088 status = "okay";
0089 phy-handle = <&phy0>;
0090 phy-mode = "rgmii-id";
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&pinctrl_gem2_default>;
0093 phy0: ethernet-phy@5 {
0094 reg = <5>;
0095 ti,rx-internal-delay = <0x8>;
0096 ti,tx-internal-delay = <0xa>;
0097 ti,fifo-depth = <0x1>;
0098 ti,dp83867-rxctrl-strap-quirk;
0099 };
0100 };
0101
0102 &gpio {
0103 status = "okay";
0104 };
0105
0106 &i2c0 {
0107 status = "okay";
0108 clock-frequency = <400000>;
0109 pinctrl-names = "default", "gpio";
0110 pinctrl-0 = <&pinctrl_i2c0_default>;
0111 pinctrl-1 = <&pinctrl_i2c0_gpio>;
0112 scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
0113 sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
0114
0115 tca6416_u26: gpio@20 {
0116 compatible = "ti,tca6416";
0117 reg = <0x20>;
0118 gpio-controller;
0119 #gpio-cells = <2>;
0120 /* IRQ not connected */
0121 };
0122
0123 rtc@68 {
0124 compatible = "dallas,ds1339";
0125 reg = <0x68>;
0126 };
0127 };
0128
0129 &nand0 {
0130 status = "okay";
0131 pinctrl-names = "default";
0132 pinctrl-0 = <&pinctrl_nand0_default>;
0133 arasan,has-mdma;
0134
0135 nand@0 {
0136 reg = <0x0>;
0137 #address-cells = <0x2>;
0138 #size-cells = <0x1>;
0139 nand-ecc-mode = "soft";
0140 nand-ecc-algo = "bch";
0141 nand-rb = <0>;
0142 label = "main-storage-0";
0143 };
0144 nand@1 {
0145 reg = <0x1>;
0146 #address-cells = <0x2>;
0147 #size-cells = <0x1>;
0148 nand-ecc-mode = "soft";
0149 nand-ecc-algo = "bch";
0150 nand-rb = <0>;
0151 label = "main-storage-1";
0152 };
0153 };
0154
0155 &pinctrl0 {
0156 status = "okay";
0157 pinctrl_can0_default: can0-default {
0158 mux {
0159 function = "can0";
0160 groups = "can0_9_grp";
0161 };
0162
0163 conf {
0164 groups = "can0_9_grp";
0165 slew-rate = <SLEW_RATE_SLOW>;
0166 power-source = <IO_STANDARD_LVCMOS18>;
0167 };
0168
0169 conf-rx {
0170 pins = "MIO38";
0171 bias-high-impedance;
0172 };
0173
0174 conf-tx {
0175 pins = "MIO39";
0176 bias-disable;
0177 };
0178 };
0179
0180 pinctrl_can1_default: can1-default {
0181 mux {
0182 function = "can1";
0183 groups = "can1_8_grp";
0184 };
0185
0186 conf {
0187 groups = "can1_8_grp";
0188 slew-rate = <SLEW_RATE_SLOW>;
0189 power-source = <IO_STANDARD_LVCMOS18>;
0190 };
0191
0192 conf-rx {
0193 pins = "MIO33";
0194 bias-high-impedance;
0195 };
0196
0197 conf-tx {
0198 pins = "MIO32";
0199 bias-disable;
0200 };
0201 };
0202
0203 pinctrl_i2c0_default: i2c0-default {
0204 mux {
0205 groups = "i2c0_1_grp";
0206 function = "i2c0";
0207 };
0208
0209 conf {
0210 groups = "i2c0_1_grp";
0211 bias-pull-up;
0212 slew-rate = <SLEW_RATE_SLOW>;
0213 power-source = <IO_STANDARD_LVCMOS18>;
0214 };
0215 };
0216
0217 pinctrl_i2c0_gpio: i2c0-gpio {
0218 mux {
0219 groups = "gpio0_6_grp", "gpio0_7_grp";
0220 function = "gpio0";
0221 };
0222
0223 conf {
0224 groups = "gpio0_6_grp", "gpio0_7_grp";
0225 slew-rate = <SLEW_RATE_SLOW>;
0226 power-source = <IO_STANDARD_LVCMOS18>;
0227 };
0228 };
0229
0230 pinctrl_uart0_default: uart0-default {
0231 mux {
0232 groups = "uart0_10_grp";
0233 function = "uart0";
0234 };
0235
0236 conf {
0237 groups = "uart0_10_grp";
0238 slew-rate = <SLEW_RATE_SLOW>;
0239 power-source = <IO_STANDARD_LVCMOS18>;
0240 };
0241
0242 conf-rx {
0243 pins = "MIO42";
0244 bias-high-impedance;
0245 };
0246
0247 conf-tx {
0248 pins = "MIO43";
0249 bias-disable;
0250 };
0251 };
0252
0253 pinctrl_uart1_default: uart1-default {
0254 mux {
0255 groups = "uart1_10_grp";
0256 function = "uart1";
0257 };
0258
0259 conf {
0260 groups = "uart1_10_grp";
0261 slew-rate = <SLEW_RATE_SLOW>;
0262 power-source = <IO_STANDARD_LVCMOS18>;
0263 };
0264
0265 conf-rx {
0266 pins = "MIO41";
0267 bias-high-impedance;
0268 };
0269
0270 conf-tx {
0271 pins = "MIO40";
0272 bias-disable;
0273 };
0274 };
0275
0276 pinctrl_usb1_default: usb1-default {
0277 mux {
0278 groups = "usb1_0_grp";
0279 function = "usb1";
0280 };
0281
0282 conf {
0283 groups = "usb1_0_grp";
0284 slew-rate = <SLEW_RATE_SLOW>;
0285 power-source = <IO_STANDARD_LVCMOS18>;
0286 };
0287
0288 conf-rx {
0289 pins = "MIO64", "MIO65", "MIO67";
0290 bias-high-impedance;
0291 };
0292
0293 conf-tx {
0294 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
0295 "MIO72", "MIO73", "MIO74", "MIO75";
0296 bias-disable;
0297 };
0298 };
0299
0300 pinctrl_gem2_default: gem2-default {
0301 mux {
0302 function = "ethernet2";
0303 groups = "ethernet2_0_grp";
0304 };
0305
0306 conf {
0307 groups = "ethernet2_0_grp";
0308 slew-rate = <SLEW_RATE_SLOW>;
0309 power-source = <IO_STANDARD_LVCMOS18>;
0310 };
0311
0312 conf-rx {
0313 pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
0314 "MIO63";
0315 bias-high-impedance;
0316 low-power-disable;
0317 };
0318
0319 conf-tx {
0320 pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
0321 "MIO57";
0322 bias-disable;
0323 low-power-enable;
0324 };
0325
0326 mux-mdio {
0327 function = "mdio2";
0328 groups = "mdio2_0_grp";
0329 };
0330
0331 conf-mdio {
0332 groups = "mdio2_0_grp";
0333 slew-rate = <SLEW_RATE_SLOW>;
0334 power-source = <IO_STANDARD_LVCMOS18>;
0335 bias-disable;
0336 };
0337 };
0338
0339 pinctrl_nand0_default: nand0-default {
0340 mux {
0341 groups = "nand0_0_grp";
0342 function = "nand0";
0343 };
0344
0345 conf {
0346 groups = "nand0_0_grp";
0347 bias-pull-up;
0348 };
0349
0350 mux-ce {
0351 groups = "nand0_ce_0_grp";
0352 function = "nand0_ce";
0353 };
0354
0355 conf-ce {
0356 groups = "nand0_ce_0_grp";
0357 bias-pull-up;
0358 };
0359
0360 mux-rb {
0361 groups = "nand0_rb_0_grp";
0362 function = "nand0_rb";
0363 };
0364
0365 conf-rb {
0366 groups = "nand0_rb_0_grp";
0367 bias-pull-up;
0368 };
0369
0370 mux-dqs {
0371 groups = "nand0_dqs_0_grp";
0372 function = "nand0_dqs";
0373 };
0374
0375 conf-dqs {
0376 groups = "nand0_dqs_0_grp";
0377 bias-pull-up;
0378 };
0379 };
0380
0381 pinctrl_spi0_default: spi0-default {
0382 mux {
0383 groups = "spi0_0_grp";
0384 function = "spi0";
0385 };
0386
0387 conf {
0388 groups = "spi0_0_grp";
0389 bias-disable;
0390 slew-rate = <SLEW_RATE_SLOW>;
0391 power-source = <IO_STANDARD_LVCMOS18>;
0392 };
0393
0394 mux-cs {
0395 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
0396 "spi0_ss_2_grp";
0397 function = "spi0_ss";
0398 };
0399
0400 conf-cs {
0401 groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
0402 "spi0_ss_2_grp";
0403 bias-disable;
0404 };
0405 };
0406
0407 pinctrl_spi1_default: spi1-default {
0408 mux {
0409 groups = "spi1_3_grp";
0410 function = "spi1";
0411 };
0412
0413 conf {
0414 groups = "spi1_3_grp";
0415 bias-disable;
0416 slew-rate = <SLEW_RATE_SLOW>;
0417 power-source = <IO_STANDARD_LVCMOS18>;
0418 };
0419
0420 mux-cs {
0421 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
0422 "spi1_ss_11_grp";
0423 function = "spi1_ss";
0424 };
0425
0426 conf-cs {
0427 groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
0428 "spi1_ss_11_grp";
0429 bias-disable;
0430 };
0431 };
0432 };
0433
0434 &rtc {
0435 status = "okay";
0436 };
0437
0438 &spi0 {
0439 status = "okay";
0440 num-cs = <1>;
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&pinctrl_spi0_default>;
0443
0444 spi0_flash0: flash@0 {
0445 #address-cells = <1>;
0446 #size-cells = <1>;
0447 compatible = "sst,sst25wf080", "jedec,spi-nor";
0448 spi-max-frequency = <50000000>;
0449 reg = <0>;
0450
0451 partition@0 {
0452 label = "spi0-data";
0453 reg = <0x0 0x100000>;
0454 };
0455 };
0456 };
0457
0458 &spi1 {
0459 status = "okay";
0460 num-cs = <1>;
0461 pinctrl-names = "default";
0462 pinctrl-0 = <&pinctrl_spi1_default>;
0463
0464 spi1_flash0: flash@0 {
0465 #address-cells = <1>;
0466 #size-cells = <1>;
0467 compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
0468 spi-max-frequency = <20000000>;
0469 reg = <0>;
0470
0471 partition@0 {
0472 label = "spi1-data";
0473 reg = <0x0 0x84000>;
0474 };
0475 };
0476 };
0477
0478 /* ULPI SMSC USB3320 */
0479 &usb1 {
0480 status = "okay";
0481 pinctrl-names = "default";
0482 pinctrl-0 = <&pinctrl_usb1_default>;
0483 };
0484
0485 &dwc3_1 {
0486 status = "okay";
0487 dr_mode = "host";
0488 snps,usb3_lpm_capable;
0489 maximum-speed = "super-speed";
0490 };
0491
0492 &uart0 {
0493 status = "okay";
0494 pinctrl-names = "default";
0495 pinctrl-0 = <&pinctrl_uart0_default>;
0496 };
0497
0498 &uart1 {
0499 status = "okay";
0500 pinctrl-names = "default";
0501 pinctrl-0 = <&pinctrl_uart1_default>;
0502 };
