0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * dts file for KV260 revA Carrier Card
0004 *
0005 * (C) Copyright 2020 - 2021, Xilinx, Inc.
0006 *
0007 * SD level shifter:
0008 * "A" – A01 board un-modified (NXP)
0009 * "Y" – A01 board modified with legacy interposer (Nexperia)
0010 * "Z" – A01 board modified with Diode interposer
0011 *
0012 * Michal Simek <michal.simek@xilinx.com>
0013 */
0014
0015 #include <dt-bindings/gpio/gpio.h>
0016 #include <dt-bindings/net/ti-dp83867.h>
0017 #include <dt-bindings/phy/phy.h>
0018 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
0019
0020 /dts-v1/;
0021 /plugin/;
0022
0023 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026 pinctrl-names = "default", "gpio";
0027 pinctrl-0 = <&pinctrl_i2c1_default>;
0028 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0029 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
0030 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
0031
0032 /* u14 - 0x40 - ina260 */
0033 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
0034 };
0035
0036 &amba {
0037 si5332_0: si5332_0 { /* u17 */
0038 compatible = "fixed-clock";
0039 #clock-cells = <0>;
0040 clock-frequency = <125000000>;
0041 };
0042
0043 si5332_1: si5332_1 { /* u17 */
0044 compatible = "fixed-clock";
0045 #clock-cells = <0>;
0046 clock-frequency = <25000000>;
0047 };
0048
0049 si5332_2: si5332_2 { /* u17 */
0050 compatible = "fixed-clock";
0051 #clock-cells = <0>;
0052 clock-frequency = <48000000>;
0053 };
0054
0055 si5332_3: si5332_3 { /* u17 */
0056 compatible = "fixed-clock";
0057 #clock-cells = <0>;
0058 clock-frequency = <24000000>;
0059 };
0060
0061 si5332_4: si5332_4 { /* u17 */
0062 compatible = "fixed-clock";
0063 #clock-cells = <0>;
0064 clock-frequency = <26000000>;
0065 };
0066
0067 si5332_5: si5332_5 { /* u17 */
0068 compatible = "fixed-clock";
0069 #clock-cells = <0>;
0070 clock-frequency = <27000000>;
0071 };
0072 };
0073
0074 /* DP/USB 3.0 and SATA */
0075 &psgtr {
0076 status = "okay";
0077 /* pcie, usb3, sata */
0078 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
0079 clock-names = "ref0", "ref1", "ref2";
0080 };
0081
0082 &sata {
0083 status = "okay";
0084 /* SATA OOB timing settings */
0085 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0086 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0087 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0088 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0089 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
0090 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
0091 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
0092 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
0093 phy-names = "sata-phy";
0094 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
0095 };
0096
0097 &zynqmp_dpsub {
0098 status = "disabled";
0099 phy-names = "dp-phy0", "dp-phy1";
0100 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
0101 };
0102
0103 &zynqmp_dpdma {
0104 status = "okay";
0105 };
0106
0107 &usb0 {
0108 status = "okay";
0109 pinctrl-names = "default";
0110 pinctrl-0 = <&pinctrl_usb0_default>;
0111 phy-names = "usb3-phy";
0112 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
0113 /* missing usb5744 - u43 */
0114 };
0115
0116 &dwc3_0 {
0117 status = "okay";
0118 dr_mode = "host";
0119 snps,usb3_lpm_capable;
0120 maximum-speed = "super-speed";
0121 };
0122
0123 &sdhci1 { /* on CC with tuned parameters */
0124 status = "okay";
0125 pinctrl-names = "default";
0126 pinctrl-0 = <&pinctrl_sdhci1_default>;
0127 /*
0128 * SD 3.0 requires level shifter and this property
0129 * should be removed if the board has level shifter and
0130 * need to work in UHS mode
0131 */
0132 no-1-8-v;
0133 disable-wp;
0134 xlnx,mio-bank = <1>;
0135 };
0136
0137 &gem3 { /* required by spec */
0138 status = "okay";
0139 pinctrl-names = "default";
0140 pinctrl-0 = <&pinctrl_gem3_default>;
0141 phy-handle = <&phy0>;
0142 phy-mode = "rgmii-id";
0143
0144 mdio: mdio {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
0148 reset-delay-us = <2>;
0149
0150 phy0: ethernet-phy@1 {
0151 #phy-cells = <1>;
0152 reg = <1>;
0153 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0154 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
0155 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0156 ti,dp83867-rxctrl-strap-quirk;
0157 };
0158 };
0159 };
0160
0161 &pinctrl0 { /* required by spec */
0162 status = "okay";
0163
0164 pinctrl_uart1_default: uart1-default {
0165 conf {
0166 groups = "uart1_9_grp";
0167 slew-rate = <SLEW_RATE_SLOW>;
0168 power-source = <IO_STANDARD_LVCMOS18>;
0169 drive-strength = <12>;
0170 };
0171
0172 conf-rx {
0173 pins = "MIO37";
0174 bias-high-impedance;
0175 };
0176
0177 conf-tx {
0178 pins = "MIO36";
0179 bias-disable;
0180 };
0181
0182 mux {
0183 groups = "uart1_9_grp";
0184 function = "uart1";
0185 };
0186 };
0187
0188 pinctrl_i2c1_default: i2c1-default {
0189 conf {
0190 groups = "i2c1_6_grp";
0191 bias-pull-up;
0192 slew-rate = <SLEW_RATE_SLOW>;
0193 power-source = <IO_STANDARD_LVCMOS18>;
0194 };
0195
0196 mux {
0197 groups = "i2c1_6_grp";
0198 function = "i2c1";
0199 };
0200 };
0201
0202 pinctrl_i2c1_gpio: i2c1-gpio {
0203 conf {
0204 groups = "gpio0_24_grp", "gpio0_25_grp";
0205 slew-rate = <SLEW_RATE_SLOW>;
0206 power-source = <IO_STANDARD_LVCMOS18>;
0207 };
0208
0209 mux {
0210 groups = "gpio0_24_grp", "gpio0_25_grp";
0211 function = "gpio0";
0212 };
0213 };
0214
0215 pinctrl_gem3_default: gem3-default {
0216 conf {
0217 groups = "ethernet3_0_grp";
0218 slew-rate = <SLEW_RATE_SLOW>;
0219 power-source = <IO_STANDARD_LVCMOS18>;
0220 };
0221
0222 conf-rx {
0223 pins = "MIO70", "MIO72", "MIO74";
0224 bias-high-impedance;
0225 low-power-disable;
0226 };
0227
0228 conf-bootstrap {
0229 pins = "MIO71", "MIO73", "MIO75";
0230 bias-disable;
0231 low-power-disable;
0232 };
0233
0234 conf-tx {
0235 pins = "MIO64", "MIO65", "MIO66",
0236 "MIO67", "MIO68", "MIO69";
0237 bias-disable;
0238 low-power-enable;
0239 };
0240
0241 conf-mdio {
0242 groups = "mdio3_0_grp";
0243 slew-rate = <SLEW_RATE_SLOW>;
0244 power-source = <IO_STANDARD_LVCMOS18>;
0245 bias-disable;
0246 };
0247
0248 mux-mdio {
0249 function = "mdio3";
0250 groups = "mdio3_0_grp";
0251 };
0252
0253 mux {
0254 function = "ethernet3";
0255 groups = "ethernet3_0_grp";
0256 };
0257 };
0258
0259 pinctrl_usb0_default: usb0-default {
0260 conf {
0261 groups = "usb0_0_grp";
0262 slew-rate = <SLEW_RATE_SLOW>;
0263 power-source = <IO_STANDARD_LVCMOS18>;
0264 };
0265
0266 conf-rx {
0267 pins = "MIO52", "MIO53", "MIO55";
0268 bias-high-impedance;
0269 };
0270
0271 conf-tx {
0272 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
0273 "MIO60", "MIO61", "MIO62", "MIO63";
0274 bias-disable;
0275 };
0276
0277 mux {
0278 groups = "usb0_0_grp";
0279 function = "usb0";
0280 };
0281 };
0282
0283 pinctrl_sdhci1_default: sdhci1-default {
0284 conf {
0285 groups = "sdio1_0_grp";
0286 slew-rate = <SLEW_RATE_SLOW>;
0287 power-source = <IO_STANDARD_LVCMOS18>;
0288 bias-disable;
0289 };
0290
0291 conf-cd {
0292 groups = "sdio1_cd_0_grp";
0293 bias-high-impedance;
0294 bias-pull-up;
0295 slew-rate = <SLEW_RATE_SLOW>;
0296 power-source = <IO_STANDARD_LVCMOS18>;
0297 };
0298
0299 mux-cd {
0300 groups = "sdio1_cd_0_grp";
0301 function = "sdio1_cd";
0302 };
0303
0304 mux {
0305 groups = "sdio1_0_grp";
0306 function = "sdio1";
0307 };
0308 };
0309 };
0310
0311 &uart1 {
0312 status = "okay";
0313 pinctrl-names = "default";
0314 pinctrl-0 = <&pinctrl_uart1_default>;
0315 };
