0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721S2 SoC Family
0004 *
0005 * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
0006 *
0007 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
0008 *
0009 */
0010
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/pinctrl/k3.h>
0014 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0015
0016 / {
0017
0018 model = "Texas Instruments K3 J721S2 SoC";
0019 compatible = "ti,j721s2";
0020 interrupt-parent = <&gic500>;
0021 #address-cells = <2>;
0022 #size-cells = <2>;
0023
0024 chosen { };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029 cpu-map {
0030 cluster0: cluster0 {
0031 core0 {
0032 cpu = <&cpu0>;
0033 };
0034
0035 core1 {
0036 cpu = <&cpu1>;
0037 };
0038 };
0039 };
0040
0041 cpu0: cpu@0 {
0042 compatible = "arm,cortex-a72";
0043 reg = <0x000>;
0044 device_type = "cpu";
0045 enable-method = "psci";
0046 i-cache-size = <0xc000>;
0047 i-cache-line-size = <64>;
0048 i-cache-sets = <256>;
0049 d-cache-size = <0x8000>;
0050 d-cache-line-size = <64>;
0051 d-cache-sets = <256>;
0052 next-level-cache = <&L2_0>;
0053 };
0054
0055 cpu1: cpu@1 {
0056 compatible = "arm,cortex-a72";
0057 reg = <0x001>;
0058 device_type = "cpu";
0059 enable-method = "psci";
0060 i-cache-size = <0xc000>;
0061 i-cache-line-size = <64>;
0062 i-cache-sets = <256>;
0063 d-cache-size = <0x8000>;
0064 d-cache-line-size = <64>;
0065 d-cache-sets = <256>;
0066 next-level-cache = <&L2_0>;
0067 };
0068 };
0069
0070 L2_0: l2-cache0 {
0071 compatible = "cache";
0072 cache-level = <2>;
0073 cache-size = <0x100000>;
0074 cache-line-size = <64>;
0075 cache-sets = <1024>;
0076 next-level-cache = <&msmc_l3>;
0077 };
0078
0079 msmc_l3: l3-cache0 {
0080 compatible = "cache";
0081 cache-level = <3>;
0082 };
0083
0084 firmware {
0085 optee {
0086 compatible = "linaro,optee-tz";
0087 method = "smc";
0088 };
0089
0090 psci: psci {
0091 compatible = "arm,psci-1.0";
0092 method = "smc";
0093 };
0094 };
0095
0096 a72_timer0: timer-cl0-cpu0 {
0097 compatible = "arm,armv8-timer";
0098 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
0099 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
0100 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
0101 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
0102
0103 };
0104
0105 pmu: pmu {
0106 compatible = "arm,cortex-a72-pmu";
0107 /* Recommendation from GIC500 TRM Table A.3 */
0108 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0109 };
0110
0111 cbass_main: bus@100000 {
0112 compatible = "simple-bus";
0113 #address-cells = <2>;
0114 #size-cells = <2>;
0115 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
0116 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
0117 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
0118 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
0119 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
0120 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
0121 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
0122 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
0123 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
0124 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
0125 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
0126 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
0127
0128 /* MCUSS_WKUP Range */
0129 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
0130 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
0131 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
0132 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
0133 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
0134 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
0135 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
0136 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
0137 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
0138 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
0139 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
0140 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
0141 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
0142
0143 cbass_mcu_wakeup: bus@28380000 {
0144 compatible = "simple-bus";
0145 #address-cells = <2>;
0146 #size-cells = <2>;
0147 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
0148 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
0149 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
0150 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
0151 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
0152 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
0153 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
0154 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
0155 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
0156 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
0157 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
0158 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
0159 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
0160
0161 };
0162
0163 };
0164 };
0165
0166 /* Now include peripherals from each bus segment */
0167 #include "k3-j721s2-main.dtsi"
0168 #include "k3-j721s2-mcu-wakeup.dtsi"
