0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 &cbass_main {
0009 msmc_ram: sram@70000000 {
0010 compatible = "mmio-sram";
0011 reg = <0x0 0x70000000 0x0 0x400000>;
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 ranges = <0x0 0x0 0x70000000 0x400000>;
0015
0016 atf-sram@0 {
0017 reg = <0x0 0x20000>;
0018 };
0019
0020 tifs-sram@1f0000 {
0021 reg = <0x1f0000 0x10000>;
0022 };
0023
0024 l3cache-sram@200000 {
0025 reg = <0x200000 0x200000>;
0026 };
0027 };
0028
0029 gic500: interrupt-controller@1800000 {
0030 compatible = "arm,gic-v3";
0031 #address-cells = <2>;
0032 #size-cells = <2>;
0033 ranges;
0034 #interrupt-cells = <3>;
0035 interrupt-controller;
0036 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
0037 <0x00 0x01900000 0x00 0x100000>, /* GICR */
0038 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
0039 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
0040 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
0041
0042 /* vcpumntirq: virtual CPU interface maintenance interrupt */
0043 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0044
0045 gic_its: msi-controller@1820000 {
0046 compatible = "arm,gic-v3-its";
0047 reg = <0x00 0x01820000 0x00 0x10000>;
0048 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0049 msi-controller;
0050 #msi-cells = <1>;
0051 };
0052 };
0053
0054 main_gpio_intr: interrupt-controller@a00000 {
0055 compatible = "ti,sci-intr";
0056 reg = <0x00 0x00a00000 0x00 0x800>;
0057 ti,intr-trigger-type = <1>;
0058 interrupt-controller;
0059 interrupt-parent = <&gic500>;
0060 #interrupt-cells = <1>;
0061 ti,sci = <&sms>;
0062 ti,sci-dev-id = <148>;
0063 ti,interrupt-ranges = <8 360 56>;
0064 };
0065
0066 main_pmx0: pinctrl@11c000 {
0067 compatible = "pinctrl-single";
0068 /* Proxy 0 addressing */
0069 reg = <0x0 0x11c000 0x0 0x120>;
0070 #pinctrl-cells = <1>;
0071 pinctrl-single,register-width = <32>;
0072 pinctrl-single,function-mask = <0xffffffff>;
0073 };
0074
0075 main_uart0: serial@2800000 {
0076 compatible = "ti,j721e-uart", "ti,am654-uart";
0077 reg = <0x00 0x02800000 0x00 0x200>;
0078 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0079 current-speed = <115200>;
0080 clocks = <&k3_clks 146 3>;
0081 clock-names = "fclk";
0082 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0083 };
0084
0085 main_uart1: serial@2810000 {
0086 compatible = "ti,j721e-uart", "ti,am654-uart";
0087 reg = <0x00 0x02810000 0x00 0x200>;
0088 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0089 current-speed = <115200>;
0090 clocks = <&k3_clks 350 3>;
0091 clock-names = "fclk";
0092 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
0093 };
0094
0095 main_uart2: serial@2820000 {
0096 compatible = "ti,j721e-uart", "ti,am654-uart";
0097 reg = <0x00 0x02820000 0x00 0x200>;
0098 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0099 current-speed = <115200>;
0100 clocks = <&k3_clks 351 3>;
0101 clock-names = "fclk";
0102 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
0103 };
0104
0105 main_uart3: serial@2830000 {
0106 compatible = "ti,j721e-uart", "ti,am654-uart";
0107 reg = <0x00 0x02830000 0x00 0x200>;
0108 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0109 current-speed = <115200>;
0110 clocks = <&k3_clks 352 3>;
0111 clock-names = "fclk";
0112 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
0113 };
0114
0115 main_uart4: serial@2840000 {
0116 compatible = "ti,j721e-uart", "ti,am654-uart";
0117 reg = <0x00 0x02840000 0x00 0x200>;
0118 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0119 current-speed = <115200>;
0120 clocks = <&k3_clks 353 3>;
0121 clock-names = "fclk";
0122 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
0123 };
0124
0125 main_uart5: serial@2850000 {
0126 compatible = "ti,j721e-uart", "ti,am654-uart";
0127 reg = <0x00 0x02850000 0x00 0x200>;
0128 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0129 current-speed = <115200>;
0130 clocks = <&k3_clks 354 3>;
0131 clock-names = "fclk";
0132 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
0133 };
0134
0135 main_uart6: serial@2860000 {
0136 compatible = "ti,j721e-uart", "ti,am654-uart";
0137 reg = <0x00 0x02860000 0x00 0x200>;
0138 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
0139 current-speed = <115200>;
0140 clocks = <&k3_clks 355 3>;
0141 clock-names = "fclk";
0142 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
0143 };
0144
0145 main_uart7: serial@2870000 {
0146 compatible = "ti,j721e-uart", "ti,am654-uart";
0147 reg = <0x00 0x02870000 0x00 0x200>;
0148 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
0149 current-speed = <115200>;
0150 clocks = <&k3_clks 356 3>;
0151 clock-names = "fclk";
0152 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
0153 };
0154
0155 main_uart8: serial@2880000 {
0156 compatible = "ti,j721e-uart", "ti,am654-uart";
0157 reg = <0x00 0x02880000 0x00 0x200>;
0158 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
0159 current-speed = <115200>;
0160 clocks = <&k3_clks 357 3>;
0161 clock-names = "fclk";
0162 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
0163 };
0164
0165 main_uart9: serial@2890000 {
0166 compatible = "ti,j721e-uart", "ti,am654-uart";
0167 reg = <0x00 0x02890000 0x00 0x200>;
0168 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0169 current-speed = <115200>;
0170 clocks = <&k3_clks 358 3>;
0171 clock-names = "fclk";
0172 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
0173 };
0174
0175 main_gpio0: gpio@600000 {
0176 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0177 reg = <0x00 0x00600000 0x00 0x100>;
0178 gpio-controller;
0179 #gpio-cells = <2>;
0180 interrupt-parent = <&main_gpio_intr>;
0181 interrupts = <145>, <146>, <147>, <148>, <149>;
0182 interrupt-controller;
0183 #interrupt-cells = <2>;
0184 ti,ngpio = <66>;
0185 ti,davinci-gpio-unbanked = <0>;
0186 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
0187 clocks = <&k3_clks 111 0>;
0188 clock-names = "gpio";
0189 };
0190
0191 main_gpio2: gpio@610000 {
0192 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0193 reg = <0x00 0x00610000 0x00 0x100>;
0194 gpio-controller;
0195 #gpio-cells = <2>;
0196 interrupt-parent = <&main_gpio_intr>;
0197 interrupts = <154>, <155>, <156>, <157>, <158>;
0198 interrupt-controller;
0199 #interrupt-cells = <2>;
0200 ti,ngpio = <66>;
0201 ti,davinci-gpio-unbanked = <0>;
0202 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
0203 clocks = <&k3_clks 112 0>;
0204 clock-names = "gpio";
0205 };
0206
0207 main_gpio4: gpio@620000 {
0208 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0209 reg = <0x00 0x00620000 0x00 0x100>;
0210 gpio-controller;
0211 #gpio-cells = <2>;
0212 interrupt-parent = <&main_gpio_intr>;
0213 interrupts = <163>, <164>, <165>, <166>, <167>;
0214 interrupt-controller;
0215 #interrupt-cells = <2>;
0216 ti,ngpio = <66>;
0217 ti,davinci-gpio-unbanked = <0>;
0218 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
0219 clocks = <&k3_clks 113 0>;
0220 clock-names = "gpio";
0221 };
0222
0223 main_gpio6: gpio@630000 {
0224 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0225 reg = <0x00 0x00630000 0x00 0x100>;
0226 gpio-controller;
0227 #gpio-cells = <2>;
0228 interrupt-parent = <&main_gpio_intr>;
0229 interrupts = <172>, <173>, <174>, <175>, <176>;
0230 interrupt-controller;
0231 #interrupt-cells = <2>;
0232 ti,ngpio = <66>;
0233 ti,davinci-gpio-unbanked = <0>;
0234 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
0235 clocks = <&k3_clks 114 0>;
0236 clock-names = "gpio";
0237 };
0238
0239 main_i2c0: i2c@2000000 {
0240 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0241 reg = <0x00 0x02000000 0x00 0x100>;
0242 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 clocks = <&k3_clks 214 1>;
0246 clock-names = "fck";
0247 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
0248 };
0249
0250 main_i2c1: i2c@2010000 {
0251 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0252 reg = <0x00 0x02010000 0x00 0x100>;
0253 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 clocks = <&k3_clks 215 1>;
0257 clock-names = "fck";
0258 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
0259 };
0260
0261 main_i2c2: i2c@2020000 {
0262 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0263 reg = <0x00 0x02020000 0x00 0x100>;
0264 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
0265 #address-cells = <1>;
0266 #size-cells = <0>;
0267 clocks = <&k3_clks 216 1>;
0268 clock-names = "fck";
0269 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
0270 };
0271
0272 main_i2c3: i2c@2030000 {
0273 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0274 reg = <0x00 0x02030000 0x00 0x100>;
0275 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 clocks = <&k3_clks 217 1>;
0279 clock-names = "fck";
0280 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
0281 };
0282
0283 main_i2c4: i2c@2040000 {
0284 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0285 reg = <0x00 0x02040000 0x00 0x100>;
0286 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
0287 #address-cells = <1>;
0288 #size-cells = <0>;
0289 clocks = <&k3_clks 218 1>;
0290 clock-names = "fck";
0291 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
0292 };
0293
0294 main_i2c5: i2c@2050000 {
0295 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0296 reg = <0x00 0x02050000 0x00 0x100>;
0297 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
0298 #address-cells = <1>;
0299 #size-cells = <0>;
0300 clocks = <&k3_clks 219 1>;
0301 clock-names = "fck";
0302 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
0303 };
0304
0305 main_i2c6: i2c@2060000 {
0306 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
0307 reg = <0x00 0x02060000 0x00 0x100>;
0308 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
0309 #address-cells = <1>;
0310 #size-cells = <0>;
0311 clocks = <&k3_clks 220 1>;
0312 clock-names = "fck";
0313 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
0314 };
0315
0316 main_sdhci0: mmc@4f80000 {
0317 compatible = "ti,j721e-sdhci-8bit";
0318 reg = <0x00 0x04f80000 0x00 0x1000>,
0319 <0x00 0x04f88000 0x00 0x400>;
0320 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0321 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
0322 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
0323 clock-names = "clk_ahb", "clk_xin";
0324 assigned-clocks = <&k3_clks 98 1>;
0325 assigned-clock-parents = <&k3_clks 98 2>;
0326 bus-width = <8>;
0327 ti,otap-del-sel-legacy = <0x0>;
0328 ti,otap-del-sel-mmc-hs = <0x0>;
0329 ti,otap-del-sel-ddr52 = <0x6>;
0330 ti,otap-del-sel-hs200 = <0x8>;
0331 ti,otap-del-sel-hs400 = <0x5>;
0332 ti,itap-del-sel-legacy = <0x10>;
0333 ti,itap-del-sel-mmc-hs = <0xa>;
0334 ti,strobe-sel = <0x77>;
0335 ti,clkbuf-sel = <0x7>;
0336 ti,trm-icp = <0x8>;
0337 mmc-ddr-1_8v;
0338 mmc-hs200-1_8v;
0339 mmc-hs400-1_8v;
0340 dma-coherent;
0341 };
0342
0343 main_sdhci1: mmc@4fb0000 {
0344 compatible = "ti,j721e-sdhci-4bit";
0345 reg = <0x00 0x04fb0000 0x00 0x1000>,
0346 <0x00 0x04fb8000 0x00 0x400>;
0347 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0348 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
0349 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
0350 clock-names = "clk_ahb", "clk_xin";
0351 assigned-clocks = <&k3_clks 99 1>;
0352 assigned-clock-parents = <&k3_clks 99 2>;
0353 bus-width = <4>;
0354 ti,otap-del-sel-legacy = <0x0>;
0355 ti,otap-del-sel-sd-hs = <0x0>;
0356 ti,otap-del-sel-sdr12 = <0xf>;
0357 ti,otap-del-sel-sdr25 = <0xf>;
0358 ti,otap-del-sel-sdr50 = <0xc>;
0359 ti,otap-del-sel-sdr104 = <0x5>;
0360 ti,otap-del-sel-ddr50 = <0xc>;
0361 ti,itap-del-sel-legacy = <0x0>;
0362 ti,itap-del-sel-sd-hs = <0x0>;
0363 ti,itap-del-sel-sdr12 = <0x0>;
0364 ti,itap-del-sel-sdr25 = <0x0>;
0365 ti,clkbuf-sel = <0x7>;
0366 ti,trm-icp = <0x8>;
0367 dma-coherent;
0368 /* Masking support for SDR104 capability */
0369 sdhci-caps-mask = <0x00000003 0x00000000>;
0370 };
0371
0372 main_navss: bus@30000000 {
0373 compatible = "simple-mfd";
0374 #address-cells = <2>;
0375 #size-cells = <2>;
0376 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
0377 ti,sci-dev-id = <224>;
0378 dma-coherent;
0379 dma-ranges;
0380
0381 main_navss_intr: interrupt-controller@310e0000 {
0382 compatible = "ti,sci-intr";
0383 reg = <0x00 0x310e0000 0x00 0x4000>;
0384 ti,intr-trigger-type = <4>;
0385 interrupt-controller;
0386 interrupt-parent = <&gic500>;
0387 #interrupt-cells = <1>;
0388 ti,sci = <&sms>;
0389 ti,sci-dev-id = <227>;
0390 ti,interrupt-ranges = <0 64 64>,
0391 <64 448 64>,
0392 <128 672 64>;
0393 };
0394
0395 main_udmass_inta: msi-controller@33d00000 {
0396 compatible = "ti,sci-inta";
0397 reg = <0x00 0x33d00000 0x00 0x100000>;
0398 interrupt-controller;
0399 #interrupt-cells = <0>;
0400 interrupt-parent = <&main_navss_intr>;
0401 msi-controller;
0402 ti,sci = <&sms>;
0403 ti,sci-dev-id = <265>;
0404 ti,interrupt-ranges = <0 0 256>;
0405 };
0406
0407 secure_proxy_main: mailbox@32c00000 {
0408 compatible = "ti,am654-secure-proxy";
0409 #mbox-cells = <1>;
0410 reg-names = "target_data", "rt", "scfg";
0411 reg = <0x00 0x32c00000 0x00 0x100000>,
0412 <0x00 0x32400000 0x00 0x100000>,
0413 <0x00 0x32800000 0x00 0x100000>;
0414 interrupt-names = "rx_011";
0415 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0416 };
0417
0418 hwspinlock: spinlock@30e00000 {
0419 compatible = "ti,am654-hwspinlock";
0420 reg = <0x00 0x30e00000 0x00 0x1000>;
0421 #hwlock-cells = <1>;
0422 };
0423
0424 mailbox0_cluster0: mailbox@31f80000 {
0425 compatible = "ti,am654-mailbox";
0426 reg = <0x00 0x31f80000 0x00 0x200>;
0427 #mbox-cells = <1>;
0428 ti,mbox-num-users = <4>;
0429 ti,mbox-num-fifos = <16>;
0430 interrupt-parent = <&main_navss_intr>;
0431 };
0432
0433 mailbox0_cluster1: mailbox@31f81000 {
0434 compatible = "ti,am654-mailbox";
0435 reg = <0x00 0x31f81000 0x00 0x200>;
0436 #mbox-cells = <1>;
0437 ti,mbox-num-users = <4>;
0438 ti,mbox-num-fifos = <16>;
0439 interrupt-parent = <&main_navss_intr>;
0440 };
0441
0442 mailbox0_cluster2: mailbox@31f82000 {
0443 compatible = "ti,am654-mailbox";
0444 reg = <0x00 0x31f82000 0x00 0x200>;
0445 #mbox-cells = <1>;
0446 ti,mbox-num-users = <4>;
0447 ti,mbox-num-fifos = <16>;
0448 interrupt-parent = <&main_navss_intr>;
0449 };
0450
0451 mailbox0_cluster3: mailbox@31f83000 {
0452 compatible = "ti,am654-mailbox";
0453 reg = <0x00 0x31f83000 0x00 0x200>;
0454 #mbox-cells = <1>;
0455 ti,mbox-num-users = <4>;
0456 ti,mbox-num-fifos = <16>;
0457 interrupt-parent = <&main_navss_intr>;
0458 };
0459
0460 mailbox0_cluster4: mailbox@31f84000 {
0461 compatible = "ti,am654-mailbox";
0462 reg = <0x00 0x31f84000 0x00 0x200>;
0463 #mbox-cells = <1>;
0464 ti,mbox-num-users = <4>;
0465 ti,mbox-num-fifos = <16>;
0466 interrupt-parent = <&main_navss_intr>;
0467 };
0468
0469 mailbox0_cluster5: mailbox@31f85000 {
0470 compatible = "ti,am654-mailbox";
0471 reg = <0x00 0x31f85000 0x00 0x200>;
0472 #mbox-cells = <1>;
0473 ti,mbox-num-users = <4>;
0474 ti,mbox-num-fifos = <16>;
0475 interrupt-parent = <&main_navss_intr>;
0476 };
0477
0478 mailbox0_cluster6: mailbox@31f86000 {
0479 compatible = "ti,am654-mailbox";
0480 reg = <0x00 0x31f86000 0x00 0x200>;
0481 #mbox-cells = <1>;
0482 ti,mbox-num-users = <4>;
0483 ti,mbox-num-fifos = <16>;
0484 interrupt-parent = <&main_navss_intr>;
0485 };
0486
0487 mailbox0_cluster7: mailbox@31f87000 {
0488 compatible = "ti,am654-mailbox";
0489 reg = <0x00 0x31f87000 0x00 0x200>;
0490 #mbox-cells = <1>;
0491 ti,mbox-num-users = <4>;
0492 ti,mbox-num-fifos = <16>;
0493 interrupt-parent = <&main_navss_intr>;
0494 };
0495
0496 mailbox0_cluster8: mailbox@31f88000 {
0497 compatible = "ti,am654-mailbox";
0498 reg = <0x00 0x31f88000 0x00 0x200>;
0499 #mbox-cells = <1>;
0500 ti,mbox-num-users = <4>;
0501 ti,mbox-num-fifos = <16>;
0502 interrupt-parent = <&main_navss_intr>;
0503 };
0504
0505 mailbox0_cluster9: mailbox@31f89000 {
0506 compatible = "ti,am654-mailbox";
0507 reg = <0x00 0x31f89000 0x00 0x200>;
0508 #mbox-cells = <1>;
0509 ti,mbox-num-users = <4>;
0510 ti,mbox-num-fifos = <16>;
0511 interrupt-parent = <&main_navss_intr>;
0512 };
0513
0514 mailbox0_cluster10: mailbox@31f8a000 {
0515 compatible = "ti,am654-mailbox";
0516 reg = <0x00 0x31f8a000 0x00 0x200>;
0517 #mbox-cells = <1>;
0518 ti,mbox-num-users = <4>;
0519 ti,mbox-num-fifos = <16>;
0520 interrupt-parent = <&main_navss_intr>;
0521 };
0522
0523 mailbox0_cluster11: mailbox@31f8b000 {
0524 compatible = "ti,am654-mailbox";
0525 reg = <0x00 0x31f8b000 0x00 0x200>;
0526 #mbox-cells = <1>;
0527 ti,mbox-num-users = <4>;
0528 ti,mbox-num-fifos = <16>;
0529 interrupt-parent = <&main_navss_intr>;
0530 };
0531
0532 mailbox1_cluster0: mailbox@31f90000 {
0533 compatible = "ti,am654-mailbox";
0534 reg = <0x00 0x31f90000 0x00 0x200>;
0535 #mbox-cells = <1>;
0536 ti,mbox-num-users = <4>;
0537 ti,mbox-num-fifos = <16>;
0538 interrupt-parent = <&main_navss_intr>;
0539 };
0540
0541 mailbox1_cluster1: mailbox@31f91000 {
0542 compatible = "ti,am654-mailbox";
0543 reg = <0x00 0x31f91000 0x00 0x200>;
0544 #mbox-cells = <1>;
0545 ti,mbox-num-users = <4>;
0546 ti,mbox-num-fifos = <16>;
0547 interrupt-parent = <&main_navss_intr>;
0548 };
0549
0550 mailbox1_cluster2: mailbox@31f92000 {
0551 compatible = "ti,am654-mailbox";
0552 reg = <0x00 0x31f92000 0x00 0x200>;
0553 #mbox-cells = <1>;
0554 ti,mbox-num-users = <4>;
0555 ti,mbox-num-fifos = <16>;
0556 interrupt-parent = <&main_navss_intr>;
0557 };
0558
0559 mailbox1_cluster3: mailbox@31f93000 {
0560 compatible = "ti,am654-mailbox";
0561 reg = <0x00 0x31f93000 0x00 0x200>;
0562 #mbox-cells = <1>;
0563 ti,mbox-num-users = <4>;
0564 ti,mbox-num-fifos = <16>;
0565 interrupt-parent = <&main_navss_intr>;
0566 };
0567
0568 mailbox1_cluster4: mailbox@31f94000 {
0569 compatible = "ti,am654-mailbox";
0570 reg = <0x00 0x31f94000 0x00 0x200>;
0571 #mbox-cells = <1>;
0572 ti,mbox-num-users = <4>;
0573 ti,mbox-num-fifos = <16>;
0574 interrupt-parent = <&main_navss_intr>;
0575 };
0576
0577 mailbox1_cluster5: mailbox@31f95000 {
0578 compatible = "ti,am654-mailbox";
0579 reg = <0x00 0x31f95000 0x00 0x200>;
0580 #mbox-cells = <1>;
0581 ti,mbox-num-users = <4>;
0582 ti,mbox-num-fifos = <16>;
0583 interrupt-parent = <&main_navss_intr>;
0584 };
0585
0586 mailbox1_cluster6: mailbox@31f96000 {
0587 compatible = "ti,am654-mailbox";
0588 reg = <0x00 0x31f96000 0x00 0x200>;
0589 #mbox-cells = <1>;
0590 ti,mbox-num-users = <4>;
0591 ti,mbox-num-fifos = <16>;
0592 interrupt-parent = <&main_navss_intr>;
0593 };
0594
0595 mailbox1_cluster7: mailbox@31f97000 {
0596 compatible = "ti,am654-mailbox";
0597 reg = <0x00 0x31f97000 0x00 0x200>;
0598 #mbox-cells = <1>;
0599 ti,mbox-num-users = <4>;
0600 ti,mbox-num-fifos = <16>;
0601 interrupt-parent = <&main_navss_intr>;
0602 };
0603
0604 mailbox1_cluster8: mailbox@31f98000 {
0605 compatible = "ti,am654-mailbox";
0606 reg = <0x00 0x31f98000 0x00 0x200>;
0607 #mbox-cells = <1>;
0608 ti,mbox-num-users = <4>;
0609 ti,mbox-num-fifos = <16>;
0610 interrupt-parent = <&main_navss_intr>;
0611 };
0612
0613 mailbox1_cluster9: mailbox@31f99000 {
0614 compatible = "ti,am654-mailbox";
0615 reg = <0x00 0x31f99000 0x00 0x200>;
0616 #mbox-cells = <1>;
0617 ti,mbox-num-users = <4>;
0618 ti,mbox-num-fifos = <16>;
0619 interrupt-parent = <&main_navss_intr>;
0620 };
0621
0622 mailbox1_cluster10: mailbox@31f9a000 {
0623 compatible = "ti,am654-mailbox";
0624 reg = <0x00 0x31f9a000 0x00 0x200>;
0625 #mbox-cells = <1>;
0626 ti,mbox-num-users = <4>;
0627 ti,mbox-num-fifos = <16>;
0628 interrupt-parent = <&main_navss_intr>;
0629 };
0630
0631 mailbox1_cluster11: mailbox@31f9b000 {
0632 compatible = "ti,am654-mailbox";
0633 reg = <0x00 0x31f9b000 0x00 0x200>;
0634 #mbox-cells = <1>;
0635 ti,mbox-num-users = <4>;
0636 ti,mbox-num-fifos = <16>;
0637 interrupt-parent = <&main_navss_intr>;
0638 };
0639
0640 main_ringacc: ringacc@3c000000 {
0641 compatible = "ti,am654-navss-ringacc";
0642 reg = <0x0 0x3c000000 0x0 0x400000>,
0643 <0x0 0x38000000 0x0 0x400000>,
0644 <0x0 0x31120000 0x0 0x100>,
0645 <0x0 0x33000000 0x0 0x40000>;
0646 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0647 ti,num-rings = <1024>;
0648 ti,sci-rm-range-gp-rings = <0x1>;
0649 ti,sci = <&sms>;
0650 ti,sci-dev-id = <259>;
0651 msi-parent = <&main_udmass_inta>;
0652 };
0653
0654 main_udmap: dma-controller@31150000 {
0655 compatible = "ti,j721e-navss-main-udmap";
0656 reg = <0x0 0x31150000 0x0 0x100>,
0657 <0x0 0x34000000 0x0 0x80000>,
0658 <0x0 0x35000000 0x0 0x200000>;
0659 reg-names = "gcfg", "rchanrt", "tchanrt";
0660 msi-parent = <&main_udmass_inta>;
0661 #dma-cells = <1>;
0662
0663 ti,sci = <&sms>;
0664 ti,sci-dev-id = <263>;
0665 ti,ringacc = <&main_ringacc>;
0666
0667 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0668 <0x0f>, /* TX_HCHAN */
0669 <0x10>; /* TX_UHCHAN */
0670 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0671 <0x0b>, /* RX_HCHAN */
0672 <0x0c>; /* RX_UHCHAN */
0673 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0674 };
0675
0676 cpts@310d0000 {
0677 compatible = "ti,j721e-cpts";
0678 reg = <0x0 0x310d0000 0x0 0x400>;
0679 reg-names = "cpts";
0680 clocks = <&k3_clks 226 5>;
0681 clock-names = "cpts";
0682 interrupts-extended = <&main_navss_intr 391>;
0683 interrupt-names = "cpts";
0684 ti,cpts-periodic-outputs = <6>;
0685 ti,cpts-ext-ts-inputs = <8>;
0686 };
0687 };
0688
0689 main_mcan0: can@2701000 {
0690 compatible = "bosch,m_can";
0691 reg = <0x00 0x02701000 0x00 0x200>,
0692 <0x00 0x02708000 0x00 0x8000>;
0693 reg-names = "m_can", "message_ram";
0694 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
0695 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
0696 clock-names = "hclk", "cclk";
0697 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0698 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0699 interrupt-names = "int0", "int1";
0700 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0701 };
0702
0703 main_mcan1: can@2711000 {
0704 compatible = "bosch,m_can";
0705 reg = <0x00 0x02711000 0x00 0x200>,
0706 <0x00 0x02718000 0x00 0x8000>;
0707 reg-names = "m_can", "message_ram";
0708 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
0709 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
0710 clock-names = "hclk", "cclk";
0711 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0712 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0713 interrupt-names = "int0", "int1";
0714 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0715 };
0716
0717 main_mcan2: can@2721000 {
0718 compatible = "bosch,m_can";
0719 reg = <0x00 0x02721000 0x00 0x200>,
0720 <0x00 0x02728000 0x00 0x8000>;
0721 reg-names = "m_can", "message_ram";
0722 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
0723 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
0724 clock-names = "hclk", "cclk";
0725 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0726 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0727 interrupt-names = "int0", "int1";
0728 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0729 };
0730
0731 main_mcan3: can@2731000 {
0732 compatible = "bosch,m_can";
0733 reg = <0x00 0x02731000 0x00 0x200>,
0734 <0x00 0x02738000 0x00 0x8000>;
0735 reg-names = "m_can", "message_ram";
0736 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
0737 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
0738 clock-names = "hclk", "cclk";
0739 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0740 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0741 interrupt-names = "int0", "int1";
0742 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0743 };
0744
0745 main_mcan4: can@2741000 {
0746 compatible = "bosch,m_can";
0747 reg = <0x00 0x02741000 0x00 0x200>,
0748 <0x00 0x02748000 0x00 0x8000>;
0749 reg-names = "m_can", "message_ram";
0750 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
0751 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
0752 clock-names = "hclk", "cclk";
0753 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0754 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
0755 interrupt-names = "int0", "int1";
0756 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0757 };
0758
0759 main_mcan5: can@2751000 {
0760 compatible = "bosch,m_can";
0761 reg = <0x00 0x02751000 0x00 0x200>,
0762 <0x00 0x02758000 0x00 0x8000>;
0763 reg-names = "m_can", "message_ram";
0764 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
0765 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
0766 clock-names = "hclk", "cclk";
0767 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0768 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0769 interrupt-names = "int0", "int1";
0770 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0771 };
0772
0773 main_mcan6: can@2761000 {
0774 compatible = "bosch,m_can";
0775 reg = <0x00 0x02761000 0x00 0x200>,
0776 <0x00 0x02768000 0x00 0x8000>;
0777 reg-names = "m_can", "message_ram";
0778 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
0779 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
0780 clock-names = "hclk", "cclk";
0781 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0782 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0783 interrupt-names = "int0", "int1";
0784 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0785 };
0786
0787 main_mcan7: can@2771000 {
0788 compatible = "bosch,m_can";
0789 reg = <0x00 0x02771000 0x00 0x200>,
0790 <0x00 0x02778000 0x00 0x8000>;
0791 reg-names = "m_can", "message_ram";
0792 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
0793 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
0794 clock-names = "hclk", "cclk";
0795 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0796 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0797 interrupt-names = "int0", "int1";
0798 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0799 };
0800
0801 main_mcan8: can@2781000 {
0802 compatible = "bosch,m_can";
0803 reg = <0x00 0x02781000 0x00 0x200>,
0804 <0x00 0x02788000 0x00 0x8000>;
0805 reg-names = "m_can", "message_ram";
0806 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
0807 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
0808 clock-names = "hclk", "cclk";
0809 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
0810 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
0811 interrupt-names = "int0", "int1";
0812 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0813 };
0814
0815 main_mcan9: can@2791000 {
0816 compatible = "bosch,m_can";
0817 reg = <0x00 0x02791000 0x00 0x200>,
0818 <0x00 0x02798000 0x00 0x8000>;
0819 reg-names = "m_can", "message_ram";
0820 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
0821 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
0822 clock-names = "hclk", "cclk";
0823 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
0824 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
0825 interrupt-names = "int0", "int1";
0826 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0827 };
0828
0829 main_mcan10: can@27a1000 {
0830 compatible = "bosch,m_can";
0831 reg = <0x00 0x027a1000 0x00 0x200>,
0832 <0x00 0x027a8000 0x00 0x8000>;
0833 reg-names = "m_can", "message_ram";
0834 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
0835 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
0836 clock-names = "hclk", "cclk";
0837 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
0838 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
0839 interrupt-names = "int0", "int1";
0840 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0841 };
0842
0843 main_mcan11: can@27b1000 {
0844 compatible = "bosch,m_can";
0845 reg = <0x00 0x027b1000 0x00 0x200>,
0846 <0x00 0x027b8000 0x00 0x8000>;
0847 reg-names = "m_can", "message_ram";
0848 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
0849 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
0850 clock-names = "hclk", "cclk";
0851 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
0852 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
0853 interrupt-names = "int0", "int1";
0854 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0855 };
0856
0857 main_mcan12: can@27c1000 {
0858 compatible = "bosch,m_can";
0859 reg = <0x00 0x027c1000 0x00 0x200>,
0860 <0x00 0x027c8000 0x00 0x8000>;
0861 reg-names = "m_can", "message_ram";
0862 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
0863 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
0864 clock-names = "hclk", "cclk";
0865 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
0866 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
0867 interrupt-names = "int0", "int1";
0868 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0869 };
0870
0871 main_mcan13: can@27d1000 {
0872 compatible = "bosch,m_can";
0873 reg = <0x00 0x027d1000 0x00 0x200>,
0874 <0x00 0x027d8000 0x00 0x8000>;
0875 reg-names = "m_can", "message_ram";
0876 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
0877 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
0878 clock-names = "hclk", "cclk";
0879 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
0880 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
0881 interrupt-names = "int0", "int1";
0882 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0883 };
0884
0885 main_mcan14: can@2681000 {
0886 compatible = "bosch,m_can";
0887 reg = <0x00 0x02681000 0x00 0x200>,
0888 <0x00 0x02688000 0x00 0x8000>;
0889 reg-names = "m_can", "message_ram";
0890 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
0891 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
0892 clock-names = "hclk", "cclk";
0893 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
0894 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
0895 interrupt-names = "int0", "int1";
0896 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0897 };
0898
0899 main_mcan15: can@2691000 {
0900 compatible = "bosch,m_can";
0901 reg = <0x00 0x02691000 0x00 0x200>,
0902 <0x00 0x02698000 0x00 0x8000>;
0903 reg-names = "m_can", "message_ram";
0904 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
0905 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
0906 clock-names = "hclk", "cclk";
0907 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
0908 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
0909 interrupt-names = "int0", "int1";
0910 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0911 };
0912
0913 main_mcan16: can@26a1000 {
0914 compatible = "bosch,m_can";
0915 reg = <0x00 0x026a1000 0x00 0x200>,
0916 <0x00 0x026a8000 0x00 0x8000>;
0917 reg-names = "m_can", "message_ram";
0918 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
0919 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
0920 clock-names = "hclk", "cclk";
0921 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
0922 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
0923 interrupt-names = "int0", "int1";
0924 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0925 };
0926
0927 main_mcan17: can@26b1000 {
0928 compatible = "bosch,m_can";
0929 reg = <0x00 0x026b1000 0x00 0x200>,
0930 <0x00 0x026b8000 0x00 0x8000>;
0931 reg-names = "m_can", "message_ram";
0932 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
0933 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
0934 clock-names = "hclk", "cclk";
0935 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
0936 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
0937 interrupt-names = "int0", "int1";
0938 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
0939 };
0940 };
