0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
0004 *
0005 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "k3-j721e.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/input/input.h>
0013 #include <dt-bindings/net/ti-dp83867.h>
0014
0015 / {
0016 compatible = "ti,j721e-sk", "ti,j721e";
0017 model = "Texas Instruments J721E SK";
0018
0019 chosen {
0020 stdout-path = "serial2:115200n8";
0021 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
0022 };
0023
0024 memory@80000000 {
0025 device_type = "memory";
0026 /* 4G RAM */
0027 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
0028 <0x00000008 0x80000000 0x00000000 0x80000000>;
0029 };
0030
0031 reserved_memory: reserved-memory {
0032 #address-cells = <2>;
0033 #size-cells = <2>;
0034 ranges;
0035
0036 secure_ddr: optee@9e800000 {
0037 reg = <0x00 0x9e800000 0x00 0x01800000>;
0038 alignment = <0x1000>;
0039 no-map;
0040 };
0041
0042 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
0043 compatible = "shared-dma-pool";
0044 reg = <0x00 0xa0000000 0x00 0x100000>;
0045 no-map;
0046 };
0047
0048 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
0049 compatible = "shared-dma-pool";
0050 reg = <0x00 0xa0100000 0x00 0xf00000>;
0051 no-map;
0052 };
0053
0054 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
0055 compatible = "shared-dma-pool";
0056 reg = <0x00 0xa1000000 0x00 0x100000>;
0057 no-map;
0058 };
0059
0060 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
0061 compatible = "shared-dma-pool";
0062 reg = <0x00 0xa1100000 0x00 0xf00000>;
0063 no-map;
0064 };
0065
0066 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
0067 compatible = "shared-dma-pool";
0068 reg = <0x00 0xa2000000 0x00 0x100000>;
0069 no-map;
0070 };
0071
0072 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
0073 compatible = "shared-dma-pool";
0074 reg = <0x00 0xa2100000 0x00 0xf00000>;
0075 no-map;
0076 };
0077
0078 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
0079 compatible = "shared-dma-pool";
0080 reg = <0x00 0xa3000000 0x00 0x100000>;
0081 no-map;
0082 };
0083
0084 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
0085 compatible = "shared-dma-pool";
0086 reg = <0x00 0xa3100000 0x00 0xf00000>;
0087 no-map;
0088 };
0089
0090 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
0091 compatible = "shared-dma-pool";
0092 reg = <0x00 0xa4000000 0x00 0x100000>;
0093 no-map;
0094 };
0095
0096 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
0097 compatible = "shared-dma-pool";
0098 reg = <0x00 0xa4100000 0x00 0xf00000>;
0099 no-map;
0100 };
0101
0102 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
0103 compatible = "shared-dma-pool";
0104 reg = <0x00 0xa5000000 0x00 0x100000>;
0105 no-map;
0106 };
0107
0108 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
0109 compatible = "shared-dma-pool";
0110 reg = <0x00 0xa5100000 0x00 0xf00000>;
0111 no-map;
0112 };
0113
0114 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
0115 compatible = "shared-dma-pool";
0116 reg = <0x00 0xa6000000 0x00 0x100000>;
0117 no-map;
0118 };
0119
0120 c66_0_memory_region: c66-memory@a6100000 {
0121 compatible = "shared-dma-pool";
0122 reg = <0x00 0xa6100000 0x00 0xf00000>;
0123 no-map;
0124 };
0125
0126 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
0127 compatible = "shared-dma-pool";
0128 reg = <0x00 0xa7000000 0x00 0x100000>;
0129 no-map;
0130 };
0131
0132 c66_1_memory_region: c66-memory@a7100000 {
0133 compatible = "shared-dma-pool";
0134 reg = <0x00 0xa7100000 0x00 0xf00000>;
0135 no-map;
0136 };
0137
0138 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
0139 compatible = "shared-dma-pool";
0140 reg = <0x00 0xa8000000 0x00 0x100000>;
0141 no-map;
0142 };
0143
0144 c71_0_memory_region: c71-memory@a8100000 {
0145 compatible = "shared-dma-pool";
0146 reg = <0x00 0xa8100000 0x00 0xf00000>;
0147 no-map;
0148 };
0149
0150 rtos_ipc_memory_region: ipc-memories@aa000000 {
0151 reg = <0x00 0xaa000000 0x00 0x01c00000>;
0152 alignment = <0x1000>;
0153 no-map;
0154 };
0155 };
0156
0157 vusb_main: fixedregulator-vusb-main5v0 {
0158 /* USB MAIN INPUT 5V DC */
0159 compatible = "regulator-fixed";
0160 regulator-name = "vusb-main5v0";
0161 regulator-min-microvolt = <5000000>;
0162 regulator-max-microvolt = <5000000>;
0163 regulator-always-on;
0164 regulator-boot-on;
0165 };
0166
0167 vsys_3v3: fixedregulator-vsys3v3 {
0168 /* Output of LM5141 */
0169 compatible = "regulator-fixed";
0170 regulator-name = "vsys_3v3";
0171 regulator-min-microvolt = <3300000>;
0172 regulator-max-microvolt = <3300000>;
0173 vin-supply = <&vusb_main>;
0174 regulator-always-on;
0175 regulator-boot-on;
0176 };
0177
0178 vdd_mmc1: fixedregulator-sd {
0179 compatible = "regulator-fixed";
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
0182 regulator-name = "vdd_mmc1";
0183 regulator-min-microvolt = <3300000>;
0184 regulator-max-microvolt = <3300000>;
0185 regulator-boot-on;
0186 enable-active-high;
0187 vin-supply = <&vsys_3v3>;
0188 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
0189 };
0190
0191 vdd_sd_dv_alt: gpio-regulator-tps659411 {
0192 compatible = "regulator-gpio";
0193 pinctrl-names = "default";
0194 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
0195 regulator-name = "tps659411";
0196 regulator-min-microvolt = <1800000>;
0197 regulator-max-microvolt = <3300000>;
0198 regulator-boot-on;
0199 vin-supply = <&vsys_3v3>;
0200 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
0201 states = <1800000 0x0>,
0202 <3300000 0x1>;
0203 };
0204
0205 dp_pwr_3v3: fixedregulator-dp-prw {
0206 compatible = "regulator-fixed";
0207 regulator-name = "dp-pwr";
0208 regulator-min-microvolt = <3300000>;
0209 regulator-max-microvolt = <3300000>;
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&dp_pwr_en_pins_default>;
0212 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
0213 enable-active-high;
0214 };
0215
0216 dp0: connector {
0217 compatible = "dp-connector";
0218 label = "DP0";
0219 type = "full-size";
0220 dp-pwr-supply = <&dp_pwr_3v3>;
0221
0222 port {
0223 dp_connector_in: endpoint {
0224 remote-endpoint = <&dp0_out>;
0225 };
0226 };
0227 };
0228
0229 hdmi-connector {
0230 compatible = "hdmi-connector";
0231 label = "hdmi";
0232 type = "a";
0233
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&hdmi_hpd_pins_default>;
0236
0237 ddc-i2c-bus = <&main_i2c1>;
0238
0239 /* HDMI_HPD */
0240 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
0241
0242 port {
0243 hdmi_connector_in: endpoint {
0244 remote-endpoint = <&tfp410_out>;
0245 };
0246 };
0247 };
0248
0249 dvi-bridge {
0250 compatible = "ti,tfp410";
0251
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&hdmi_pdn_pins_default>;
0254
0255 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
0256 ti,deskew = <0>;
0257
0258 ports {
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261
0262 port@0 {
0263 reg = <0>;
0264
0265 tfp410_in: endpoint {
0266 remote-endpoint = <&dpi1_out>;
0267 pclk-sample = <1>;
0268 };
0269 };
0270
0271 port@1 {
0272 reg = <1>;
0273
0274 tfp410_out: endpoint {
0275 remote-endpoint =
0276 <&hdmi_connector_in>;
0277 };
0278 };
0279 };
0280 };
0281 };
0282
0283 &main_pmx0 {
0284 main_mmc1_pins_default: main-mmc1-pins-default {
0285 pinctrl-single,pins = <
0286 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
0287 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
0288 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
0289 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
0290 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
0291 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
0292 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
0293 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
0294 >;
0295 };
0296
0297 main_uart0_pins_default: main-uart0-pins-default {
0298 pinctrl-single,pins = <
0299 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
0300 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
0301 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
0302 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
0303 >;
0304 };
0305
0306 main_i2c0_pins_default: main-i2c0-pins-default {
0307 pinctrl-single,pins = <
0308 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
0309 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
0310 >;
0311 };
0312
0313 main_i2c1_pins_default: main-i2c1-pins-default {
0314 pinctrl-single,pins = <
0315 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
0316 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
0317 >;
0318 };
0319
0320 main_i2c3_pins_default: main-i2c3-pins-default {
0321 pinctrl-single,pins = <
0322 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
0323 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
0324 >;
0325 };
0326
0327 main_usbss0_pins_default: main-usbss0-pins-default {
0328 pinctrl-single,pins = <
0329 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
0330 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
0331 >;
0332 };
0333
0334 main_usbss1_pins_default: main-usbss1-pins-default {
0335 pinctrl-single,pins = <
0336 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
0337 >;
0338 };
0339
0340 dp0_pins_default: dp0-pins-default {
0341 pinctrl-single,pins = <
0342 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
0343 >;
0344 };
0345
0346 dp_pwr_en_pins_default: dp-pwr-en-pins-default {
0347 pinctrl-single,pins = <
0348 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
0349 >;
0350 };
0351
0352 dss_vout0_pins_default: dss-vout0-pins-default {
0353 pinctrl-single,pins = <
0354 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
0355 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
0356 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
0357 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
0358 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
0359 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
0360 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
0361 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
0362 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
0363 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
0364 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
0365 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
0366 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
0367 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
0368 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
0369 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
0370 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
0371 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
0372 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
0373 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
0374 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
0375 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
0376 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
0377 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
0378 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
0379 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
0380 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
0381 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
0382 >;
0383 };
0384
0385 hdmi_hpd_pins_default: hdmi-hpd-pins-default {
0386 pinctrl-single,pins = <
0387 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
0388 >;
0389 };
0390
0391 hdmi_pdn_pins_default: hdmi-pdn-pins-default {
0392 pinctrl-single,pins = <
0393 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
0394 >;
0395 };
0396
0397 /* Reset for M.2 E Key slot on PCIe0 */
0398 ekey_reset_pins_default: ekey-reset-pns-pins-default {
0399 pinctrl-single,pins = <
0400 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
0401 >;
0402 };
0403 };
0404
0405 &wkup_pmx0 {
0406 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
0407 pinctrl-single,pins = <
0408 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
0409 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
0410 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
0411 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
0412 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
0413 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
0414 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
0415 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
0416 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
0417 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
0418 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
0419 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
0420 >;
0421 };
0422
0423 mcu_mdio_pins_default: mcu-mdio1-pins-default {
0424 pinctrl-single,pins = <
0425 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
0426 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
0427 >;
0428 };
0429
0430 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
0431 pinctrl-single,pins = <
0432 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
0433 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
0434 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
0435 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
0436 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
0437 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
0438 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
0439 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
0440 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
0441 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
0442 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
0443 >;
0444 };
0445
0446 vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
0447 pinctrl-single,pins = <
0448 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
0449 >;
0450 };
0451
0452 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
0453 pinctrl-single,pins = <
0454 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
0455 >;
0456 };
0457
0458 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
0459 pinctrl-single,pins = <
0460 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
0461 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
0462 >;
0463 };
0464
0465 /* Reset for M.2 M Key slot on PCIe1 */
0466 mkey_reset_pins_default: mkey-reset-pns-pins-default {
0467 pinctrl-single,pins = <
0468 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
0469 >;
0470 };
0471 };
0472
0473 &wkup_uart0 {
0474 /* Wakeup UART is used by System firmware */
0475 status = "reserved";
0476 };
0477
0478 &main_uart0 {
0479 pinctrl-names = "default";
0480 pinctrl-0 = <&main_uart0_pins_default>;
0481 /* Shared with ATF on this platform */
0482 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
0483 };
0484
0485 &main_uart2 {
0486 /* Brought out on RPi header */
0487 status = "disabled";
0488 };
0489
0490 &main_uart3 {
0491 /* UART not brought out */
0492 status = "disabled";
0493 };
0494
0495 &main_uart5 {
0496 /* UART not brought out */
0497 status = "disabled";
0498 };
0499
0500 &main_uart6 {
0501 /* UART not brought out */
0502 status = "disabled";
0503 };
0504
0505 &main_uart7 {
0506 /* UART not brought out */
0507 status = "disabled";
0508 };
0509
0510 &main_uart8 {
0511 /* UART not brought out */
0512 status = "disabled";
0513 };
0514
0515 &main_uart9 {
0516 /* Brought out on M.2 E Key */
0517 status = "disabled";
0518 };
0519
0520 &main_sdhci0 {
0521 /* Unused */
0522 status = "disabled";
0523 };
0524
0525 &main_sdhci1 {
0526 /* SD Card */
0527 vmmc-supply = <&vdd_mmc1>;
0528 vqmmc-supply = <&vdd_sd_dv_alt>;
0529 pinctrl-names = "default";
0530 pinctrl-0 = <&main_mmc1_pins_default>;
0531 ti,driver-strength-ohm = <50>;
0532 disable-wp;
0533 };
0534
0535 &main_sdhci2 {
0536 /* Unused */
0537 status = "disabled";
0538 };
0539
0540 &ospi0 {
0541 pinctrl-names = "default";
0542 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
0543
0544 flash@0 {
0545 compatible = "jedec,spi-nor";
0546 reg = <0x0>;
0547 spi-tx-bus-width = <8>;
0548 spi-rx-bus-width = <8>;
0549 spi-max-frequency = <25000000>;
0550 cdns,tshsl-ns = <60>;
0551 cdns,tsd2d-ns = <60>;
0552 cdns,tchsh-ns = <60>;
0553 cdns,tslch-ns = <60>;
0554 cdns,read-delay = <4>;
0555 };
0556 };
0557
0558 &ospi1 {
0559 /* Unused */
0560 status = "disabled";
0561 };
0562
0563 &main_i2c0 {
0564 pinctrl-names = "default";
0565 pinctrl-0 = <&main_i2c0_pins_default>;
0566 clock-frequency = <400000>;
0567
0568 i2c-mux@71 {
0569 compatible = "nxp,pca9543";
0570 #address-cells = <1>;
0571 #size-cells = <0>;
0572 reg = <0x71>;
0573
0574 /* PCIe1 M.2 M Key I2C */
0575 i2c@0 {
0576 #address-cells = <1>;
0577 #size-cells = <0>;
0578 reg = <0>;
0579 };
0580
0581 /* PCIe0 M.2 E Key I2C */
0582 i2c@1 {
0583 #address-cells = <1>;
0584 #size-cells = <0>;
0585 reg = <1>;
0586 };
0587 };
0588 };
0589
0590 &main_i2c1 {
0591 pinctrl-names = "default";
0592 pinctrl-0 = <&main_i2c1_pins_default>;
0593 /* i2c1 is used for DVI DDC, so we need to use 100kHz */
0594 clock-frequency = <100000>;
0595 };
0596
0597 &main_i2c2 {
0598 /* Unused */
0599 status = "disabled";
0600 };
0601
0602 &main_i2c3 {
0603 pinctrl-names = "default";
0604 pinctrl-0 = <&main_i2c3_pins_default>;
0605 clock-frequency = <400000>;
0606
0607 i2c-mux@70 {
0608 compatible = "nxp,pca9543";
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 reg = <0x70>;
0612
0613 /* CSI0 I2C */
0614 i2c@0 {
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 reg = <0>;
0618 };
0619
0620 /* CSI1 I2C */
0621 i2c@1 {
0622 #address-cells = <1>;
0623 #size-cells = <0>;
0624 reg = <1>;
0625 };
0626 };
0627 };
0628
0629 &main_i2c4 {
0630 /* Unused */
0631 status = "disabled";
0632 };
0633
0634 &main_i2c5 {
0635 /* Brought out on RPi Header */
0636 status = "disabled";
0637 };
0638
0639 &main_i2c6 {
0640 /* Unused */
0641 status = "disabled";
0642 };
0643
0644 &main_gpio2 {
0645 status = "disabled";
0646 };
0647
0648 &main_gpio3 {
0649 status = "disabled";
0650 };
0651
0652 &main_gpio4 {
0653 status = "disabled";
0654 };
0655
0656 &main_gpio5 {
0657 status = "disabled";
0658 };
0659
0660 &main_gpio6 {
0661 status = "disabled";
0662 };
0663
0664 &main_gpio7 {
0665 status = "disabled";
0666 };
0667
0668 &wkup_gpio1 {
0669 status = "disabled";
0670 };
0671
0672 &main_r5fss0_core0{
0673 firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
0674 };
0675
0676 &usb_serdes_mux {
0677 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
0678 };
0679
0680 &serdes_ln_ctrl {
0681 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
0682 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
0683 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
0684 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
0685 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
0686 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
0687 };
0688
0689 &serdes_wiz3 {
0690 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
0691 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
0692 };
0693
0694 &serdes3 {
0695 serdes3_usb_link: phy@0 {
0696 reg = <0>;
0697 cdns,num-lanes = <2>;
0698 #phy-cells = <0>;
0699 cdns,phy-type = <PHY_TYPE_USB3>;
0700 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
0701 };
0702 };
0703
0704 &serdes4 {
0705 torrent_phy_dp: phy@0 {
0706 reg = <0>;
0707 resets = <&serdes_wiz4 1>;
0708 cdns,phy-type = <PHY_TYPE_DP>;
0709 cdns,num-lanes = <4>;
0710 cdns,max-bit-rate = <5400>;
0711 #phy-cells = <0>;
0712 };
0713 };
0714
0715 &mhdp {
0716 phys = <&torrent_phy_dp>;
0717 phy-names = "dpphy";
0718 pinctrl-names = "default";
0719 pinctrl-0 = <&dp0_pins_default>;
0720 };
0721
0722 &usbss0 {
0723 pinctrl-names = "default";
0724 pinctrl-0 = <&main_usbss0_pins_default>;
0725 ti,vbus-divider;
0726 };
0727
0728 &usb0 {
0729 dr_mode = "otg";
0730 maximum-speed = "super-speed";
0731 phys = <&serdes3_usb_link>;
0732 phy-names = "cdns3,usb3-phy";
0733 };
0734
0735 &serdes2 {
0736 serdes2_usb_link: phy@1 {
0737 reg = <1>;
0738 cdns,num-lanes = <1>;
0739 #phy-cells = <0>;
0740 cdns,phy-type = <PHY_TYPE_USB3>;
0741 resets = <&serdes_wiz2 2>;
0742 };
0743 };
0744
0745 &usbss1 {
0746 pinctrl-names = "default";
0747 pinctrl-0 = <&main_usbss1_pins_default>;
0748 ti,vbus-divider;
0749 };
0750
0751 &usb1 {
0752 dr_mode = "host";
0753 maximum-speed = "super-speed";
0754 phys = <&serdes2_usb_link>;
0755 phy-names = "cdns3,usb3-phy";
0756 };
0757
0758 &tscadc0 {
0759 /* Unused */
0760 status = "disabled";
0761 };
0762
0763 &tscadc1 {
0764 /* Unused */
0765 status = "disabled";
0766 };
0767
0768 &mcu_cpsw {
0769 pinctrl-names = "default";
0770 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
0771 };
0772
0773 &davinci_mdio {
0774 phy0: ethernet-phy@0 {
0775 reg = <0>;
0776 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0777 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0778 };
0779 };
0780
0781 &cpsw_port1 {
0782 phy-mode = "rgmii-rxid";
0783 phy-handle = <&phy0>;
0784 };
0785
0786 &dss {
0787 pinctrl-names = "default";
0788 pinctrl-0 = <&dss_vout0_pins_default>;
0789
0790 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
0791 <&k3_clks 152 4>, /* VP 2 pixel clock */
0792 <&k3_clks 152 9>, /* VP 3 pixel clock */
0793 <&k3_clks 152 13>; /* VP 4 pixel clock */
0794 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
0795 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
0796 <&k3_clks 152 11>, /* PLL18_HSDIV0 */
0797 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
0798 };
0799
0800 &dss_ports {
0801 #address-cells = <1>;
0802 #size-cells = <0>;
0803
0804 port@0 {
0805 reg = <0>;
0806
0807 dpi0_out: endpoint {
0808 remote-endpoint = <&dp0_in>;
0809 };
0810 };
0811
0812 port@1 {
0813 reg = <1>;
0814
0815 dpi1_out: endpoint {
0816 remote-endpoint = <&tfp410_in>;
0817 };
0818 };
0819 };
0820
0821 &dp0_ports {
0822 #address-cells = <1>;
0823 #size-cells = <0>;
0824
0825 port@0 {
0826 reg = <0>;
0827 dp0_in: endpoint {
0828 remote-endpoint = <&dpi0_out>;
0829 };
0830 };
0831
0832 port@4 {
0833 reg = <4>;
0834 dp0_out: endpoint {
0835 remote-endpoint = <&dp_connector_in>;
0836 };
0837 };
0838 };
0839
0840 &mcasp0 {
0841 /* Unused */
0842 status = "disabled";
0843 };
0844
0845 &mcasp1 {
0846 /* Unused */
0847 status = "disabled";
0848 };
0849
0850 &mcasp2 {
0851 /* Unused */
0852 status = "disabled";
0853 };
0854
0855 &mcasp3 {
0856 /* Unused */
0857 status = "disabled";
0858 };
0859
0860 &mcasp4 {
0861 /* Unused */
0862 status = "disabled";
0863 };
0864
0865 &mcasp5 {
0866 /* Unused */
0867 status = "disabled";
0868 };
0869
0870 &mcasp6 {
0871 /* Brought out on RPi header */
0872 status = "disabled";
0873 };
0874
0875 &mcasp7 {
0876 /* Unused */
0877 status = "disabled";
0878 };
0879
0880 &mcasp8 {
0881 /* Unused */
0882 status = "disabled";
0883 };
0884
0885 &mcasp9 {
0886 /* Unused */
0887 status = "disabled";
0888 };
0889
0890 &mcasp10 {
0891 /* Unused */
0892 status = "disabled";
0893 };
0894
0895 &mcasp11 {
0896 /* Brought out on M.2 E Key */
0897 status = "disabled";
0898 };
0899
0900 &serdes0 {
0901 serdes0_pcie_link: phy@0 {
0902 reg = <0>;
0903 cdns,num-lanes = <1>;
0904 #phy-cells = <0>;
0905 cdns,phy-type = <PHY_TYPE_PCIE>;
0906 resets = <&serdes_wiz0 1>;
0907 };
0908 };
0909
0910 &serdes1 {
0911 serdes1_pcie_link: phy@0 {
0912 reg = <0>;
0913 cdns,num-lanes = <2>;
0914 #phy-cells = <0>;
0915 cdns,phy-type = <PHY_TYPE_PCIE>;
0916 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
0917 };
0918 };
0919
0920 &pcie0_rc {
0921 pinctrl-names = "default";
0922 pinctrl-0 = <&ekey_reset_pins_default>;
0923 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
0924
0925 phys = <&serdes0_pcie_link>;
0926 phy-names = "pcie-phy";
0927 num-lanes = <1>;
0928 };
0929
0930 &pcie1_rc {
0931 pinctrl-names = "default";
0932 pinctrl-0 = <&mkey_reset_pins_default>;
0933 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
0934
0935 phys = <&serdes1_pcie_link>;
0936 phy-names = "pcie-phy";
0937 num-lanes = <2>;
0938 };
0939
0940 &pcie2_rc {
0941 /* Unused */
0942 status = "disabled";
0943 };
0944
0945 &pcie0_ep {
0946 status = "disabled";
0947 phys = <&serdes0_pcie_link>;
0948 phy-names = "pcie-phy";
0949 num-lanes = <1>;
0950 };
0951
0952 &pcie1_ep {
0953 status = "disabled";
0954 phys = <&serdes1_pcie_link>;
0955 phy-names = "pcie-phy";
0956 num-lanes = <2>;
0957 };
0958
0959 &pcie2_ep {
0960 /* Unused */
0961 status = "disabled";
0962 };
0963
0964 &pcie3_rc {
0965 /* Unused */
0966 status = "disabled";
0967 };
0968
0969 &pcie3_ep {
0970 /* Unused */
0971 status = "disabled";
0972 };
0973
0974 &icssg0_mdio {
0975 status = "disabled";
0976 };
0977
0978 &icssg1_mdio {
0979 status = "disabled";
0980 };
0981
0982 &ufs_wrapper {
0983 status = "disabled";
0984 };
0985
0986 &mailbox0_cluster0 {
0987 interrupts = <436>;
0988
0989 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
0990 ti,mbox-rx = <0 0 0>;
0991 ti,mbox-tx = <1 0 0>;
0992 };
0993
0994 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
0995 ti,mbox-rx = <2 0 0>;
0996 ti,mbox-tx = <3 0 0>;
0997 };
0998 };
0999
1000 &mailbox0_cluster1 {
1001 interrupts = <432>;
1002
1003 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1004 ti,mbox-rx = <0 0 0>;
1005 ti,mbox-tx = <1 0 0>;
1006 };
1007
1008 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1009 ti,mbox-rx = <2 0 0>;
1010 ti,mbox-tx = <3 0 0>;
1011 };
1012 };
1013
1014 &mailbox0_cluster2 {
1015 interrupts = <428>;
1016
1017 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1018 ti,mbox-rx = <0 0 0>;
1019 ti,mbox-tx = <1 0 0>;
1020 };
1021
1022 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1023 ti,mbox-rx = <2 0 0>;
1024 ti,mbox-tx = <3 0 0>;
1025 };
1026 };
1027
1028 &mailbox0_cluster3 {
1029 interrupts = <424>;
1030
1031 mbox_c66_0: mbox-c66-0 {
1032 ti,mbox-rx = <0 0 0>;
1033 ti,mbox-tx = <1 0 0>;
1034 };
1035
1036 mbox_c66_1: mbox-c66-1 {
1037 ti,mbox-rx = <2 0 0>;
1038 ti,mbox-tx = <3 0 0>;
1039 };
1040 };
1041
1042 &mailbox0_cluster4 {
1043 interrupts = <420>;
1044
1045 mbox_c71_0: mbox-c71-0 {
1046 ti,mbox-rx = <0 0 0>;
1047 ti,mbox-tx = <1 0 0>;
1048 };
1049 };
1050
1051 &mailbox0_cluster5 {
1052 status = "disabled";
1053 };
1054
1055 &mailbox0_cluster6 {
1056 status = "disabled";
1057 };
1058
1059 &mailbox0_cluster7 {
1060 status = "disabled";
1061 };
1062
1063 &mailbox0_cluster8 {
1064 status = "disabled";
1065 };
1066
1067 &mailbox0_cluster9 {
1068 status = "disabled";
1069 };
1070
1071 &mailbox0_cluster10 {
1072 status = "disabled";
1073 };
1074
1075 &mailbox0_cluster11 {
1076 status = "disabled";
1077 };
1078
1079 &mcu_r5fss0_core0 {
1080 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
1081 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1082 <&mcu_r5fss0_core0_memory_region>;
1083 };
1084
1085 &mcu_r5fss0_core1 {
1086 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
1087 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1088 <&mcu_r5fss0_core1_memory_region>;
1089 };
1090
1091 &main_r5fss0_core0 {
1092 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
1093 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1094 <&main_r5fss0_core0_memory_region>;
1095 };
1096
1097 &main_r5fss0_core1 {
1098 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
1099 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1100 <&main_r5fss0_core1_memory_region>;
1101 };
1102
1103 &main_r5fss1_core0 {
1104 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
1105 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1106 <&main_r5fss1_core0_memory_region>;
1107 };
1108
1109 &main_r5fss1_core1 {
1110 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
1111 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1112 <&main_r5fss1_core1_memory_region>;
1113 };
1114
1115 &c66_0 {
1116 mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
1117 memory-region = <&c66_0_dma_memory_region>,
1118 <&c66_0_memory_region>;
1119 };
1120
1121 &c66_1 {
1122 mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
1123 memory-region = <&c66_1_dma_memory_region>,
1124 <&c66_1_memory_region>;
1125 };
1126
1127 &c71_0 {
1128 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
1129 memory-region = <&c71_0_dma_memory_region>,
1130 <&c71_0_memory_region>;
1131 };
