0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for J721E SoC Family Main Domain peripherals
0004 *
0005 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007 #include <dt-bindings/phy/phy.h>
0008 #include <dt-bindings/phy/phy-ti.h>
0009 #include <dt-bindings/mux/mux.h>
0010 #include <dt-bindings/mux/ti-serdes.h>
0011
0012 / {
0013 cmn_refclk: clock-cmnrefclk {
0014 #clock-cells = <0>;
0015 compatible = "fixed-clock";
0016 clock-frequency = <0>;
0017 };
0018
0019 cmn_refclk1: clock-cmnrefclk1 {
0020 #clock-cells = <0>;
0021 compatible = "fixed-clock";
0022 clock-frequency = <0>;
0023 };
0024 };
0025
0026 &cbass_main {
0027 msmc_ram: sram@70000000 {
0028 compatible = "mmio-sram";
0029 reg = <0x0 0x70000000 0x0 0x800000>;
0030 #address-cells = <1>;
0031 #size-cells = <1>;
0032 ranges = <0x0 0x0 0x70000000 0x800000>;
0033
0034 atf-sram@0 {
0035 reg = <0x0 0x20000>;
0036 };
0037 };
0038
0039 scm_conf: scm-conf@100000 {
0040 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
0041 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
0042 #address-cells = <1>;
0043 #size-cells = <1>;
0044 ranges = <0x0 0x0 0x00100000 0x1c000>;
0045
0046 serdes_ln_ctrl: mux-controller@4080 {
0047 compatible = "mmio-mux";
0048 reg = <0x00004080 0x50>;
0049 #mux-control-cells = <1>;
0050 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
0051 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
0052 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
0053 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
0054 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
0055 /* SERDES4 lane0/1/2/3 select */
0056 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
0057 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
0058 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
0059 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
0060 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
0061 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
0062 };
0063
0064 usb_serdes_mux: mux-controller@4000 {
0065 compatible = "mmio-mux";
0066 #mux-control-cells = <1>;
0067 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
0068 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
0069 };
0070 };
0071
0072 gic500: interrupt-controller@1800000 {
0073 compatible = "arm,gic-v3";
0074 #address-cells = <2>;
0075 #size-cells = <2>;
0076 ranges;
0077 #interrupt-cells = <3>;
0078 interrupt-controller;
0079 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
0080 <0x00 0x01900000 0x00 0x100000>, /* GICR */
0081 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
0082 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
0083 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
0084
0085 /* vcpumntirq: virtual CPU interface maintenance interrupt */
0086 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0087
0088 gic_its: msi-controller@1820000 {
0089 compatible = "arm,gic-v3-its";
0090 reg = <0x00 0x01820000 0x00 0x10000>;
0091 socionext,synquacer-pre-its = <0x1000000 0x400000>;
0092 msi-controller;
0093 #msi-cells = <1>;
0094 };
0095 };
0096
0097 main_gpio_intr: interrupt-controller@a00000 {
0098 compatible = "ti,sci-intr";
0099 reg = <0x00 0x00a00000 0x00 0x800>;
0100 ti,intr-trigger-type = <1>;
0101 interrupt-controller;
0102 interrupt-parent = <&gic500>;
0103 #interrupt-cells = <1>;
0104 ti,sci = <&dmsc>;
0105 ti,sci-dev-id = <131>;
0106 ti,interrupt-ranges = <8 392 56>;
0107 };
0108
0109 main_navss: bus@30000000 {
0110 compatible = "simple-mfd";
0111 #address-cells = <2>;
0112 #size-cells = <2>;
0113 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
0114 dma-coherent;
0115 dma-ranges;
0116
0117 ti,sci-dev-id = <199>;
0118
0119 main_navss_intr: interrupt-controller@310e0000 {
0120 compatible = "ti,sci-intr";
0121 reg = <0x0 0x310e0000 0x0 0x4000>;
0122 ti,intr-trigger-type = <4>;
0123 interrupt-controller;
0124 interrupt-parent = <&gic500>;
0125 #interrupt-cells = <1>;
0126 ti,sci = <&dmsc>;
0127 ti,sci-dev-id = <213>;
0128 ti,interrupt-ranges = <0 64 64>,
0129 <64 448 64>,
0130 <128 672 64>;
0131 };
0132
0133 main_udmass_inta: interrupt-controller@33d00000 {
0134 compatible = "ti,sci-inta";
0135 reg = <0x0 0x33d00000 0x0 0x100000>;
0136 interrupt-controller;
0137 interrupt-parent = <&main_navss_intr>;
0138 msi-controller;
0139 #interrupt-cells = <0>;
0140 ti,sci = <&dmsc>;
0141 ti,sci-dev-id = <209>;
0142 ti,interrupt-ranges = <0 0 256>;
0143 };
0144
0145 secure_proxy_main: mailbox@32c00000 {
0146 compatible = "ti,am654-secure-proxy";
0147 #mbox-cells = <1>;
0148 reg-names = "target_data", "rt", "scfg";
0149 reg = <0x00 0x32c00000 0x00 0x100000>,
0150 <0x00 0x32400000 0x00 0x100000>,
0151 <0x00 0x32800000 0x00 0x100000>;
0152 interrupt-names = "rx_011";
0153 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0154 };
0155
0156 smmu0: iommu@36600000 {
0157 compatible = "arm,smmu-v3";
0158 reg = <0x0 0x36600000 0x0 0x100000>;
0159 interrupt-parent = <&gic500>;
0160 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
0161 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
0162 interrupt-names = "eventq", "gerror";
0163 #iommu-cells = <1>;
0164 };
0165
0166 hwspinlock: spinlock@30e00000 {
0167 compatible = "ti,am654-hwspinlock";
0168 reg = <0x00 0x30e00000 0x00 0x1000>;
0169 #hwlock-cells = <1>;
0170 };
0171
0172 mailbox0_cluster0: mailbox@31f80000 {
0173 compatible = "ti,am654-mailbox";
0174 reg = <0x00 0x31f80000 0x00 0x200>;
0175 #mbox-cells = <1>;
0176 ti,mbox-num-users = <4>;
0177 ti,mbox-num-fifos = <16>;
0178 interrupt-parent = <&main_navss_intr>;
0179 };
0180
0181 mailbox0_cluster1: mailbox@31f81000 {
0182 compatible = "ti,am654-mailbox";
0183 reg = <0x00 0x31f81000 0x00 0x200>;
0184 #mbox-cells = <1>;
0185 ti,mbox-num-users = <4>;
0186 ti,mbox-num-fifos = <16>;
0187 interrupt-parent = <&main_navss_intr>;
0188 };
0189
0190 mailbox0_cluster2: mailbox@31f82000 {
0191 compatible = "ti,am654-mailbox";
0192 reg = <0x00 0x31f82000 0x00 0x200>;
0193 #mbox-cells = <1>;
0194 ti,mbox-num-users = <4>;
0195 ti,mbox-num-fifos = <16>;
0196 interrupt-parent = <&main_navss_intr>;
0197 };
0198
0199 mailbox0_cluster3: mailbox@31f83000 {
0200 compatible = "ti,am654-mailbox";
0201 reg = <0x00 0x31f83000 0x00 0x200>;
0202 #mbox-cells = <1>;
0203 ti,mbox-num-users = <4>;
0204 ti,mbox-num-fifos = <16>;
0205 interrupt-parent = <&main_navss_intr>;
0206 };
0207
0208 mailbox0_cluster4: mailbox@31f84000 {
0209 compatible = "ti,am654-mailbox";
0210 reg = <0x00 0x31f84000 0x00 0x200>;
0211 #mbox-cells = <1>;
0212 ti,mbox-num-users = <4>;
0213 ti,mbox-num-fifos = <16>;
0214 interrupt-parent = <&main_navss_intr>;
0215 };
0216
0217 mailbox0_cluster5: mailbox@31f85000 {
0218 compatible = "ti,am654-mailbox";
0219 reg = <0x00 0x31f85000 0x00 0x200>;
0220 #mbox-cells = <1>;
0221 ti,mbox-num-users = <4>;
0222 ti,mbox-num-fifos = <16>;
0223 interrupt-parent = <&main_navss_intr>;
0224 };
0225
0226 mailbox0_cluster6: mailbox@31f86000 {
0227 compatible = "ti,am654-mailbox";
0228 reg = <0x00 0x31f86000 0x00 0x200>;
0229 #mbox-cells = <1>;
0230 ti,mbox-num-users = <4>;
0231 ti,mbox-num-fifos = <16>;
0232 interrupt-parent = <&main_navss_intr>;
0233 };
0234
0235 mailbox0_cluster7: mailbox@31f87000 {
0236 compatible = "ti,am654-mailbox";
0237 reg = <0x00 0x31f87000 0x00 0x200>;
0238 #mbox-cells = <1>;
0239 ti,mbox-num-users = <4>;
0240 ti,mbox-num-fifos = <16>;
0241 interrupt-parent = <&main_navss_intr>;
0242 };
0243
0244 mailbox0_cluster8: mailbox@31f88000 {
0245 compatible = "ti,am654-mailbox";
0246 reg = <0x00 0x31f88000 0x00 0x200>;
0247 #mbox-cells = <1>;
0248 ti,mbox-num-users = <4>;
0249 ti,mbox-num-fifos = <16>;
0250 interrupt-parent = <&main_navss_intr>;
0251 };
0252
0253 mailbox0_cluster9: mailbox@31f89000 {
0254 compatible = "ti,am654-mailbox";
0255 reg = <0x00 0x31f89000 0x00 0x200>;
0256 #mbox-cells = <1>;
0257 ti,mbox-num-users = <4>;
0258 ti,mbox-num-fifos = <16>;
0259 interrupt-parent = <&main_navss_intr>;
0260 };
0261
0262 mailbox0_cluster10: mailbox@31f8a000 {
0263 compatible = "ti,am654-mailbox";
0264 reg = <0x00 0x31f8a000 0x00 0x200>;
0265 #mbox-cells = <1>;
0266 ti,mbox-num-users = <4>;
0267 ti,mbox-num-fifos = <16>;
0268 interrupt-parent = <&main_navss_intr>;
0269 };
0270
0271 mailbox0_cluster11: mailbox@31f8b000 {
0272 compatible = "ti,am654-mailbox";
0273 reg = <0x00 0x31f8b000 0x00 0x200>;
0274 #mbox-cells = <1>;
0275 ti,mbox-num-users = <4>;
0276 ti,mbox-num-fifos = <16>;
0277 interrupt-parent = <&main_navss_intr>;
0278 };
0279
0280 main_ringacc: ringacc@3c000000 {
0281 compatible = "ti,am654-navss-ringacc";
0282 reg = <0x0 0x3c000000 0x0 0x400000>,
0283 <0x0 0x38000000 0x0 0x400000>,
0284 <0x0 0x31120000 0x0 0x100>,
0285 <0x0 0x33000000 0x0 0x40000>;
0286 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
0287 ti,num-rings = <1024>;
0288 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
0289 ti,sci = <&dmsc>;
0290 ti,sci-dev-id = <211>;
0291 msi-parent = <&main_udmass_inta>;
0292 };
0293
0294 main_udmap: dma-controller@31150000 {
0295 compatible = "ti,j721e-navss-main-udmap";
0296 reg = <0x0 0x31150000 0x0 0x100>,
0297 <0x0 0x34000000 0x0 0x100000>,
0298 <0x0 0x35000000 0x0 0x100000>;
0299 reg-names = "gcfg", "rchanrt", "tchanrt";
0300 msi-parent = <&main_udmass_inta>;
0301 #dma-cells = <1>;
0302
0303 ti,sci = <&dmsc>;
0304 ti,sci-dev-id = <212>;
0305 ti,ringacc = <&main_ringacc>;
0306
0307 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
0308 <0x0f>, /* TX_HCHAN */
0309 <0x10>; /* TX_UHCHAN */
0310 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
0311 <0x0b>, /* RX_HCHAN */
0312 <0x0c>; /* RX_UHCHAN */
0313 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
0314 };
0315
0316 cpts@310d0000 {
0317 compatible = "ti,j721e-cpts";
0318 reg = <0x0 0x310d0000 0x0 0x400>;
0319 reg-names = "cpts";
0320 clocks = <&k3_clks 201 1>;
0321 clock-names = "cpts";
0322 interrupts-extended = <&main_navss_intr 391>;
0323 interrupt-names = "cpts";
0324 ti,cpts-periodic-outputs = <6>;
0325 ti,cpts-ext-ts-inputs = <8>;
0326 };
0327 };
0328
0329 main_crypto: crypto@4e00000 {
0330 compatible = "ti,j721e-sa2ul";
0331 reg = <0x0 0x4e00000 0x0 0x1200>;
0332 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
0333 #address-cells = <2>;
0334 #size-cells = <2>;
0335 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
0336
0337 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
0338 <&main_udmap 0x4001>;
0339 dma-names = "tx", "rx1", "rx2";
0340 dma-coherent;
0341
0342 rng: rng@4e10000 {
0343 compatible = "inside-secure,safexcel-eip76";
0344 reg = <0x0 0x4e10000 0x0 0x7d>;
0345 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0346 clocks = <&k3_clks 264 1>;
0347 };
0348 };
0349
0350 main_pmx0: pinctrl@11c000 {
0351 compatible = "pinctrl-single";
0352 /* Proxy 0 addressing */
0353 reg = <0x0 0x11c000 0x0 0x2b4>;
0354 #pinctrl-cells = <1>;
0355 pinctrl-single,register-width = <32>;
0356 pinctrl-single,function-mask = <0xffffffff>;
0357 };
0358
0359 serdes_wiz0: wiz@5000000 {
0360 compatible = "ti,j721e-wiz-16g";
0361 #address-cells = <1>;
0362 #size-cells = <1>;
0363 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
0364 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
0365 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0366 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
0367 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
0368 num-lanes = <2>;
0369 #reset-cells = <1>;
0370 ranges = <0x5000000 0x0 0x5000000 0x10000>;
0371
0372 wiz0_pll0_refclk: pll0-refclk {
0373 clocks = <&k3_clks 292 11>, <&cmn_refclk>;
0374 #clock-cells = <0>;
0375 assigned-clocks = <&wiz0_pll0_refclk>;
0376 assigned-clock-parents = <&k3_clks 292 11>;
0377 };
0378
0379 wiz0_pll1_refclk: pll1-refclk {
0380 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
0381 #clock-cells = <0>;
0382 assigned-clocks = <&wiz0_pll1_refclk>;
0383 assigned-clock-parents = <&k3_clks 292 0>;
0384 };
0385
0386 wiz0_refclk_dig: refclk-dig {
0387 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
0388 #clock-cells = <0>;
0389 assigned-clocks = <&wiz0_refclk_dig>;
0390 assigned-clock-parents = <&k3_clks 292 11>;
0391 };
0392
0393 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
0394 clocks = <&wiz0_refclk_dig>;
0395 #clock-cells = <0>;
0396 };
0397
0398 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
0399 clocks = <&wiz0_pll1_refclk>;
0400 #clock-cells = <0>;
0401 };
0402
0403 serdes0: serdes@5000000 {
0404 compatible = "ti,sierra-phy-t0";
0405 reg-names = "serdes";
0406 reg = <0x5000000 0x10000>;
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 #clock-cells = <1>;
0410 resets = <&serdes_wiz0 0>;
0411 reset-names = "sierra_reset";
0412 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
0413 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
0414 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
0415 "pll0_refclk", "pll1_refclk";
0416 };
0417 };
0418
0419 serdes_wiz1: wiz@5010000 {
0420 compatible = "ti,j721e-wiz-16g";
0421 #address-cells = <1>;
0422 #size-cells = <1>;
0423 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
0424 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
0425 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0426 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
0427 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
0428 num-lanes = <2>;
0429 #reset-cells = <1>;
0430 ranges = <0x5010000 0x0 0x5010000 0x10000>;
0431
0432 wiz1_pll0_refclk: pll0-refclk {
0433 clocks = <&k3_clks 293 13>, <&cmn_refclk>;
0434 #clock-cells = <0>;
0435 assigned-clocks = <&wiz1_pll0_refclk>;
0436 assigned-clock-parents = <&k3_clks 293 13>;
0437 };
0438
0439 wiz1_pll1_refclk: pll1-refclk {
0440 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
0441 #clock-cells = <0>;
0442 assigned-clocks = <&wiz1_pll1_refclk>;
0443 assigned-clock-parents = <&k3_clks 293 0>;
0444 };
0445
0446 wiz1_refclk_dig: refclk-dig {
0447 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
0448 #clock-cells = <0>;
0449 assigned-clocks = <&wiz1_refclk_dig>;
0450 assigned-clock-parents = <&k3_clks 293 13>;
0451 };
0452
0453 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
0454 clocks = <&wiz1_refclk_dig>;
0455 #clock-cells = <0>;
0456 };
0457
0458 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
0459 clocks = <&wiz1_pll1_refclk>;
0460 #clock-cells = <0>;
0461 };
0462
0463 serdes1: serdes@5010000 {
0464 compatible = "ti,sierra-phy-t0";
0465 reg-names = "serdes";
0466 reg = <0x5010000 0x10000>;
0467 #address-cells = <1>;
0468 #size-cells = <0>;
0469 #clock-cells = <1>;
0470 resets = <&serdes_wiz1 0>;
0471 reset-names = "sierra_reset";
0472 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
0473 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
0474 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
0475 "pll0_refclk", "pll1_refclk";
0476 };
0477 };
0478
0479 serdes_wiz2: wiz@5020000 {
0480 compatible = "ti,j721e-wiz-16g";
0481 #address-cells = <1>;
0482 #size-cells = <1>;
0483 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
0484 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
0485 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0486 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
0487 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
0488 num-lanes = <2>;
0489 #reset-cells = <1>;
0490 ranges = <0x5020000 0x0 0x5020000 0x10000>;
0491
0492 wiz2_pll0_refclk: pll0-refclk {
0493 clocks = <&k3_clks 294 11>, <&cmn_refclk>;
0494 #clock-cells = <0>;
0495 assigned-clocks = <&wiz2_pll0_refclk>;
0496 assigned-clock-parents = <&k3_clks 294 11>;
0497 };
0498
0499 wiz2_pll1_refclk: pll1-refclk {
0500 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
0501 #clock-cells = <0>;
0502 assigned-clocks = <&wiz2_pll1_refclk>;
0503 assigned-clock-parents = <&k3_clks 294 0>;
0504 };
0505
0506 wiz2_refclk_dig: refclk-dig {
0507 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
0508 #clock-cells = <0>;
0509 assigned-clocks = <&wiz2_refclk_dig>;
0510 assigned-clock-parents = <&k3_clks 294 11>;
0511 };
0512
0513 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
0514 clocks = <&wiz2_refclk_dig>;
0515 #clock-cells = <0>;
0516 };
0517
0518 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
0519 clocks = <&wiz2_pll1_refclk>;
0520 #clock-cells = <0>;
0521 };
0522
0523 serdes2: serdes@5020000 {
0524 compatible = "ti,sierra-phy-t0";
0525 reg-names = "serdes";
0526 reg = <0x5020000 0x10000>;
0527 #address-cells = <1>;
0528 #size-cells = <0>;
0529 #clock-cells = <1>;
0530 resets = <&serdes_wiz2 0>;
0531 reset-names = "sierra_reset";
0532 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
0533 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
0534 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
0535 "pll0_refclk", "pll1_refclk";
0536 };
0537 };
0538
0539 serdes_wiz3: wiz@5030000 {
0540 compatible = "ti,j721e-wiz-16g";
0541 #address-cells = <1>;
0542 #size-cells = <1>;
0543 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
0544 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
0545 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0546 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
0547 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
0548 num-lanes = <2>;
0549 #reset-cells = <1>;
0550 ranges = <0x5030000 0x0 0x5030000 0x10000>;
0551
0552 wiz3_pll0_refclk: pll0-refclk {
0553 clocks = <&k3_clks 295 9>, <&cmn_refclk>;
0554 #clock-cells = <0>;
0555 assigned-clocks = <&wiz3_pll0_refclk>;
0556 assigned-clock-parents = <&k3_clks 295 9>;
0557 };
0558
0559 wiz3_pll1_refclk: pll1-refclk {
0560 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
0561 #clock-cells = <0>;
0562 assigned-clocks = <&wiz3_pll1_refclk>;
0563 assigned-clock-parents = <&k3_clks 295 0>;
0564 };
0565
0566 wiz3_refclk_dig: refclk-dig {
0567 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
0568 #clock-cells = <0>;
0569 assigned-clocks = <&wiz3_refclk_dig>;
0570 assigned-clock-parents = <&k3_clks 295 9>;
0571 };
0572
0573 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
0574 clocks = <&wiz3_refclk_dig>;
0575 #clock-cells = <0>;
0576 };
0577
0578 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
0579 clocks = <&wiz3_pll1_refclk>;
0580 #clock-cells = <0>;
0581 };
0582
0583 serdes3: serdes@5030000 {
0584 compatible = "ti,sierra-phy-t0";
0585 reg-names = "serdes";
0586 reg = <0x5030000 0x10000>;
0587 #address-cells = <1>;
0588 #size-cells = <0>;
0589 #clock-cells = <1>;
0590 resets = <&serdes_wiz3 0>;
0591 reset-names = "sierra_reset";
0592 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
0593 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
0594 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
0595 "pll0_refclk", "pll1_refclk";
0596 };
0597 };
0598
0599 pcie0_rc: pcie@2900000 {
0600 compatible = "ti,j721e-pcie-host";
0601 reg = <0x00 0x02900000 0x00 0x1000>,
0602 <0x00 0x02907000 0x00 0x400>,
0603 <0x00 0x0d000000 0x00 0x00800000>,
0604 <0x00 0x10000000 0x00 0x00001000>;
0605 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0606 interrupt-names = "link_state";
0607 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
0608 device_type = "pci";
0609 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
0610 max-link-speed = <3>;
0611 num-lanes = <2>;
0612 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
0613 clocks = <&k3_clks 239 1>;
0614 clock-names = "fck";
0615 #address-cells = <3>;
0616 #size-cells = <2>;
0617 bus-range = <0x0 0xff>;
0618 vendor-id = <0x104c>;
0619 device-id = <0xb00d>;
0620 msi-map = <0x0 &gic_its 0x0 0x10000>;
0621 dma-coherent;
0622 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
0623 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
0624 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0625 };
0626
0627 pcie0_ep: pcie-ep@2900000 {
0628 compatible = "ti,j721e-pcie-ep";
0629 reg = <0x00 0x02900000 0x00 0x1000>,
0630 <0x00 0x02907000 0x00 0x400>,
0631 <0x00 0x0d000000 0x00 0x00800000>,
0632 <0x00 0x10000000 0x00 0x08000000>;
0633 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0634 interrupt-names = "link_state";
0635 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
0636 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
0637 max-link-speed = <3>;
0638 num-lanes = <2>;
0639 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
0640 clocks = <&k3_clks 239 1>;
0641 clock-names = "fck";
0642 max-functions = /bits/ 8 <6>;
0643 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
0644 dma-coherent;
0645 };
0646
0647 pcie1_rc: pcie@2910000 {
0648 compatible = "ti,j721e-pcie-host";
0649 reg = <0x00 0x02910000 0x00 0x1000>,
0650 <0x00 0x02917000 0x00 0x400>,
0651 <0x00 0x0d800000 0x00 0x00800000>,
0652 <0x00 0x18000000 0x00 0x00001000>;
0653 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0654 interrupt-names = "link_state";
0655 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
0656 device_type = "pci";
0657 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
0658 max-link-speed = <3>;
0659 num-lanes = <2>;
0660 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
0661 clocks = <&k3_clks 240 1>;
0662 clock-names = "fck";
0663 #address-cells = <3>;
0664 #size-cells = <2>;
0665 bus-range = <0x0 0xff>;
0666 vendor-id = <0x104c>;
0667 device-id = <0xb00d>;
0668 msi-map = <0x0 &gic_its 0x10000 0x10000>;
0669 dma-coherent;
0670 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
0671 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
0672 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0673 };
0674
0675 pcie1_ep: pcie-ep@2910000 {
0676 compatible = "ti,j721e-pcie-ep";
0677 reg = <0x00 0x02910000 0x00 0x1000>,
0678 <0x00 0x02917000 0x00 0x400>,
0679 <0x00 0x0d800000 0x00 0x00800000>,
0680 <0x00 0x18000000 0x00 0x08000000>;
0681 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0682 interrupt-names = "link_state";
0683 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
0684 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
0685 max-link-speed = <3>;
0686 num-lanes = <2>;
0687 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
0688 clocks = <&k3_clks 240 1>;
0689 clock-names = "fck";
0690 max-functions = /bits/ 8 <6>;
0691 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
0692 dma-coherent;
0693 };
0694
0695 pcie2_rc: pcie@2920000 {
0696 compatible = "ti,j721e-pcie-host";
0697 reg = <0x00 0x02920000 0x00 0x1000>,
0698 <0x00 0x02927000 0x00 0x400>,
0699 <0x00 0x0e000000 0x00 0x00800000>,
0700 <0x44 0x00000000 0x00 0x00001000>;
0701 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0702 interrupt-names = "link_state";
0703 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
0704 device_type = "pci";
0705 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
0706 max-link-speed = <3>;
0707 num-lanes = <2>;
0708 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
0709 clocks = <&k3_clks 241 1>;
0710 clock-names = "fck";
0711 #address-cells = <3>;
0712 #size-cells = <2>;
0713 bus-range = <0x0 0xff>;
0714 vendor-id = <0x104c>;
0715 device-id = <0xb00d>;
0716 msi-map = <0x0 &gic_its 0x20000 0x10000>;
0717 dma-coherent;
0718 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
0719 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
0720 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0721 };
0722
0723 pcie2_ep: pcie-ep@2920000 {
0724 compatible = "ti,j721e-pcie-ep";
0725 reg = <0x00 0x02920000 0x00 0x1000>,
0726 <0x00 0x02927000 0x00 0x400>,
0727 <0x00 0x0e000000 0x00 0x00800000>,
0728 <0x44 0x00000000 0x00 0x08000000>;
0729 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0730 interrupt-names = "link_state";
0731 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
0732 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
0733 max-link-speed = <3>;
0734 num-lanes = <2>;
0735 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
0736 clocks = <&k3_clks 241 1>;
0737 clock-names = "fck";
0738 max-functions = /bits/ 8 <6>;
0739 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
0740 dma-coherent;
0741 };
0742
0743 pcie3_rc: pcie@2930000 {
0744 compatible = "ti,j721e-pcie-host";
0745 reg = <0x00 0x02930000 0x00 0x1000>,
0746 <0x00 0x02937000 0x00 0x400>,
0747 <0x00 0x0e800000 0x00 0x00800000>,
0748 <0x44 0x10000000 0x00 0x00001000>;
0749 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0750 interrupt-names = "link_state";
0751 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
0752 device_type = "pci";
0753 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
0754 max-link-speed = <3>;
0755 num-lanes = <2>;
0756 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
0757 clocks = <&k3_clks 242 1>;
0758 clock-names = "fck";
0759 #address-cells = <3>;
0760 #size-cells = <2>;
0761 bus-range = <0x0 0xff>;
0762 vendor-id = <0x104c>;
0763 device-id = <0xb00d>;
0764 msi-map = <0x0 &gic_its 0x30000 0x10000>;
0765 dma-coherent;
0766 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
0767 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
0768 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0769 };
0770
0771 pcie3_ep: pcie-ep@2930000 {
0772 compatible = "ti,j721e-pcie-ep";
0773 reg = <0x00 0x02930000 0x00 0x1000>,
0774 <0x00 0x02937000 0x00 0x400>,
0775 <0x00 0x0e800000 0x00 0x00800000>,
0776 <0x44 0x10000000 0x00 0x08000000>;
0777 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0778 interrupt-names = "link_state";
0779 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
0780 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
0781 max-link-speed = <3>;
0782 num-lanes = <2>;
0783 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
0784 clocks = <&k3_clks 242 1>;
0785 clock-names = "fck";
0786 max-functions = /bits/ 8 <6>;
0787 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
0788 dma-coherent;
0789 #address-cells = <2>;
0790 #size-cells = <2>;
0791 };
0792
0793 serdes_wiz4: wiz@5050000 {
0794 compatible = "ti,am64-wiz-10g";
0795 #address-cells = <1>;
0796 #size-cells = <1>;
0797 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
0798 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
0799 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0800 assigned-clocks = <&k3_clks 297 9>;
0801 assigned-clock-parents = <&k3_clks 297 10>;
0802 assigned-clock-rates = <19200000>;
0803 num-lanes = <4>;
0804 #reset-cells = <1>;
0805 #clock-cells = <1>;
0806 ranges = <0x05050000 0x00 0x05050000 0x010000>,
0807 <0x0a030a00 0x00 0x0a030a00 0x40>;
0808
0809 serdes4: serdes@5050000 {
0810 /*
0811 * Note: we also map DPTX PHY registers as the Torrent
0812 * needs to manage those.
0813 */
0814 compatible = "ti,j721e-serdes-10g";
0815 reg = <0x05050000 0x010000>,
0816 <0x0a030a00 0x40>; /* DPTX PHY */
0817 reg-names = "torrent_phy", "dptx_phy";
0818
0819 resets = <&serdes_wiz4 0>;
0820 reset-names = "torrent_reset";
0821 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
0822 clock-names = "refclk";
0823 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
0824 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
0825 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
0826 assigned-clock-parents = <&k3_clks 297 9>,
0827 <&k3_clks 297 9>,
0828 <&k3_clks 297 9>;
0829 #address-cells = <1>;
0830 #size-cells = <0>;
0831 };
0832 };
0833
0834 main_uart0: serial@2800000 {
0835 compatible = "ti,j721e-uart", "ti,am654-uart";
0836 reg = <0x00 0x02800000 0x00 0x100>;
0837 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
0838 clock-frequency = <48000000>;
0839 current-speed = <115200>;
0840 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
0841 clocks = <&k3_clks 146 0>;
0842 clock-names = "fclk";
0843 };
0844
0845 main_uart1: serial@2810000 {
0846 compatible = "ti,j721e-uart", "ti,am654-uart";
0847 reg = <0x00 0x02810000 0x00 0x100>;
0848 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0849 clock-frequency = <48000000>;
0850 current-speed = <115200>;
0851 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
0852 clocks = <&k3_clks 278 0>;
0853 clock-names = "fclk";
0854 };
0855
0856 main_uart2: serial@2820000 {
0857 compatible = "ti,j721e-uart", "ti,am654-uart";
0858 reg = <0x00 0x02820000 0x00 0x100>;
0859 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0860 clock-frequency = <48000000>;
0861 current-speed = <115200>;
0862 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
0863 clocks = <&k3_clks 279 0>;
0864 clock-names = "fclk";
0865 };
0866
0867 main_uart3: serial@2830000 {
0868 compatible = "ti,j721e-uart", "ti,am654-uart";
0869 reg = <0x00 0x02830000 0x00 0x100>;
0870 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0871 clock-frequency = <48000000>;
0872 current-speed = <115200>;
0873 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
0874 clocks = <&k3_clks 280 0>;
0875 clock-names = "fclk";
0876 };
0877
0878 main_uart4: serial@2840000 {
0879 compatible = "ti,j721e-uart", "ti,am654-uart";
0880 reg = <0x00 0x02840000 0x00 0x100>;
0881 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0882 clock-frequency = <48000000>;
0883 current-speed = <115200>;
0884 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
0885 clocks = <&k3_clks 281 0>;
0886 clock-names = "fclk";
0887 };
0888
0889 main_uart5: serial@2850000 {
0890 compatible = "ti,j721e-uart", "ti,am654-uart";
0891 reg = <0x00 0x02850000 0x00 0x100>;
0892 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0893 clock-frequency = <48000000>;
0894 current-speed = <115200>;
0895 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
0896 clocks = <&k3_clks 282 0>;
0897 clock-names = "fclk";
0898 };
0899
0900 main_uart6: serial@2860000 {
0901 compatible = "ti,j721e-uart", "ti,am654-uart";
0902 reg = <0x00 0x02860000 0x00 0x100>;
0903 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
0904 clock-frequency = <48000000>;
0905 current-speed = <115200>;
0906 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
0907 clocks = <&k3_clks 283 0>;
0908 clock-names = "fclk";
0909 };
0910
0911 main_uart7: serial@2870000 {
0912 compatible = "ti,j721e-uart", "ti,am654-uart";
0913 reg = <0x00 0x02870000 0x00 0x100>;
0914 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
0915 clock-frequency = <48000000>;
0916 current-speed = <115200>;
0917 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
0918 clocks = <&k3_clks 284 0>;
0919 clock-names = "fclk";
0920 };
0921
0922 main_uart8: serial@2880000 {
0923 compatible = "ti,j721e-uart", "ti,am654-uart";
0924 reg = <0x00 0x02880000 0x00 0x100>;
0925 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
0926 clock-frequency = <48000000>;
0927 current-speed = <115200>;
0928 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
0929 clocks = <&k3_clks 285 0>;
0930 clock-names = "fclk";
0931 };
0932
0933 main_uart9: serial@2890000 {
0934 compatible = "ti,j721e-uart", "ti,am654-uart";
0935 reg = <0x00 0x02890000 0x00 0x100>;
0936 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0937 clock-frequency = <48000000>;
0938 current-speed = <115200>;
0939 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
0940 clocks = <&k3_clks 286 0>;
0941 clock-names = "fclk";
0942 };
0943
0944 main_gpio0: gpio@600000 {
0945 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0946 reg = <0x0 0x00600000 0x0 0x100>;
0947 gpio-controller;
0948 #gpio-cells = <2>;
0949 interrupt-parent = <&main_gpio_intr>;
0950 interrupts = <256>, <257>, <258>, <259>,
0951 <260>, <261>, <262>, <263>;
0952 interrupt-controller;
0953 #interrupt-cells = <2>;
0954 ti,ngpio = <128>;
0955 ti,davinci-gpio-unbanked = <0>;
0956 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
0957 clocks = <&k3_clks 105 0>;
0958 clock-names = "gpio";
0959 };
0960
0961 main_gpio1: gpio@601000 {
0962 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0963 reg = <0x0 0x00601000 0x0 0x100>;
0964 gpio-controller;
0965 #gpio-cells = <2>;
0966 interrupt-parent = <&main_gpio_intr>;
0967 interrupts = <288>, <289>, <290>;
0968 interrupt-controller;
0969 #interrupt-cells = <2>;
0970 ti,ngpio = <36>;
0971 ti,davinci-gpio-unbanked = <0>;
0972 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
0973 clocks = <&k3_clks 106 0>;
0974 clock-names = "gpio";
0975 };
0976
0977 main_gpio2: gpio@610000 {
0978 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0979 reg = <0x0 0x00610000 0x0 0x100>;
0980 gpio-controller;
0981 #gpio-cells = <2>;
0982 interrupt-parent = <&main_gpio_intr>;
0983 interrupts = <264>, <265>, <266>, <267>,
0984 <268>, <269>, <270>, <271>;
0985 interrupt-controller;
0986 #interrupt-cells = <2>;
0987 ti,ngpio = <128>;
0988 ti,davinci-gpio-unbanked = <0>;
0989 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
0990 clocks = <&k3_clks 107 0>;
0991 clock-names = "gpio";
0992 };
0993
0994 main_gpio3: gpio@611000 {
0995 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
0996 reg = <0x0 0x00611000 0x0 0x100>;
0997 gpio-controller;
0998 #gpio-cells = <2>;
0999 interrupt-parent = <&main_gpio_intr>;
1000 interrupts = <292>, <293>, <294>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1003 ti,ngpio = <36>;
1004 ti,davinci-gpio-unbanked = <0>;
1005 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1006 clocks = <&k3_clks 108 0>;
1007 clock-names = "gpio";
1008 };
1009
1010 main_gpio4: gpio@620000 {
1011 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1012 reg = <0x0 0x00620000 0x0 0x100>;
1013 gpio-controller;
1014 #gpio-cells = <2>;
1015 interrupt-parent = <&main_gpio_intr>;
1016 interrupts = <272>, <273>, <274>, <275>,
1017 <276>, <277>, <278>, <279>;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1020 ti,ngpio = <128>;
1021 ti,davinci-gpio-unbanked = <0>;
1022 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1023 clocks = <&k3_clks 109 0>;
1024 clock-names = "gpio";
1025 };
1026
1027 main_gpio5: gpio@621000 {
1028 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1029 reg = <0x0 0x00621000 0x0 0x100>;
1030 gpio-controller;
1031 #gpio-cells = <2>;
1032 interrupt-parent = <&main_gpio_intr>;
1033 interrupts = <296>, <297>, <298>;
1034 interrupt-controller;
1035 #interrupt-cells = <2>;
1036 ti,ngpio = <36>;
1037 ti,davinci-gpio-unbanked = <0>;
1038 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1039 clocks = <&k3_clks 110 0>;
1040 clock-names = "gpio";
1041 };
1042
1043 main_gpio6: gpio@630000 {
1044 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1045 reg = <0x0 0x00630000 0x0 0x100>;
1046 gpio-controller;
1047 #gpio-cells = <2>;
1048 interrupt-parent = <&main_gpio_intr>;
1049 interrupts = <280>, <281>, <282>, <283>,
1050 <284>, <285>, <286>, <287>;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1053 ti,ngpio = <128>;
1054 ti,davinci-gpio-unbanked = <0>;
1055 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1056 clocks = <&k3_clks 111 0>;
1057 clock-names = "gpio";
1058 };
1059
1060 main_gpio7: gpio@631000 {
1061 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1062 reg = <0x0 0x00631000 0x0 0x100>;
1063 gpio-controller;
1064 #gpio-cells = <2>;
1065 interrupt-parent = <&main_gpio_intr>;
1066 interrupts = <300>, <301>, <302>;
1067 interrupt-controller;
1068 #interrupt-cells = <2>;
1069 ti,ngpio = <36>;
1070 ti,davinci-gpio-unbanked = <0>;
1071 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1072 clocks = <&k3_clks 112 0>;
1073 clock-names = "gpio";
1074 };
1075
1076 main_sdhci0: mmc@4f80000 {
1077 compatible = "ti,j721e-sdhci-8bit";
1078 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1079 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1080 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1081 clock-names = "clk_ahb", "clk_xin";
1082 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1083 assigned-clocks = <&k3_clks 91 1>;
1084 assigned-clock-parents = <&k3_clks 91 2>;
1085 bus-width = <8>;
1086 mmc-hs200-1_8v;
1087 mmc-ddr-1_8v;
1088 ti,otap-del-sel-legacy = <0xf>;
1089 ti,otap-del-sel-mmc-hs = <0xf>;
1090 ti,otap-del-sel-ddr52 = <0x5>;
1091 ti,otap-del-sel-hs200 = <0x6>;
1092 ti,otap-del-sel-hs400 = <0x0>;
1093 ti,itap-del-sel-legacy = <0x10>;
1094 ti,itap-del-sel-mmc-hs = <0xa>;
1095 ti,itap-del-sel-ddr52 = <0x3>;
1096 ti,trm-icp = <0x8>;
1097 ti,strobe-sel = <0x77>;
1098 dma-coherent;
1099 };
1100
1101 main_sdhci1: mmc@4fb0000 {
1102 compatible = "ti,j721e-sdhci-4bit";
1103 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1104 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1105 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1106 clock-names = "clk_ahb", "clk_xin";
1107 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1108 assigned-clocks = <&k3_clks 92 0>;
1109 assigned-clock-parents = <&k3_clks 92 1>;
1110 ti,otap-del-sel-legacy = <0x0>;
1111 ti,otap-del-sel-sd-hs = <0xf>;
1112 ti,otap-del-sel-sdr12 = <0xf>;
1113 ti,otap-del-sel-sdr25 = <0xf>;
1114 ti,otap-del-sel-sdr50 = <0xc>;
1115 ti,otap-del-sel-ddr50 = <0xc>;
1116 ti,itap-del-sel-legacy = <0x0>;
1117 ti,itap-del-sel-sd-hs = <0x0>;
1118 ti,itap-del-sel-sdr12 = <0x0>;
1119 ti,itap-del-sel-sdr25 = <0x0>;
1120 ti,itap-del-sel-ddr50 = <0x2>;
1121 ti,trm-icp = <0x8>;
1122 ti,clkbuf-sel = <0x7>;
1123 dma-coherent;
1124 sdhci-caps-mask = <0x2 0x0>;
1125 };
1126
1127 main_sdhci2: mmc@4f98000 {
1128 compatible = "ti,j721e-sdhci-4bit";
1129 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1130 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1131 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1132 clock-names = "clk_ahb", "clk_xin";
1133 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1134 assigned-clocks = <&k3_clks 93 0>;
1135 assigned-clock-parents = <&k3_clks 93 1>;
1136 ti,otap-del-sel-legacy = <0x0>;
1137 ti,otap-del-sel-sd-hs = <0xf>;
1138 ti,otap-del-sel-sdr12 = <0xf>;
1139 ti,otap-del-sel-sdr25 = <0xf>;
1140 ti,otap-del-sel-sdr50 = <0xc>;
1141 ti,otap-del-sel-ddr50 = <0xc>;
1142 ti,itap-del-sel-legacy = <0x0>;
1143 ti,itap-del-sel-sd-hs = <0x0>;
1144 ti,itap-del-sel-sdr12 = <0x0>;
1145 ti,itap-del-sel-sdr25 = <0x0>;
1146 ti,itap-del-sel-ddr50 = <0x2>;
1147 ti,trm-icp = <0x8>;
1148 ti,clkbuf-sel = <0x7>;
1149 dma-coherent;
1150 sdhci-caps-mask = <0x2 0x0>;
1151 };
1152
1153 usbss0: cdns-usb@4104000 {
1154 compatible = "ti,j721e-usb";
1155 reg = <0x00 0x4104000 0x00 0x100>;
1156 dma-coherent;
1157 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1158 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1159 clock-names = "ref", "lpm";
1160 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1161 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1162 #address-cells = <2>;
1163 #size-cells = <2>;
1164 ranges;
1165
1166 usb0: usb@6000000 {
1167 compatible = "cdns,usb3";
1168 reg = <0x00 0x6000000 0x00 0x10000>,
1169 <0x00 0x6010000 0x00 0x10000>,
1170 <0x00 0x6020000 0x00 0x10000>;
1171 reg-names = "otg", "xhci", "dev";
1172 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1173 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1174 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1175 interrupt-names = "host",
1176 "peripheral",
1177 "otg";
1178 maximum-speed = "super-speed";
1179 dr_mode = "otg";
1180 };
1181 };
1182
1183 usbss1: cdns-usb@4114000 {
1184 compatible = "ti,j721e-usb";
1185 reg = <0x00 0x4114000 0x00 0x100>;
1186 dma-coherent;
1187 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1188 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1189 clock-names = "ref", "lpm";
1190 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1191 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1192 #address-cells = <2>;
1193 #size-cells = <2>;
1194 ranges;
1195
1196 usb1: usb@6400000 {
1197 compatible = "cdns,usb3";
1198 reg = <0x00 0x6400000 0x00 0x10000>,
1199 <0x00 0x6410000 0x00 0x10000>,
1200 <0x00 0x6420000 0x00 0x10000>;
1201 reg-names = "otg", "xhci", "dev";
1202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1203 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1204 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1205 interrupt-names = "host",
1206 "peripheral",
1207 "otg";
1208 maximum-speed = "super-speed";
1209 dr_mode = "otg";
1210 };
1211 };
1212
1213 main_i2c0: i2c@2000000 {
1214 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1215 reg = <0x0 0x2000000 0x0 0x100>;
1216 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219 clock-names = "fck";
1220 clocks = <&k3_clks 187 0>;
1221 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1222 };
1223
1224 main_i2c1: i2c@2010000 {
1225 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1226 reg = <0x0 0x2010000 0x0 0x100>;
1227 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1230 clock-names = "fck";
1231 clocks = <&k3_clks 188 0>;
1232 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1233 };
1234
1235 main_i2c2: i2c@2020000 {
1236 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1237 reg = <0x0 0x2020000 0x0 0x100>;
1238 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241 clock-names = "fck";
1242 clocks = <&k3_clks 189 0>;
1243 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1244 };
1245
1246 main_i2c3: i2c@2030000 {
1247 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1248 reg = <0x0 0x2030000 0x0 0x100>;
1249 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1252 clock-names = "fck";
1253 clocks = <&k3_clks 190 0>;
1254 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1255 };
1256
1257 main_i2c4: i2c@2040000 {
1258 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1259 reg = <0x0 0x2040000 0x0 0x100>;
1260 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1261 #address-cells = <1>;
1262 #size-cells = <0>;
1263 clock-names = "fck";
1264 clocks = <&k3_clks 191 0>;
1265 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1266 };
1267
1268 main_i2c5: i2c@2050000 {
1269 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1270 reg = <0x0 0x2050000 0x0 0x100>;
1271 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 clock-names = "fck";
1275 clocks = <&k3_clks 192 0>;
1276 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1277 };
1278
1279 main_i2c6: i2c@2060000 {
1280 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1281 reg = <0x0 0x2060000 0x0 0x100>;
1282 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 clock-names = "fck";
1286 clocks = <&k3_clks 193 0>;
1287 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1288 };
1289
1290 ufs_wrapper: ufs-wrapper@4e80000 {
1291 compatible = "ti,j721e-ufs";
1292 reg = <0x0 0x4e80000 0x0 0x100>;
1293 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1294 clocks = <&k3_clks 277 1>;
1295 assigned-clocks = <&k3_clks 277 1>;
1296 assigned-clock-parents = <&k3_clks 277 4>;
1297 ranges;
1298 #address-cells = <2>;
1299 #size-cells = <2>;
1300
1301 ufs@4e84000 {
1302 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1303 reg = <0x0 0x4e84000 0x0 0x10000>;
1304 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1305 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1306 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1307 clock-names = "core_clk", "phy_clk", "ref_clk";
1308 dma-coherent;
1309 };
1310 };
1311
1312 mhdp: dp-bridge@a000000 {
1313 compatible = "ti,j721e-mhdp8546";
1314 /*
1315 * Note: we do not map DPTX PHY area, as that is handled by
1316 * the PHY driver.
1317 */
1318 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1319 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1320 reg-names = "mhdptx", "j721e-intg";
1321
1322 clocks = <&k3_clks 151 36>;
1323
1324 interrupt-parent = <&gic500>;
1325 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1326
1327 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1328
1329 dp0_ports: ports {
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1332
1333 port@0 {
1334 reg = <0>;
1335 };
1336
1337 port@4 {
1338 reg = <4>;
1339 };
1340 };
1341 };
1342
1343 dss: dss@4a00000 {
1344 compatible = "ti,j721e-dss";
1345 reg =
1346 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1347 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1348 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1349 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1350
1351 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1352 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1353 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1354 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1355
1356 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1357 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1358 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1359 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1360
1361 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1362 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1363 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1364 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1365 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1366
1367 reg-names = "common_m", "common_s0",
1368 "common_s1", "common_s2",
1369 "vidl1", "vidl2","vid1","vid2",
1370 "ovr1", "ovr2", "ovr3", "ovr4",
1371 "vp1", "vp2", "vp3", "vp4",
1372 "wb";
1373
1374 clocks = <&k3_clks 152 0>,
1375 <&k3_clks 152 1>,
1376 <&k3_clks 152 4>,
1377 <&k3_clks 152 9>,
1378 <&k3_clks 152 13>;
1379 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1380
1381 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1382
1383 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "common_m",
1388 "common_s0",
1389 "common_s1",
1390 "common_s2";
1391
1392 dss_ports: ports {
1393 };
1394 };
1395
1396 mcasp0: mcasp@2b00000 {
1397 compatible = "ti,am33xx-mcasp-audio";
1398 reg = <0x0 0x02b00000 0x0 0x2000>,
1399 <0x0 0x02b08000 0x0 0x1000>;
1400 reg-names = "mpu","dat";
1401 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1403 interrupt-names = "tx", "rx";
1404
1405 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1406 dma-names = "tx", "rx";
1407
1408 clocks = <&k3_clks 174 1>;
1409 clock-names = "fck";
1410 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1411 };
1412
1413 mcasp1: mcasp@2b10000 {
1414 compatible = "ti,am33xx-mcasp-audio";
1415 reg = <0x0 0x02b10000 0x0 0x2000>,
1416 <0x0 0x02b18000 0x0 0x1000>;
1417 reg-names = "mpu","dat";
1418 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1420 interrupt-names = "tx", "rx";
1421
1422 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1423 dma-names = "tx", "rx";
1424
1425 clocks = <&k3_clks 175 1>;
1426 clock-names = "fck";
1427 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1428 };
1429
1430 mcasp2: mcasp@2b20000 {
1431 compatible = "ti,am33xx-mcasp-audio";
1432 reg = <0x0 0x02b20000 0x0 0x2000>,
1433 <0x0 0x02b28000 0x0 0x1000>;
1434 reg-names = "mpu","dat";
1435 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1437 interrupt-names = "tx", "rx";
1438
1439 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1440 dma-names = "tx", "rx";
1441
1442 clocks = <&k3_clks 176 1>;
1443 clock-names = "fck";
1444 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1445 };
1446
1447 mcasp3: mcasp@2b30000 {
1448 compatible = "ti,am33xx-mcasp-audio";
1449 reg = <0x0 0x02b30000 0x0 0x2000>,
1450 <0x0 0x02b38000 0x0 0x1000>;
1451 reg-names = "mpu","dat";
1452 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1454 interrupt-names = "tx", "rx";
1455
1456 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1457 dma-names = "tx", "rx";
1458
1459 clocks = <&k3_clks 177 1>;
1460 clock-names = "fck";
1461 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1462 };
1463
1464 mcasp4: mcasp@2b40000 {
1465 compatible = "ti,am33xx-mcasp-audio";
1466 reg = <0x0 0x02b40000 0x0 0x2000>,
1467 <0x0 0x02b48000 0x0 0x1000>;
1468 reg-names = "mpu","dat";
1469 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1471 interrupt-names = "tx", "rx";
1472
1473 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1474 dma-names = "tx", "rx";
1475
1476 clocks = <&k3_clks 178 1>;
1477 clock-names = "fck";
1478 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1479 };
1480
1481 mcasp5: mcasp@2b50000 {
1482 compatible = "ti,am33xx-mcasp-audio";
1483 reg = <0x0 0x02b50000 0x0 0x2000>,
1484 <0x0 0x02b58000 0x0 0x1000>;
1485 reg-names = "mpu","dat";
1486 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1488 interrupt-names = "tx", "rx";
1489
1490 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1491 dma-names = "tx", "rx";
1492
1493 clocks = <&k3_clks 179 1>;
1494 clock-names = "fck";
1495 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1496 };
1497
1498 mcasp6: mcasp@2b60000 {
1499 compatible = "ti,am33xx-mcasp-audio";
1500 reg = <0x0 0x02b60000 0x0 0x2000>,
1501 <0x0 0x02b68000 0x0 0x1000>;
1502 reg-names = "mpu","dat";
1503 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1505 interrupt-names = "tx", "rx";
1506
1507 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1508 dma-names = "tx", "rx";
1509
1510 clocks = <&k3_clks 180 1>;
1511 clock-names = "fck";
1512 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1513 };
1514
1515 mcasp7: mcasp@2b70000 {
1516 compatible = "ti,am33xx-mcasp-audio";
1517 reg = <0x0 0x02b70000 0x0 0x2000>,
1518 <0x0 0x02b78000 0x0 0x1000>;
1519 reg-names = "mpu","dat";
1520 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1522 interrupt-names = "tx", "rx";
1523
1524 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1525 dma-names = "tx", "rx";
1526
1527 clocks = <&k3_clks 181 1>;
1528 clock-names = "fck";
1529 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1530 };
1531
1532 mcasp8: mcasp@2b80000 {
1533 compatible = "ti,am33xx-mcasp-audio";
1534 reg = <0x0 0x02b80000 0x0 0x2000>,
1535 <0x0 0x02b88000 0x0 0x1000>;
1536 reg-names = "mpu","dat";
1537 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1539 interrupt-names = "tx", "rx";
1540
1541 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1542 dma-names = "tx", "rx";
1543
1544 clocks = <&k3_clks 182 1>;
1545 clock-names = "fck";
1546 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1547 };
1548
1549 mcasp9: mcasp@2b90000 {
1550 compatible = "ti,am33xx-mcasp-audio";
1551 reg = <0x0 0x02b90000 0x0 0x2000>,
1552 <0x0 0x02b98000 0x0 0x1000>;
1553 reg-names = "mpu","dat";
1554 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1556 interrupt-names = "tx", "rx";
1557
1558 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1559 dma-names = "tx", "rx";
1560
1561 clocks = <&k3_clks 183 1>;
1562 clock-names = "fck";
1563 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1564 };
1565
1566 mcasp10: mcasp@2ba0000 {
1567 compatible = "ti,am33xx-mcasp-audio";
1568 reg = <0x0 0x02ba0000 0x0 0x2000>,
1569 <0x0 0x02ba8000 0x0 0x1000>;
1570 reg-names = "mpu","dat";
1571 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1573 interrupt-names = "tx", "rx";
1574
1575 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1576 dma-names = "tx", "rx";
1577
1578 clocks = <&k3_clks 184 1>;
1579 clock-names = "fck";
1580 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1581 };
1582
1583 mcasp11: mcasp@2bb0000 {
1584 compatible = "ti,am33xx-mcasp-audio";
1585 reg = <0x0 0x02bb0000 0x0 0x2000>,
1586 <0x0 0x02bb8000 0x0 0x1000>;
1587 reg-names = "mpu","dat";
1588 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1590 interrupt-names = "tx", "rx";
1591
1592 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1593 dma-names = "tx", "rx";
1594
1595 clocks = <&k3_clks 185 1>;
1596 clock-names = "fck";
1597 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1598 };
1599
1600 watchdog0: watchdog@2200000 {
1601 compatible = "ti,j7-rti-wdt";
1602 reg = <0x0 0x2200000 0x0 0x100>;
1603 clocks = <&k3_clks 252 1>;
1604 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1605 assigned-clocks = <&k3_clks 252 1>;
1606 assigned-clock-parents = <&k3_clks 252 5>;
1607 };
1608
1609 watchdog1: watchdog@2210000 {
1610 compatible = "ti,j7-rti-wdt";
1611 reg = <0x0 0x2210000 0x0 0x100>;
1612 clocks = <&k3_clks 253 1>;
1613 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1614 assigned-clocks = <&k3_clks 253 1>;
1615 assigned-clock-parents = <&k3_clks 253 5>;
1616 };
1617
1618 main_r5fss0: r5fss@5c00000 {
1619 compatible = "ti,j721e-r5fss";
1620 ti,cluster-mode = <1>;
1621 #address-cells = <1>;
1622 #size-cells = <1>;
1623 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1624 <0x5d00000 0x00 0x5d00000 0x20000>;
1625 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1626
1627 main_r5fss0_core0: r5f@5c00000 {
1628 compatible = "ti,j721e-r5f";
1629 reg = <0x5c00000 0x00008000>,
1630 <0x5c10000 0x00008000>;
1631 reg-names = "atcm", "btcm";
1632 ti,sci = <&dmsc>;
1633 ti,sci-dev-id = <245>;
1634 ti,sci-proc-ids = <0x06 0xff>;
1635 resets = <&k3_reset 245 1>;
1636 firmware-name = "j7-main-r5f0_0-fw";
1637 ti,atcm-enable = <1>;
1638 ti,btcm-enable = <1>;
1639 ti,loczrama = <1>;
1640 };
1641
1642 main_r5fss0_core1: r5f@5d00000 {
1643 compatible = "ti,j721e-r5f";
1644 reg = <0x5d00000 0x00008000>,
1645 <0x5d10000 0x00008000>;
1646 reg-names = "atcm", "btcm";
1647 ti,sci = <&dmsc>;
1648 ti,sci-dev-id = <246>;
1649 ti,sci-proc-ids = <0x07 0xff>;
1650 resets = <&k3_reset 246 1>;
1651 firmware-name = "j7-main-r5f0_1-fw";
1652 ti,atcm-enable = <1>;
1653 ti,btcm-enable = <1>;
1654 ti,loczrama = <1>;
1655 };
1656 };
1657
1658 main_r5fss1: r5fss@5e00000 {
1659 compatible = "ti,j721e-r5fss";
1660 ti,cluster-mode = <1>;
1661 #address-cells = <1>;
1662 #size-cells = <1>;
1663 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1664 <0x5f00000 0x00 0x5f00000 0x20000>;
1665 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1666
1667 main_r5fss1_core0: r5f@5e00000 {
1668 compatible = "ti,j721e-r5f";
1669 reg = <0x5e00000 0x00008000>,
1670 <0x5e10000 0x00008000>;
1671 reg-names = "atcm", "btcm";
1672 ti,sci = <&dmsc>;
1673 ti,sci-dev-id = <247>;
1674 ti,sci-proc-ids = <0x08 0xff>;
1675 resets = <&k3_reset 247 1>;
1676 firmware-name = "j7-main-r5f1_0-fw";
1677 ti,atcm-enable = <1>;
1678 ti,btcm-enable = <1>;
1679 ti,loczrama = <1>;
1680 };
1681
1682 main_r5fss1_core1: r5f@5f00000 {
1683 compatible = "ti,j721e-r5f";
1684 reg = <0x5f00000 0x00008000>,
1685 <0x5f10000 0x00008000>;
1686 reg-names = "atcm", "btcm";
1687 ti,sci = <&dmsc>;
1688 ti,sci-dev-id = <248>;
1689 ti,sci-proc-ids = <0x09 0xff>;
1690 resets = <&k3_reset 248 1>;
1691 firmware-name = "j7-main-r5f1_1-fw";
1692 ti,atcm-enable = <1>;
1693 ti,btcm-enable = <1>;
1694 ti,loczrama = <1>;
1695 };
1696 };
1697
1698 c66_0: dsp@4d80800000 {
1699 compatible = "ti,j721e-c66-dsp";
1700 reg = <0x4d 0x80800000 0x00 0x00048000>,
1701 <0x4d 0x80e00000 0x00 0x00008000>,
1702 <0x4d 0x80f00000 0x00 0x00008000>;
1703 reg-names = "l2sram", "l1pram", "l1dram";
1704 ti,sci = <&dmsc>;
1705 ti,sci-dev-id = <142>;
1706 ti,sci-proc-ids = <0x03 0xff>;
1707 resets = <&k3_reset 142 1>;
1708 firmware-name = "j7-c66_0-fw";
1709 };
1710
1711 c66_1: dsp@4d81800000 {
1712 compatible = "ti,j721e-c66-dsp";
1713 reg = <0x4d 0x81800000 0x00 0x00048000>,
1714 <0x4d 0x81e00000 0x00 0x00008000>,
1715 <0x4d 0x81f00000 0x00 0x00008000>;
1716 reg-names = "l2sram", "l1pram", "l1dram";
1717 ti,sci = <&dmsc>;
1718 ti,sci-dev-id = <143>;
1719 ti,sci-proc-ids = <0x04 0xff>;
1720 resets = <&k3_reset 143 1>;
1721 firmware-name = "j7-c66_1-fw";
1722 };
1723
1724 c71_0: dsp@64800000 {
1725 compatible = "ti,j721e-c71-dsp";
1726 reg = <0x00 0x64800000 0x00 0x00080000>,
1727 <0x00 0x64e00000 0x00 0x0000c000>;
1728 reg-names = "l2sram", "l1dram";
1729 ti,sci = <&dmsc>;
1730 ti,sci-dev-id = <15>;
1731 ti,sci-proc-ids = <0x30 0xff>;
1732 resets = <&k3_reset 15 1>;
1733 firmware-name = "j7-c71_0-fw";
1734 };
1735
1736 icssg0: icssg@b000000 {
1737 compatible = "ti,j721e-icssg";
1738 reg = <0x00 0xb000000 0x00 0x80000>;
1739 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
1740 #address-cells = <1>;
1741 #size-cells = <1>;
1742 ranges = <0x0 0x00 0x0b000000 0x100000>;
1743
1744 icssg0_mem: memories@0 {
1745 reg = <0x0 0x2000>,
1746 <0x2000 0x2000>,
1747 <0x10000 0x10000>;
1748 reg-names = "dram0", "dram1",
1749 "shrdram2";
1750 };
1751
1752 icssg0_cfg: cfg@26000 {
1753 compatible = "ti,pruss-cfg", "syscon";
1754 reg = <0x26000 0x200>;
1755 #address-cells = <1>;
1756 #size-cells = <1>;
1757 ranges = <0x0 0x26000 0x2000>;
1758
1759 clocks {
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1762
1763 icssg0_coreclk_mux: coreclk-mux@3c {
1764 reg = <0x3c>;
1765 #clock-cells = <0>;
1766 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
1767 <&k3_clks 119 1>; /* icssg0_iclk */
1768 assigned-clocks = <&icssg0_coreclk_mux>;
1769 assigned-clock-parents = <&k3_clks 119 1>;
1770 };
1771
1772 icssg0_iepclk_mux: iepclk-mux@30 {
1773 reg = <0x30>;
1774 #clock-cells = <0>;
1775 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
1776 <&icssg0_coreclk_mux>; /* core_clk */
1777 assigned-clocks = <&icssg0_iepclk_mux>;
1778 assigned-clock-parents = <&icssg0_coreclk_mux>;
1779 };
1780 };
1781 };
1782
1783 icssg0_mii_rt: mii-rt@32000 {
1784 compatible = "ti,pruss-mii", "syscon";
1785 reg = <0x32000 0x100>;
1786 };
1787
1788 icssg0_mii_g_rt: mii-g-rt@33000 {
1789 compatible = "ti,pruss-mii-g", "syscon";
1790 reg = <0x33000 0x1000>;
1791 };
1792
1793 icssg0_intc: interrupt-controller@20000 {
1794 compatible = "ti,icssg-intc";
1795 reg = <0x20000 0x2000>;
1796 interrupt-controller;
1797 #interrupt-cells = <3>;
1798 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1801 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1806 interrupt-names = "host_intr0", "host_intr1",
1807 "host_intr2", "host_intr3",
1808 "host_intr4", "host_intr5",
1809 "host_intr6", "host_intr7";
1810 };
1811
1812 pru0_0: pru@34000 {
1813 compatible = "ti,j721e-pru";
1814 reg = <0x34000 0x3000>,
1815 <0x22000 0x100>,
1816 <0x22400 0x100>;
1817 reg-names = "iram", "control", "debug";
1818 firmware-name = "j7-pru0_0-fw";
1819 };
1820
1821 rtu0_0: rtu@4000 {
1822 compatible = "ti,j721e-rtu";
1823 reg = <0x4000 0x2000>,
1824 <0x23000 0x100>,
1825 <0x23400 0x100>;
1826 reg-names = "iram", "control", "debug";
1827 firmware-name = "j7-rtu0_0-fw";
1828 };
1829
1830 tx_pru0_0: txpru@a000 {
1831 compatible = "ti,j721e-tx-pru";
1832 reg = <0xa000 0x1800>,
1833 <0x25000 0x100>,
1834 <0x25400 0x100>;
1835 reg-names = "iram", "control", "debug";
1836 firmware-name = "j7-txpru0_0-fw";
1837 };
1838
1839 pru0_1: pru@38000 {
1840 compatible = "ti,j721e-pru";
1841 reg = <0x38000 0x3000>,
1842 <0x24000 0x100>,
1843 <0x24400 0x100>;
1844 reg-names = "iram", "control", "debug";
1845 firmware-name = "j7-pru0_1-fw";
1846 };
1847
1848 rtu0_1: rtu@6000 {
1849 compatible = "ti,j721e-rtu";
1850 reg = <0x6000 0x2000>,
1851 <0x23800 0x100>,
1852 <0x23c00 0x100>;
1853 reg-names = "iram", "control", "debug";
1854 firmware-name = "j7-rtu0_1-fw";
1855 };
1856
1857 tx_pru0_1: txpru@c000 {
1858 compatible = "ti,j721e-tx-pru";
1859 reg = <0xc000 0x1800>,
1860 <0x25800 0x100>,
1861 <0x25c00 0x100>;
1862 reg-names = "iram", "control", "debug";
1863 firmware-name = "j7-txpru0_1-fw";
1864 };
1865
1866 icssg0_mdio: mdio@32400 {
1867 compatible = "ti,davinci_mdio";
1868 reg = <0x32400 0x100>;
1869 clocks = <&k3_clks 119 1>;
1870 clock-names = "fck";
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1873 bus_freq = <1000000>;
1874 };
1875 };
1876
1877 icssg1: icssg@b100000 {
1878 compatible = "ti,j721e-icssg";
1879 reg = <0x00 0xb100000 0x00 0x80000>;
1880 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0x0 0x00 0x0b100000 0x100000>;
1884
1885 icssg1_mem: memories@b100000 {
1886 reg = <0x0 0x2000>,
1887 <0x2000 0x2000>,
1888 <0x10000 0x10000>;
1889 reg-names = "dram0", "dram1",
1890 "shrdram2";
1891 };
1892
1893 icssg1_cfg: cfg@26000 {
1894 compatible = "ti,pruss-cfg", "syscon";
1895 reg = <0x26000 0x200>;
1896 #address-cells = <1>;
1897 #size-cells = <1>;
1898 ranges = <0x0 0x26000 0x2000>;
1899
1900 clocks {
1901 #address-cells = <1>;
1902 #size-cells = <0>;
1903
1904 icssg1_coreclk_mux: coreclk-mux@3c {
1905 reg = <0x3c>;
1906 #clock-cells = <0>;
1907 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
1908 <&k3_clks 120 4>; /* icssg1_iclk */
1909 assigned-clocks = <&icssg1_coreclk_mux>;
1910 assigned-clock-parents = <&k3_clks 120 4>;
1911 };
1912
1913 icssg1_iepclk_mux: iepclk-mux@30 {
1914 reg = <0x30>;
1915 #clock-cells = <0>;
1916 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
1917 <&icssg1_coreclk_mux>; /* core_clk */
1918 assigned-clocks = <&icssg1_iepclk_mux>;
1919 assigned-clock-parents = <&icssg1_coreclk_mux>;
1920 };
1921 };
1922 };
1923
1924 icssg1_mii_rt: mii-rt@32000 {
1925 compatible = "ti,pruss-mii", "syscon";
1926 reg = <0x32000 0x100>;
1927 };
1928
1929 icssg1_mii_g_rt: mii-g-rt@33000 {
1930 compatible = "ti,pruss-mii-g", "syscon";
1931 reg = <0x33000 0x1000>;
1932 };
1933
1934 icssg1_intc: interrupt-controller@20000 {
1935 compatible = "ti,icssg-intc";
1936 reg = <0x20000 0x2000>;
1937 interrupt-controller;
1938 #interrupt-cells = <3>;
1939 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1947 interrupt-names = "host_intr0", "host_intr1",
1948 "host_intr2", "host_intr3",
1949 "host_intr4", "host_intr5",
1950 "host_intr6", "host_intr7";
1951 };
1952
1953 pru1_0: pru@34000 {
1954 compatible = "ti,j721e-pru";
1955 reg = <0x34000 0x4000>,
1956 <0x22000 0x100>,
1957 <0x22400 0x100>;
1958 reg-names = "iram", "control", "debug";
1959 firmware-name = "j7-pru1_0-fw";
1960 };
1961
1962 rtu1_0: rtu@4000 {
1963 compatible = "ti,j721e-rtu";
1964 reg = <0x4000 0x2000>,
1965 <0x23000 0x100>,
1966 <0x23400 0x100>;
1967 reg-names = "iram", "control", "debug";
1968 firmware-name = "j7-rtu1_0-fw";
1969 };
1970
1971 tx_pru1_0: txpru@a000 {
1972 compatible = "ti,j721e-tx-pru";
1973 reg = <0xa000 0x1800>,
1974 <0x25000 0x100>,
1975 <0x25400 0x100>;
1976 reg-names = "iram", "control", "debug";
1977 firmware-name = "j7-txpru1_0-fw";
1978 };
1979
1980 pru1_1: pru@38000 {
1981 compatible = "ti,j721e-pru";
1982 reg = <0x38000 0x4000>,
1983 <0x24000 0x100>,
1984 <0x24400 0x100>;
1985 reg-names = "iram", "control", "debug";
1986 firmware-name = "j7-pru1_1-fw";
1987 };
1988
1989 rtu1_1: rtu@6000 {
1990 compatible = "ti,j721e-rtu";
1991 reg = <0x6000 0x2000>,
1992 <0x23800 0x100>,
1993 <0x23c00 0x100>;
1994 reg-names = "iram", "control", "debug";
1995 firmware-name = "j7-rtu1_1-fw";
1996 };
1997
1998 tx_pru1_1: txpru@c000 {
1999 compatible = "ti,j721e-tx-pru";
2000 reg = <0xc000 0x1800>,
2001 <0x25800 0x100>,
2002 <0x25c00 0x100>;
2003 reg-names = "iram", "control", "debug";
2004 firmware-name = "j7-txpru1_1-fw";
2005 };
2006
2007 icssg1_mdio: mdio@32400 {
2008 compatible = "ti,davinci_mdio";
2009 reg = <0x32400 0x100>;
2010 clocks = <&k3_clks 120 4>;
2011 clock-names = "fck";
2012 #address-cells = <1>;
2013 #size-cells = <0>;
2014 bus_freq = <1000000>;
2015 };
2016 };
2017
2018 main_mcan0: can@2701000 {
2019 compatible = "bosch,m_can";
2020 reg = <0x00 0x02701000 0x00 0x200>,
2021 <0x00 0x02708000 0x00 0x8000>;
2022 reg-names = "m_can", "message_ram";
2023 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2024 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2025 clock-names = "hclk", "cclk";
2026 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2028 interrupt-names = "int0", "int1";
2029 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2030 };
2031
2032 main_mcan1: can@2711000 {
2033 compatible = "bosch,m_can";
2034 reg = <0x00 0x02711000 0x00 0x200>,
2035 <0x00 0x02718000 0x00 0x8000>;
2036 reg-names = "m_can", "message_ram";
2037 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2038 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2039 clock-names = "hclk", "cclk";
2040 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2042 interrupt-names = "int0", "int1";
2043 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2044 };
2045
2046 main_mcan2: can@2721000 {
2047 compatible = "bosch,m_can";
2048 reg = <0x00 0x02721000 0x00 0x200>,
2049 <0x00 0x02728000 0x00 0x8000>;
2050 reg-names = "m_can", "message_ram";
2051 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2052 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2053 clock-names = "hclk", "cclk";
2054 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2055 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2056 interrupt-names = "int0", "int1";
2057 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2058 };
2059
2060 main_mcan3: can@2731000 {
2061 compatible = "bosch,m_can";
2062 reg = <0x00 0x02731000 0x00 0x200>,
2063 <0x00 0x02738000 0x00 0x8000>;
2064 reg-names = "m_can", "message_ram";
2065 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2066 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2067 clock-names = "hclk", "cclk";
2068 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2069 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2070 interrupt-names = "int0", "int1";
2071 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2072 };
2073
2074 main_mcan4: can@2741000 {
2075 compatible = "bosch,m_can";
2076 reg = <0x00 0x02741000 0x00 0x200>,
2077 <0x00 0x02748000 0x00 0x8000>;
2078 reg-names = "m_can", "message_ram";
2079 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2080 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2081 clock-names = "hclk", "cclk";
2082 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2084 interrupt-names = "int0", "int1";
2085 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2086 };
2087
2088 main_mcan5: can@2751000 {
2089 compatible = "bosch,m_can";
2090 reg = <0x00 0x02751000 0x00 0x200>,
2091 <0x00 0x02758000 0x00 0x8000>;
2092 reg-names = "m_can", "message_ram";
2093 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2094 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2095 clock-names = "hclk", "cclk";
2096 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2098 interrupt-names = "int0", "int1";
2099 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2100 };
2101
2102 main_mcan6: can@2761000 {
2103 compatible = "bosch,m_can";
2104 reg = <0x00 0x02761000 0x00 0x200>,
2105 <0x00 0x02768000 0x00 0x8000>;
2106 reg-names = "m_can", "message_ram";
2107 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2108 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2109 clock-names = "hclk", "cclk";
2110 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2112 interrupt-names = "int0", "int1";
2113 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2114 };
2115
2116 main_mcan7: can@2771000 {
2117 compatible = "bosch,m_can";
2118 reg = <0x00 0x02771000 0x00 0x200>,
2119 <0x00 0x02778000 0x00 0x8000>;
2120 reg-names = "m_can", "message_ram";
2121 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2122 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2123 clock-names = "hclk", "cclk";
2124 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2126 interrupt-names = "int0", "int1";
2127 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2128 };
2129
2130 main_mcan8: can@2781000 {
2131 compatible = "bosch,m_can";
2132 reg = <0x00 0x02781000 0x00 0x200>,
2133 <0x00 0x02788000 0x00 0x8000>;
2134 reg-names = "m_can", "message_ram";
2135 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2136 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2137 clock-names = "hclk", "cclk";
2138 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2139 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2140 interrupt-names = "int0", "int1";
2141 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2142 };
2143
2144 main_mcan9: can@2791000 {
2145 compatible = "bosch,m_can";
2146 reg = <0x00 0x02791000 0x00 0x200>,
2147 <0x00 0x02798000 0x00 0x8000>;
2148 reg-names = "m_can", "message_ram";
2149 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2150 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2151 clock-names = "hclk", "cclk";
2152 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2154 interrupt-names = "int0", "int1";
2155 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2156 };
2157
2158 main_mcan10: can@27a1000 {
2159 compatible = "bosch,m_can";
2160 reg = <0x00 0x027a1000 0x00 0x200>,
2161 <0x00 0x027a8000 0x00 0x8000>;
2162 reg-names = "m_can", "message_ram";
2163 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2164 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2165 clock-names = "hclk", "cclk";
2166 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2167 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2168 interrupt-names = "int0", "int1";
2169 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2170 };
2171
2172 main_mcan11: can@27b1000 {
2173 compatible = "bosch,m_can";
2174 reg = <0x00 0x027b1000 0x00 0x200>,
2175 <0x00 0x027b8000 0x00 0x8000>;
2176 reg-names = "m_can", "message_ram";
2177 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2178 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2179 clock-names = "hclk", "cclk";
2180 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2181 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2182 interrupt-names = "int0", "int1";
2183 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2184 };
2185
2186 main_mcan12: can@27c1000 {
2187 compatible = "bosch,m_can";
2188 reg = <0x00 0x027c1000 0x00 0x200>,
2189 <0x00 0x027c8000 0x00 0x8000>;
2190 reg-names = "m_can", "message_ram";
2191 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2192 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2193 clock-names = "hclk", "cclk";
2194 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2195 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2196 interrupt-names = "int0", "int1";
2197 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2198 };
2199
2200 main_mcan13: can@27d1000 {
2201 compatible = "bosch,m_can";
2202 reg = <0x00 0x027d1000 0x00 0x200>,
2203 <0x00 0x027d8000 0x00 0x8000>;
2204 reg-names = "m_can", "message_ram";
2205 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2206 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2207 clock-names = "hclk", "cclk";
2208 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2210 interrupt-names = "int0", "int1";
2211 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2212 };
2213 };
