0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "k3-j7200-som-p0.dtsi"
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/net/ti-dp83867.h>
0011 #include <dt-bindings/mux/ti-serdes.h>
0012 #include <dt-bindings/phy/phy.h>
0013
0014 / {
0015 compatible = "ti,j7200-evm", "ti,j7200";
0016 model = "Texas Instruments J7200 EVM";
0017
0018 chosen {
0019 stdout-path = "serial2:115200n8";
0020 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
0021 };
0022
0023 evm_12v0: fixedregulator-evm12v0 {
0024 /* main supply */
0025 compatible = "regulator-fixed";
0026 regulator-name = "evm_12v0";
0027 regulator-min-microvolt = <12000000>;
0028 regulator-max-microvolt = <12000000>;
0029 regulator-always-on;
0030 regulator-boot-on;
0031 };
0032
0033 vsys_3v3: fixedregulator-vsys3v3 {
0034 /* Output of LM5140 */
0035 compatible = "regulator-fixed";
0036 regulator-name = "vsys_3v3";
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 vin-supply = <&evm_12v0>;
0040 regulator-always-on;
0041 regulator-boot-on;
0042 };
0043
0044 vsys_5v0: fixedregulator-vsys5v0 {
0045 /* Output of LM5140 */
0046 compatible = "regulator-fixed";
0047 regulator-name = "vsys_5v0";
0048 regulator-min-microvolt = <5000000>;
0049 regulator-max-microvolt = <5000000>;
0050 vin-supply = <&evm_12v0>;
0051 regulator-always-on;
0052 regulator-boot-on;
0053 };
0054
0055 vdd_mmc1: fixedregulator-sd {
0056 /* Output of TPS22918 */
0057 compatible = "regulator-fixed";
0058 regulator-name = "vdd_mmc1";
0059 regulator-min-microvolt = <3300000>;
0060 regulator-max-microvolt = <3300000>;
0061 regulator-boot-on;
0062 enable-active-high;
0063 vin-supply = <&vsys_3v3>;
0064 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
0065 };
0066
0067 vdd_sd_dv: gpio-regulator-TLV71033 {
0068 /* Output of TLV71033 */
0069 compatible = "regulator-gpio";
0070 regulator-name = "tlv71033";
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&vdd_sd_dv_pins_default>;
0073 regulator-min-microvolt = <1800000>;
0074 regulator-max-microvolt = <3300000>;
0075 regulator-boot-on;
0076 vin-supply = <&vsys_5v0>;
0077 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
0078 states = <1800000 0x0>,
0079 <3300000 0x1>;
0080 };
0081 };
0082
0083 &wkup_pmx0 {
0084 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
0085 pinctrl-single,pins = <
0086 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
0087 J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
0088 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
0089 J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
0090 J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
0091 J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
0092 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
0093 J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
0094 J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
0095 J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
0096 J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
0097 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
0098 >;
0099 };
0100
0101 mcu_mdio_pins_default: mcu-mdio1-pins-default {
0102 pinctrl-single,pins = <
0103 J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
0104 J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
0105 >;
0106 };
0107 };
0108
0109 &main_pmx0 {
0110 main_i2c0_pins_default: main-i2c0-pins-default {
0111 pinctrl-single,pins = <
0112 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
0113 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
0114 >;
0115 };
0116
0117 main_i2c1_pins_default: main-i2c1-pins-default {
0118 pinctrl-single,pins = <
0119 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
0120 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
0121 >;
0122 };
0123
0124 main_mmc1_pins_default: main-mmc1-pins-default {
0125 pinctrl-single,pins = <
0126 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
0127 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
0128 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
0129 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
0130 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
0131 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
0132 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
0133 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
0134 >;
0135 };
0136
0137 main_usbss0_pins_default: main-usbss0-pins-default {
0138 pinctrl-single,pins = <
0139 J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
0140 >;
0141 };
0142
0143 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
0144 pinctrl-single,pins = <
0145 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
0146 >;
0147 };
0148 };
0149
0150 &wkup_uart0 {
0151 /* Wakeup UART is used by System firmware */
0152 status = "reserved";
0153 };
0154
0155 &main_uart0 {
0156 /* Shared with ATF on this platform */
0157 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
0158 };
0159
0160 &main_uart2 {
0161 /* MAIN UART 2 is used by R5F firmware */
0162 status = "reserved";
0163 };
0164
0165 &main_uart3 {
0166 /* UART not brought out */
0167 status = "disabled";
0168 };
0169
0170 &main_uart4 {
0171 /* UART not brought out */
0172 status = "disabled";
0173 };
0174
0175 &main_uart5 {
0176 /* UART not brought out */
0177 status = "disabled";
0178 };
0179
0180 &main_uart6 {
0181 /* UART not brought out */
0182 status = "disabled";
0183 };
0184
0185 &main_uart7 {
0186 /* UART not brought out */
0187 status = "disabled";
0188 };
0189
0190 &main_uart8 {
0191 /* UART not brought out */
0192 status = "disabled";
0193 };
0194
0195 &main_uart9 {
0196 /* UART not brought out */
0197 status = "disabled";
0198 };
0199
0200 &main_gpio2 {
0201 status = "disabled";
0202 };
0203
0204 &main_gpio4 {
0205 status = "disabled";
0206 };
0207
0208 &main_gpio6 {
0209 status = "disabled";
0210 };
0211
0212 &wkup_gpio1 {
0213 status = "disabled";
0214 };
0215
0216 &mcu_cpsw {
0217 pinctrl-names = "default";
0218 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
0219 };
0220
0221 &davinci_mdio {
0222 phy0: ethernet-phy@0 {
0223 reg = <0>;
0224 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0225 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0226 };
0227 };
0228
0229 &cpsw_port1 {
0230 phy-mode = "rgmii-rxid";
0231 phy-handle = <&phy0>;
0232 };
0233
0234 &main_i2c0 {
0235 pinctrl-names = "default";
0236 pinctrl-0 = <&main_i2c0_pins_default>;
0237 clock-frequency = <400000>;
0238
0239 exp1: gpio@20 {
0240 compatible = "ti,tca6416";
0241 reg = <0x20>;
0242 gpio-controller;
0243 #gpio-cells = <2>;
0244 };
0245
0246 exp2: gpio@22 {
0247 compatible = "ti,tca6424";
0248 reg = <0x22>;
0249 gpio-controller;
0250 #gpio-cells = <2>;
0251 };
0252 };
0253
0254 /*
0255 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
0256 * swapped on the CPB.
0257 *
0258 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
0259 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
0260 */
0261 &main_i2c1 {
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&main_i2c1_pins_default>;
0264 clock-frequency = <400000>;
0265
0266 exp3: gpio@20 {
0267 compatible = "ti,tca6408";
0268 reg = <0x20>;
0269 gpio-controller;
0270 #gpio-cells = <2>;
0271 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
0272 "UB926_LOCK", "UB926_PWR_SW_CNTRL",
0273 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
0274 };
0275 };
0276
0277 &main_sdhci0 {
0278 /* eMMC */
0279 non-removable;
0280 ti,driver-strength-ohm = <50>;
0281 disable-wp;
0282 };
0283
0284 &main_sdhci1 {
0285 /* SD card */
0286 pinctrl-0 = <&main_mmc1_pins_default>;
0287 pinctrl-names = "default";
0288 vmmc-supply = <&vdd_mmc1>;
0289 vqmmc-supply = <&vdd_sd_dv>;
0290 ti,driver-strength-ohm = <50>;
0291 disable-wp;
0292 };
0293
0294 &serdes_ln_ctrl {
0295 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
0296 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
0297 };
0298
0299 &usb_serdes_mux {
0300 idle-states = <1>; /* USB0 to SERDES lane 3 */
0301 };
0302
0303 &usbss0 {
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&main_usbss0_pins_default>;
0306 ti,vbus-divider;
0307 ti,usb2-only;
0308 };
0309
0310 &usb0 {
0311 dr_mode = "otg";
0312 maximum-speed = "high-speed";
0313 };
0314
0315 &tscadc0 {
0316 adc {
0317 ti,adc-channels = <0 1 2 3 4 5 6 7>;
0318 };
0319 };
0320
0321 &serdes_refclk {
0322 clock-frequency = <100000000>;
0323 };
0324
0325 &serdes0 {
0326 serdes0_pcie_link: phy@0 {
0327 reg = <0>;
0328 cdns,num-lanes = <2>;
0329 #phy-cells = <0>;
0330 cdns,phy-type = <PHY_TYPE_PCIE>;
0331 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
0332 };
0333
0334 serdes0_qsgmii_link: phy@1 {
0335 reg = <2>;
0336 cdns,num-lanes = <1>;
0337 #phy-cells = <0>;
0338 cdns,phy-type = <PHY_TYPE_QSGMII>;
0339 resets = <&serdes_wiz0 3>;
0340 };
0341 };
0342
0343 &pcie1_rc {
0344 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
0345 phys = <&serdes0_pcie_link>;
0346 phy-names = "pcie-phy";
0347 num-lanes = <2>;
0348 };
0349
0350 &pcie1_ep {
0351 phys = <&serdes0_pcie_link>;
0352 phy-names = "pcie-phy";
0353 num-lanes = <2>;
0354 status = "disabled";
0355 };
