0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM6 SoC family in Quad core configuration
0004 *
0005 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include "k3-am65.dtsi"
0009
0010 / {
0011 cpus {
0012 #address-cells = <1>;
0013 #size-cells = <0>;
0014 cpu-map {
0015 cluster0: cluster0 {
0016 core0 {
0017 cpu = <&cpu0>;
0018 };
0019
0020 core1 {
0021 cpu = <&cpu1>;
0022 };
0023 };
0024
0025 cluster1: cluster1 {
0026 core0 {
0027 cpu = <&cpu2>;
0028 };
0029
0030 core1 {
0031 cpu = <&cpu3>;
0032 };
0033 };
0034 };
0035
0036 cpu0: cpu@0 {
0037 compatible = "arm,cortex-a53";
0038 reg = <0x000>;
0039 device_type = "cpu";
0040 enable-method = "psci";
0041 i-cache-size = <0x8000>;
0042 i-cache-line-size = <64>;
0043 i-cache-sets = <256>;
0044 d-cache-size = <0x8000>;
0045 d-cache-line-size = <64>;
0046 d-cache-sets = <128>;
0047 next-level-cache = <&L2_0>;
0048 };
0049
0050 cpu1: cpu@1 {
0051 compatible = "arm,cortex-a53";
0052 reg = <0x001>;
0053 device_type = "cpu";
0054 enable-method = "psci";
0055 i-cache-size = <0x8000>;
0056 i-cache-line-size = <64>;
0057 i-cache-sets = <256>;
0058 d-cache-size = <0x8000>;
0059 d-cache-line-size = <64>;
0060 d-cache-sets = <128>;
0061 next-level-cache = <&L2_0>;
0062 };
0063
0064 cpu2: cpu@100 {
0065 compatible = "arm,cortex-a53";
0066 reg = <0x100>;
0067 device_type = "cpu";
0068 enable-method = "psci";
0069 i-cache-size = <0x8000>;
0070 i-cache-line-size = <64>;
0071 i-cache-sets = <256>;
0072 d-cache-size = <0x8000>;
0073 d-cache-line-size = <64>;
0074 d-cache-sets = <128>;
0075 next-level-cache = <&L2_1>;
0076 };
0077
0078 cpu3: cpu@101 {
0079 compatible = "arm,cortex-a53";
0080 reg = <0x101>;
0081 device_type = "cpu";
0082 enable-method = "psci";
0083 i-cache-size = <0x8000>;
0084 i-cache-line-size = <64>;
0085 i-cache-sets = <256>;
0086 d-cache-size = <0x8000>;
0087 d-cache-line-size = <64>;
0088 d-cache-sets = <128>;
0089 next-level-cache = <&L2_1>;
0090 };
0091 };
0092
0093 L2_0: l2-cache0 {
0094 compatible = "cache";
0095 cache-level = <2>;
0096 cache-size = <0x80000>;
0097 cache-line-size = <64>;
0098 cache-sets = <512>;
0099 next-level-cache = <&msmc_l3>;
0100 };
0101
0102 L2_1: l2-cache1 {
0103 compatible = "cache";
0104 cache-level = <2>;
0105 cache-size = <0x80000>;
0106 cache-line-size = <64>;
0107 cache-sets = <512>;
0108 next-level-cache = <&msmc_l3>;
0109 };
0110
0111 msmc_l3: l3-cache0 {
0112 compatible = "cache";
0113 cache-level = <3>;
0114 };
0115
0116 thermal_zones: thermal-zones {
0117 #include "k3-am654-industrial-thermal.dtsi"
0118 };
0119 };
