0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for AM625 SoC family in Quad core configuration
0004 *
0005 * TRM: https://www.ti.com/lit/pdf/spruiv7
0006 *
0007 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
0008 */
0009
0010 /dts-v1/;
0011
0012 #include "k3-am62.dtsi"
0013
0014 / {
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu-map {
0020 cluster0: cluster0 {
0021 core0 {
0022 cpu = <&cpu0>;
0023 };
0024
0025 core1 {
0026 cpu = <&cpu1>;
0027 };
0028
0029 core2 {
0030 cpu = <&cpu2>;
0031 };
0032
0033 core3 {
0034 cpu = <&cpu3>;
0035 };
0036 };
0037 };
0038
0039 cpu0: cpu@0 {
0040 compatible = "arm,cortex-a53";
0041 reg = <0x000>;
0042 device_type = "cpu";
0043 enable-method = "psci";
0044 i-cache-size = <0x8000>;
0045 i-cache-line-size = <64>;
0046 i-cache-sets = <256>;
0047 d-cache-size = <0x8000>;
0048 d-cache-line-size = <64>;
0049 d-cache-sets = <128>;
0050 next-level-cache = <&L2_0>;
0051 };
0052
0053 cpu1: cpu@1 {
0054 compatible = "arm,cortex-a53";
0055 reg = <0x001>;
0056 device_type = "cpu";
0057 enable-method = "psci";
0058 i-cache-size = <0x8000>;
0059 i-cache-line-size = <64>;
0060 i-cache-sets = <256>;
0061 d-cache-size = <0x8000>;
0062 d-cache-line-size = <64>;
0063 d-cache-sets = <128>;
0064 next-level-cache = <&L2_0>;
0065 };
0066
0067 cpu2: cpu@2 {
0068 compatible = "arm,cortex-a53";
0069 reg = <0x002>;
0070 device_type = "cpu";
0071 enable-method = "psci";
0072 i-cache-size = <0x8000>;
0073 i-cache-line-size = <64>;
0074 i-cache-sets = <256>;
0075 d-cache-size = <0x8000>;
0076 d-cache-line-size = <64>;
0077 d-cache-sets = <128>;
0078 next-level-cache = <&L2_0>;
0079 };
0080
0081 cpu3: cpu@3 {
0082 compatible = "arm,cortex-a53";
0083 reg = <0x003>;
0084 device_type = "cpu";
0085 enable-method = "psci";
0086 i-cache-size = <0x8000>;
0087 i-cache-line-size = <64>;
0088 i-cache-sets = <256>;
0089 d-cache-size = <0x8000>;
0090 d-cache-line-size = <64>;
0091 d-cache-sets = <128>;
0092 next-level-cache = <&L2_0>;
0093 };
0094 };
0095
0096 L2_0: l2-cache0 {
0097 compatible = "cache";
0098 cache-level = <2>;
0099 cache-size = <0x40000>;
0100 cache-line-size = <64>;
0101 cache-sets = <512>;
0102 };
0103 };
