0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2015 Marvell Technology Group Ltd.
0004 *
0005 * Author: Jisheng Zhang <jszhang@marvell.com>
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 compatible = "marvell,berlin4ct", "marvell,berlin";
0012 interrupt-parent = <&gic>;
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 aliases {
0017 serial0 = &uart0;
0018 };
0019
0020 psci {
0021 compatible = "arm,psci-1.0", "arm,psci-0.2";
0022 method = "smc";
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 cpu0: cpu@0 {
0030 compatible = "arm,cortex-a53";
0031 device_type = "cpu";
0032 reg = <0x0>;
0033 enable-method = "psci";
0034 next-level-cache = <&l2>;
0035 cpu-idle-states = <&CPU_SLEEP_0>;
0036 };
0037
0038 cpu1: cpu@1 {
0039 compatible = "arm,cortex-a53";
0040 device_type = "cpu";
0041 reg = <0x1>;
0042 enable-method = "psci";
0043 next-level-cache = <&l2>;
0044 cpu-idle-states = <&CPU_SLEEP_0>;
0045 };
0046
0047 cpu2: cpu@2 {
0048 compatible = "arm,cortex-a53";
0049 device_type = "cpu";
0050 reg = <0x2>;
0051 enable-method = "psci";
0052 next-level-cache = <&l2>;
0053 cpu-idle-states = <&CPU_SLEEP_0>;
0054 };
0055
0056 cpu3: cpu@3 {
0057 compatible = "arm,cortex-a53";
0058 device_type = "cpu";
0059 reg = <0x3>;
0060 enable-method = "psci";
0061 next-level-cache = <&l2>;
0062 cpu-idle-states = <&CPU_SLEEP_0>;
0063 };
0064
0065 l2: cache {
0066 compatible = "cache";
0067 };
0068
0069 idle-states {
0070 entry-method = "psci";
0071 CPU_SLEEP_0: cpu-sleep-0 {
0072 compatible = "arm,idle-state";
0073 local-timer-stop;
0074 arm,psci-suspend-param = <0x0010000>;
0075 entry-latency-us = <75>;
0076 exit-latency-us = <155>;
0077 min-residency-us = <1000>;
0078 };
0079 };
0080 };
0081
0082 osc: osc {
0083 compatible = "fixed-clock";
0084 #clock-cells = <0>;
0085 clock-frequency = <25000000>;
0086 };
0087
0088 pmu {
0089 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
0090 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0094 interrupt-affinity = <&cpu0>,
0095 <&cpu1>,
0096 <&cpu2>,
0097 <&cpu3>;
0098 };
0099
0100 timer {
0101 compatible = "arm,armv8-timer";
0102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0106 };
0107
0108 soc@f7000000 {
0109 compatible = "simple-bus";
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 ranges = <0 0 0xf7000000 0x1000000>;
0113
0114 gic: interrupt-controller@901000 {
0115 compatible = "arm,gic-400";
0116 #interrupt-cells = <3>;
0117 interrupt-controller;
0118 reg = <0x901000 0x1000>,
0119 <0x902000 0x2000>,
0120 <0x904000 0x2000>,
0121 <0x906000 0x2000>;
0122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0123 };
0124
0125 apb@e80000 {
0126 compatible = "simple-bus";
0127 #address-cells = <1>;
0128 #size-cells = <1>;
0129
0130 ranges = <0 0xe80000 0x10000>;
0131 interrupt-parent = <&aic>;
0132
0133 gpio0: gpio@400 {
0134 compatible = "snps,dw-apb-gpio";
0135 reg = <0x0400 0x400>;
0136 #address-cells = <1>;
0137 #size-cells = <0>;
0138
0139 porta: gpio-port@0 {
0140 compatible = "snps,dw-apb-gpio-port";
0141 gpio-controller;
0142 #gpio-cells = <2>;
0143 ngpios = <32>;
0144 reg = <0>;
0145 interrupt-controller;
0146 #interrupt-cells = <2>;
0147 interrupts = <0>;
0148 };
0149 };
0150
0151 gpio1: gpio@800 {
0152 compatible = "snps,dw-apb-gpio";
0153 reg = <0x0800 0x400>;
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156
0157 portb: gpio-port@1 {
0158 compatible = "snps,dw-apb-gpio-port";
0159 gpio-controller;
0160 #gpio-cells = <2>;
0161 ngpios = <32>;
0162 reg = <0>;
0163 interrupt-controller;
0164 #interrupt-cells = <2>;
0165 interrupts = <1>;
0166 };
0167 };
0168
0169 gpio2: gpio@c00 {
0170 compatible = "snps,dw-apb-gpio";
0171 reg = <0x0c00 0x400>;
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174
0175 portc: gpio-port@2 {
0176 compatible = "snps,dw-apb-gpio-port";
0177 gpio-controller;
0178 #gpio-cells = <2>;
0179 ngpios = <32>;
0180 reg = <0>;
0181 interrupt-controller;
0182 #interrupt-cells = <2>;
0183 interrupts = <2>;
0184 };
0185 };
0186
0187 gpio3: gpio@1000 {
0188 compatible = "snps,dw-apb-gpio";
0189 reg = <0x1000 0x400>;
0190 #address-cells = <1>;
0191 #size-cells = <0>;
0192
0193 portd: gpio-port@3 {
0194 compatible = "snps,dw-apb-gpio-port";
0195 gpio-controller;
0196 #gpio-cells = <2>;
0197 ngpios = <32>;
0198 reg = <0>;
0199 interrupt-controller;
0200 #interrupt-cells = <2>;
0201 interrupts = <3>;
0202 };
0203 };
0204
0205 aic: interrupt-controller@3800 {
0206 compatible = "snps,dw-apb-ictl";
0207 reg = <0x3800 0x30>;
0208 interrupt-controller;
0209 #interrupt-cells = <1>;
0210 interrupt-parent = <&gic>;
0211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0212 };
0213 };
0214
0215 soc_pinctrl: pin-controller@ea8000 {
0216 compatible = "marvell,berlin4ct-soc-pinctrl";
0217 reg = <0xea8000 0x14>;
0218 };
0219
0220 avio_pinctrl: pin-controller@ea8400 {
0221 compatible = "marvell,berlin4ct-avio-pinctrl";
0222 reg = <0xea8400 0x8>;
0223 };
0224
0225 apb@fc0000 {
0226 compatible = "simple-bus";
0227 #address-cells = <1>;
0228 #size-cells = <1>;
0229 ranges = <0 0xfc0000 0x10000>;
0230 interrupt-parent = <&sic>;
0231
0232 sic: interrupt-controller@1000 {
0233 compatible = "snps,dw-apb-ictl";
0234 reg = <0x1000 0x30>;
0235 interrupt-controller;
0236 #interrupt-cells = <1>;
0237 interrupt-parent = <&gic>;
0238 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0239 };
0240
0241 wdt0: watchdog@3000 {
0242 compatible = "snps,dw-wdt";
0243 reg = <0x3000 0x100>;
0244 clocks = <&osc>;
0245 interrupts = <0>;
0246 };
0247
0248 wdt1: watchdog@4000 {
0249 compatible = "snps,dw-wdt";
0250 reg = <0x4000 0x100>;
0251 clocks = <&osc>;
0252 interrupts = <1>;
0253 };
0254
0255 wdt2: watchdog@5000 {
0256 compatible = "snps,dw-wdt";
0257 reg = <0x5000 0x100>;
0258 clocks = <&osc>;
0259 interrupts = <2>;
0260 };
0261
0262 sm_gpio0: gpio@8000 {
0263 compatible = "snps,dw-apb-gpio";
0264 reg = <0x8000 0x400>;
0265 #address-cells = <1>;
0266 #size-cells = <0>;
0267
0268 porte: gpio-port@4 {
0269 compatible = "snps,dw-apb-gpio-port";
0270 gpio-controller;
0271 #gpio-cells = <2>;
0272 ngpios = <32>;
0273 reg = <0>;
0274 };
0275 };
0276
0277 sm_gpio1: gpio@9000 {
0278 compatible = "snps,dw-apb-gpio";
0279 reg = <0x9000 0x400>;
0280 #address-cells = <1>;
0281 #size-cells = <0>;
0282
0283 portf: gpio-port@5 {
0284 compatible = "snps,dw-apb-gpio-port";
0285 gpio-controller;
0286 #gpio-cells = <2>;
0287 ngpios = <32>;
0288 reg = <0>;
0289 };
0290 };
0291
0292 uart0: uart@d000 {
0293 compatible = "snps,dw-apb-uart";
0294 reg = <0xd000 0x100>;
0295 interrupts = <8>;
0296 clocks = <&osc>;
0297 reg-shift = <2>;
0298 status = "disabled";
0299 pinctrl-0 = <&uart0_pmux>;
0300 pinctrl-names = "default";
0301 };
0302 };
0303
0304 system_pinctrl: pin-controller@fe2200 {
0305 compatible = "marvell,berlin4ct-system-pinctrl";
0306 reg = <0xfe2200 0xc>;
0307
0308 uart0_pmux: uart0-pmux {
0309 groups = "SM_URT0_TXD", "SM_URT0_RXD";
0310 function = "uart0";
0311 };
0312 };
0313 };
0314 };
