0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier PXs3 SoC
0004 //
0005 // Copyright (C) 2017 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/gpio/uniphier-gpio.h>
0010 #include <dt-bindings/thermal/thermal.h>
0011
0012 / {
0013 compatible = "socionext,uniphier-pxs3";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016 interrupt-parent = <&gic>;
0017
0018 cpus {
0019 #address-cells = <2>;
0020 #size-cells = <0>;
0021
0022 cpu-map {
0023 cluster0 {
0024 core0 {
0025 cpu = <&cpu0>;
0026 };
0027 core1 {
0028 cpu = <&cpu1>;
0029 };
0030 core2 {
0031 cpu = <&cpu2>;
0032 };
0033 core3 {
0034 cpu = <&cpu3>;
0035 };
0036 };
0037 };
0038
0039 cpu0: cpu@0 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a53";
0042 reg = <0 0x000>;
0043 clocks = <&sys_clk 33>;
0044 enable-method = "psci";
0045 operating-points-v2 = <&cluster0_opp>;
0046 #cooling-cells = <2>;
0047 };
0048
0049 cpu1: cpu@1 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a53";
0052 reg = <0 0x001>;
0053 clocks = <&sys_clk 33>;
0054 enable-method = "psci";
0055 operating-points-v2 = <&cluster0_opp>;
0056 #cooling-cells = <2>;
0057 };
0058
0059 cpu2: cpu@2 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a53";
0062 reg = <0 0x002>;
0063 clocks = <&sys_clk 33>;
0064 enable-method = "psci";
0065 operating-points-v2 = <&cluster0_opp>;
0066 #cooling-cells = <2>;
0067 };
0068
0069 cpu3: cpu@3 {
0070 device_type = "cpu";
0071 compatible = "arm,cortex-a53";
0072 reg = <0 0x003>;
0073 clocks = <&sys_clk 33>;
0074 enable-method = "psci";
0075 operating-points-v2 = <&cluster0_opp>;
0076 #cooling-cells = <2>;
0077 };
0078 };
0079
0080 cluster0_opp: opp-table {
0081 compatible = "operating-points-v2";
0082 opp-shared;
0083
0084 opp-250000000 {
0085 opp-hz = /bits/ 64 <250000000>;
0086 clock-latency-ns = <300>;
0087 };
0088 opp-325000000 {
0089 opp-hz = /bits/ 64 <325000000>;
0090 clock-latency-ns = <300>;
0091 };
0092 opp-500000000 {
0093 opp-hz = /bits/ 64 <500000000>;
0094 clock-latency-ns = <300>;
0095 };
0096 opp-650000000 {
0097 opp-hz = /bits/ 64 <650000000>;
0098 clock-latency-ns = <300>;
0099 };
0100 opp-666667000 {
0101 opp-hz = /bits/ 64 <666667000>;
0102 clock-latency-ns = <300>;
0103 };
0104 opp-866667000 {
0105 opp-hz = /bits/ 64 <866667000>;
0106 clock-latency-ns = <300>;
0107 };
0108 opp-1000000000 {
0109 opp-hz = /bits/ 64 <1000000000>;
0110 clock-latency-ns = <300>;
0111 };
0112 opp-1300000000 {
0113 opp-hz = /bits/ 64 <1300000000>;
0114 clock-latency-ns = <300>;
0115 };
0116 };
0117
0118 psci {
0119 compatible = "arm,psci-1.0";
0120 method = "smc";
0121 };
0122
0123 clocks {
0124 refclk: ref {
0125 compatible = "fixed-clock";
0126 #clock-cells = <0>;
0127 clock-frequency = <25000000>;
0128 };
0129 };
0130
0131 emmc_pwrseq: emmc-pwrseq {
0132 compatible = "mmc-pwrseq-emmc";
0133 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
0134 };
0135
0136 timer {
0137 compatible = "arm,armv8-timer";
0138 interrupts = <1 13 4>,
0139 <1 14 4>,
0140 <1 11 4>,
0141 <1 10 4>;
0142 };
0143
0144 thermal-zones {
0145 cpu-thermal {
0146 polling-delay-passive = <250>; /* 250ms */
0147 polling-delay = <1000>; /* 1000ms */
0148 thermal-sensors = <&pvtctl>;
0149
0150 trips {
0151 cpu_crit: cpu-crit {
0152 temperature = <110000>; /* 110C */
0153 hysteresis = <2000>;
0154 type = "critical";
0155 };
0156 cpu_alert: cpu-alert {
0157 temperature = <100000>; /* 100C */
0158 hysteresis = <2000>;
0159 type = "passive";
0160 };
0161 };
0162
0163 cooling-maps {
0164 map0 {
0165 trip = <&cpu_alert>;
0166 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0167 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0168 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0169 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0170 };
0171 };
0172 };
0173 };
0174
0175 reserved-memory {
0176 #address-cells = <2>;
0177 #size-cells = <2>;
0178 ranges;
0179
0180 secure-memory@81000000 {
0181 reg = <0x0 0x81000000 0x0 0x01000000>;
0182 no-map;
0183 };
0184 };
0185
0186 soc@0 {
0187 compatible = "simple-bus";
0188 #address-cells = <1>;
0189 #size-cells = <1>;
0190 ranges = <0 0 0 0xffffffff>;
0191
0192 spi0: spi@54006000 {
0193 compatible = "socionext,uniphier-scssi";
0194 status = "disabled";
0195 reg = <0x54006000 0x100>;
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198 interrupts = <0 39 4>;
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_spi0>;
0201 clocks = <&peri_clk 11>;
0202 resets = <&peri_rst 11>;
0203 };
0204
0205 spi1: spi@54006100 {
0206 compatible = "socionext,uniphier-scssi";
0207 status = "disabled";
0208 reg = <0x54006100 0x100>;
0209 #address-cells = <1>;
0210 #size-cells = <0>;
0211 interrupts = <0 216 4>;
0212 pinctrl-names = "default";
0213 pinctrl-0 = <&pinctrl_spi1>;
0214 clocks = <&peri_clk 12>;
0215 resets = <&peri_rst 12>;
0216 };
0217
0218 serial0: serial@54006800 {
0219 compatible = "socionext,uniphier-uart";
0220 status = "disabled";
0221 reg = <0x54006800 0x40>;
0222 interrupts = <0 33 4>;
0223 pinctrl-names = "default";
0224 pinctrl-0 = <&pinctrl_uart0>;
0225 clocks = <&peri_clk 0>;
0226 resets = <&peri_rst 0>;
0227 };
0228
0229 serial1: serial@54006900 {
0230 compatible = "socionext,uniphier-uart";
0231 status = "disabled";
0232 reg = <0x54006900 0x40>;
0233 interrupts = <0 35 4>;
0234 pinctrl-names = "default";
0235 pinctrl-0 = <&pinctrl_uart1>;
0236 clocks = <&peri_clk 1>;
0237 resets = <&peri_rst 1>;
0238 };
0239
0240 serial2: serial@54006a00 {
0241 compatible = "socionext,uniphier-uart";
0242 status = "disabled";
0243 reg = <0x54006a00 0x40>;
0244 interrupts = <0 37 4>;
0245 pinctrl-names = "default";
0246 pinctrl-0 = <&pinctrl_uart2>;
0247 clocks = <&peri_clk 2>;
0248 resets = <&peri_rst 2>;
0249 };
0250
0251 serial3: serial@54006b00 {
0252 compatible = "socionext,uniphier-uart";
0253 status = "disabled";
0254 reg = <0x54006b00 0x40>;
0255 interrupts = <0 177 4>;
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&pinctrl_uart3>;
0258 clocks = <&peri_clk 3>;
0259 resets = <&peri_rst 3>;
0260 };
0261
0262 gpio: gpio@55000000 {
0263 compatible = "socionext,uniphier-gpio";
0264 reg = <0x55000000 0x200>;
0265 interrupt-parent = <&aidet>;
0266 interrupt-controller;
0267 #interrupt-cells = <2>;
0268 gpio-controller;
0269 #gpio-cells = <2>;
0270 gpio-ranges = <&pinctrl 0 0 0>,
0271 <&pinctrl 104 0 0>,
0272 <&pinctrl 168 0 0>;
0273 gpio-ranges-group-names = "gpio_range0",
0274 "gpio_range1",
0275 "gpio_range2";
0276 ngpios = <286>;
0277 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
0278 <21 217 3>;
0279 };
0280
0281 i2c0: i2c@58780000 {
0282 compatible = "socionext,uniphier-fi2c";
0283 status = "disabled";
0284 reg = <0x58780000 0x80>;
0285 #address-cells = <1>;
0286 #size-cells = <0>;
0287 interrupts = <0 41 4>;
0288 pinctrl-names = "default";
0289 pinctrl-0 = <&pinctrl_i2c0>;
0290 clocks = <&peri_clk 4>;
0291 resets = <&peri_rst 4>;
0292 clock-frequency = <100000>;
0293 };
0294
0295 i2c1: i2c@58781000 {
0296 compatible = "socionext,uniphier-fi2c";
0297 status = "disabled";
0298 reg = <0x58781000 0x80>;
0299 #address-cells = <1>;
0300 #size-cells = <0>;
0301 interrupts = <0 42 4>;
0302 pinctrl-names = "default";
0303 pinctrl-0 = <&pinctrl_i2c1>;
0304 clocks = <&peri_clk 5>;
0305 resets = <&peri_rst 5>;
0306 clock-frequency = <100000>;
0307 };
0308
0309 i2c2: i2c@58782000 {
0310 compatible = "socionext,uniphier-fi2c";
0311 status = "disabled";
0312 reg = <0x58782000 0x80>;
0313 #address-cells = <1>;
0314 #size-cells = <0>;
0315 interrupts = <0 43 4>;
0316 pinctrl-names = "default";
0317 pinctrl-0 = <&pinctrl_i2c2>;
0318 clocks = <&peri_clk 6>;
0319 resets = <&peri_rst 6>;
0320 clock-frequency = <100000>;
0321 };
0322
0323 i2c3: i2c@58783000 {
0324 compatible = "socionext,uniphier-fi2c";
0325 status = "disabled";
0326 reg = <0x58783000 0x80>;
0327 #address-cells = <1>;
0328 #size-cells = <0>;
0329 interrupts = <0 44 4>;
0330 pinctrl-names = "default";
0331 pinctrl-0 = <&pinctrl_i2c3>;
0332 clocks = <&peri_clk 7>;
0333 resets = <&peri_rst 7>;
0334 clock-frequency = <100000>;
0335 };
0336
0337 /* chip-internal connection for HDMI */
0338 i2c6: i2c@58786000 {
0339 compatible = "socionext,uniphier-fi2c";
0340 reg = <0x58786000 0x80>;
0341 #address-cells = <1>;
0342 #size-cells = <0>;
0343 interrupts = <0 26 4>;
0344 clocks = <&peri_clk 10>;
0345 resets = <&peri_rst 10>;
0346 clock-frequency = <400000>;
0347 };
0348
0349 system_bus: system-bus@58c00000 {
0350 compatible = "socionext,uniphier-system-bus";
0351 status = "disabled";
0352 reg = <0x58c00000 0x400>;
0353 #address-cells = <2>;
0354 #size-cells = <1>;
0355 pinctrl-names = "default";
0356 pinctrl-0 = <&pinctrl_system_bus>;
0357 };
0358
0359 smpctrl@59801000 {
0360 compatible = "socionext,uniphier-smpctrl";
0361 reg = <0x59801000 0x400>;
0362 };
0363
0364 sdctrl@59810000 {
0365 compatible = "socionext,uniphier-pxs3-sdctrl",
0366 "simple-mfd", "syscon";
0367 reg = <0x59810000 0x400>;
0368
0369 sd_clk: clock {
0370 compatible = "socionext,uniphier-pxs3-sd-clock";
0371 #clock-cells = <1>;
0372 };
0373
0374 sd_rst: reset {
0375 compatible = "socionext,uniphier-pxs3-sd-reset";
0376 #reset-cells = <1>;
0377 };
0378 };
0379
0380 perictrl@59820000 {
0381 compatible = "socionext,uniphier-pxs3-perictrl",
0382 "simple-mfd", "syscon";
0383 reg = <0x59820000 0x200>;
0384
0385 peri_clk: clock {
0386 compatible = "socionext,uniphier-pxs3-peri-clock";
0387 #clock-cells = <1>;
0388 };
0389
0390 peri_rst: reset {
0391 compatible = "socionext,uniphier-pxs3-peri-reset";
0392 #reset-cells = <1>;
0393 };
0394 };
0395
0396 emmc: mmc@5a000000 {
0397 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
0398 reg = <0x5a000000 0x400>;
0399 interrupts = <0 78 4>;
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&pinctrl_emmc>;
0402 clocks = <&sys_clk 4>;
0403 resets = <&sys_rst 4>;
0404 bus-width = <8>;
0405 mmc-ddr-1_8v;
0406 mmc-hs200-1_8v;
0407 mmc-pwrseq = <&emmc_pwrseq>;
0408 cdns,phy-input-delay-legacy = <9>;
0409 cdns,phy-input-delay-mmc-highspeed = <2>;
0410 cdns,phy-input-delay-mmc-ddr = <3>;
0411 cdns,phy-dll-delay-sdclk = <21>;
0412 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
0413 };
0414
0415 sd: mmc@5a400000 {
0416 compatible = "socionext,uniphier-sd-v3.1.1";
0417 status = "disabled";
0418 reg = <0x5a400000 0x800>;
0419 interrupts = <0 76 4>;
0420 pinctrl-names = "default", "uhs";
0421 pinctrl-0 = <&pinctrl_sd>;
0422 pinctrl-1 = <&pinctrl_sd_uhs>;
0423 clocks = <&sd_clk 0>;
0424 reset-names = "host";
0425 resets = <&sd_rst 0>;
0426 bus-width = <4>;
0427 cap-sd-highspeed;
0428 sd-uhs-sdr12;
0429 sd-uhs-sdr25;
0430 sd-uhs-sdr50;
0431 };
0432
0433 soc_glue: soc-glue@5f800000 {
0434 compatible = "socionext,uniphier-pxs3-soc-glue",
0435 "simple-mfd", "syscon";
0436 reg = <0x5f800000 0x2000>;
0437
0438 pinctrl: pinctrl {
0439 compatible = "socionext,uniphier-pxs3-pinctrl";
0440 };
0441 };
0442
0443 soc-glue@5f900000 {
0444 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
0445 "simple-mfd";
0446 #address-cells = <1>;
0447 #size-cells = <1>;
0448 ranges = <0 0x5f900000 0x2000>;
0449
0450 efuse@100 {
0451 compatible = "socionext,uniphier-efuse";
0452 reg = <0x100 0x28>;
0453 };
0454
0455 efuse@200 {
0456 compatible = "socionext,uniphier-efuse";
0457 reg = <0x200 0x68>;
0458 #address-cells = <1>;
0459 #size-cells = <1>;
0460
0461 /* USB cells */
0462 usb_rterm0: trim@54,4 {
0463 reg = <0x54 1>;
0464 bits = <4 2>;
0465 };
0466 usb_rterm1: trim@55,4 {
0467 reg = <0x55 1>;
0468 bits = <4 2>;
0469 };
0470 usb_rterm2: trim@58,4 {
0471 reg = <0x58 1>;
0472 bits = <4 2>;
0473 };
0474 usb_rterm3: trim@59,4 {
0475 reg = <0x59 1>;
0476 bits = <4 2>;
0477 };
0478 usb_sel_t0: trim@54,0 {
0479 reg = <0x54 1>;
0480 bits = <0 4>;
0481 };
0482 usb_sel_t1: trim@55,0 {
0483 reg = <0x55 1>;
0484 bits = <0 4>;
0485 };
0486 usb_sel_t2: trim@58,0 {
0487 reg = <0x58 1>;
0488 bits = <0 4>;
0489 };
0490 usb_sel_t3: trim@59,0 {
0491 reg = <0x59 1>;
0492 bits = <0 4>;
0493 };
0494 usb_hs_i0: trim@56,0 {
0495 reg = <0x56 1>;
0496 bits = <0 4>;
0497 };
0498 usb_hs_i2: trim@5a,0 {
0499 reg = <0x5a 1>;
0500 bits = <0 4>;
0501 };
0502 };
0503 };
0504
0505 xdmac: dma-controller@5fc10000 {
0506 compatible = "socionext,uniphier-xdmac";
0507 reg = <0x5fc10000 0x5300>;
0508 interrupts = <0 188 4>;
0509 dma-channels = <16>;
0510 #dma-cells = <2>;
0511 };
0512
0513 aidet: interrupt-controller@5fc20000 {
0514 compatible = "socionext,uniphier-pxs3-aidet";
0515 reg = <0x5fc20000 0x200>;
0516 interrupt-controller;
0517 #interrupt-cells = <2>;
0518 };
0519
0520 gic: interrupt-controller@5fe00000 {
0521 compatible = "arm,gic-v3";
0522 reg = <0x5fe00000 0x10000>, /* GICD */
0523 <0x5fe80000 0x80000>; /* GICR */
0524 interrupt-controller;
0525 #interrupt-cells = <3>;
0526 interrupts = <1 9 4>;
0527 };
0528
0529 sysctrl@61840000 {
0530 compatible = "socionext,uniphier-pxs3-sysctrl",
0531 "simple-mfd", "syscon";
0532 reg = <0x61840000 0x10000>;
0533
0534 sys_clk: clock {
0535 compatible = "socionext,uniphier-pxs3-clock";
0536 #clock-cells = <1>;
0537 };
0538
0539 sys_rst: reset {
0540 compatible = "socionext,uniphier-pxs3-reset";
0541 #reset-cells = <1>;
0542 };
0543
0544 watchdog {
0545 compatible = "socionext,uniphier-wdt";
0546 };
0547
0548 pvtctl: pvtctl {
0549 compatible = "socionext,uniphier-pxs3-thermal";
0550 interrupts = <0 3 4>;
0551 #thermal-sensor-cells = <0>;
0552 socionext,tmod-calibration = <0x0f22 0x68ee>;
0553 };
0554 };
0555
0556 eth0: ethernet@65000000 {
0557 compatible = "socionext,uniphier-pxs3-ave4";
0558 status = "disabled";
0559 reg = <0x65000000 0x8500>;
0560 interrupts = <0 66 4>;
0561 pinctrl-names = "default";
0562 pinctrl-0 = <&pinctrl_ether_rgmii>;
0563 clock-names = "ether";
0564 clocks = <&sys_clk 6>;
0565 reset-names = "ether";
0566 resets = <&sys_rst 6>;
0567 phy-mode = "rgmii-id";
0568 local-mac-address = [00 00 00 00 00 00];
0569 socionext,syscon-phy-mode = <&soc_glue 0>;
0570
0571 mdio0: mdio {
0572 #address-cells = <1>;
0573 #size-cells = <0>;
0574 };
0575 };
0576
0577 eth1: ethernet@65200000 {
0578 compatible = "socionext,uniphier-pxs3-ave4";
0579 status = "disabled";
0580 reg = <0x65200000 0x8500>;
0581 interrupts = <0 67 4>;
0582 pinctrl-names = "default";
0583 pinctrl-0 = <&pinctrl_ether1_rgmii>;
0584 clock-names = "ether";
0585 clocks = <&sys_clk 7>;
0586 reset-names = "ether";
0587 resets = <&sys_rst 7>;
0588 phy-mode = "rgmii-id";
0589 local-mac-address = [00 00 00 00 00 00];
0590 socionext,syscon-phy-mode = <&soc_glue 1>;
0591
0592 mdio1: mdio {
0593 #address-cells = <1>;
0594 #size-cells = <0>;
0595 };
0596 };
0597
0598 usb0: usb@65a00000 {
0599 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0600 status = "disabled";
0601 reg = <0x65a00000 0xcd00>;
0602 interrupt-names = "dwc_usb3";
0603 interrupts = <0 134 4>;
0604 pinctrl-names = "default";
0605 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
0606 clock-names = "ref", "bus_early", "suspend";
0607 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
0608 resets = <&usb0_rst 15>;
0609 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
0610 <&usb0_ssphy0>, <&usb0_ssphy1>;
0611 dr_mode = "host";
0612 };
0613
0614 usb-glue@65b00000 {
0615 compatible = "socionext,uniphier-pxs3-dwc3-glue",
0616 "simple-mfd";
0617 #address-cells = <1>;
0618 #size-cells = <1>;
0619 ranges = <0 0x65b00000 0x400>;
0620
0621 usb0_rst: reset@0 {
0622 compatible = "socionext,uniphier-pxs3-usb3-reset";
0623 reg = <0x0 0x4>;
0624 #reset-cells = <1>;
0625 clock-names = "link";
0626 clocks = <&sys_clk 12>;
0627 reset-names = "link";
0628 resets = <&sys_rst 12>;
0629 };
0630
0631 usb0_vbus0: regulator@100 {
0632 compatible = "socionext,uniphier-pxs3-usb3-regulator";
0633 reg = <0x100 0x10>;
0634 clock-names = "link";
0635 clocks = <&sys_clk 12>;
0636 reset-names = "link";
0637 resets = <&sys_rst 12>;
0638 };
0639
0640 usb0_vbus1: regulator@110 {
0641 compatible = "socionext,uniphier-pxs3-usb3-regulator";
0642 reg = <0x110 0x10>;
0643 clock-names = "link";
0644 clocks = <&sys_clk 12>;
0645 reset-names = "link";
0646 resets = <&sys_rst 12>;
0647 };
0648
0649 usb0_hsphy0: hs-phy@200 {
0650 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
0651 reg = <0x200 0x10>;
0652 #phy-cells = <0>;
0653 clock-names = "link", "phy";
0654 clocks = <&sys_clk 12>, <&sys_clk 16>;
0655 reset-names = "link", "phy";
0656 resets = <&sys_rst 12>, <&sys_rst 16>;
0657 vbus-supply = <&usb0_vbus0>;
0658 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0659 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
0660 <&usb_hs_i0>;
0661 };
0662
0663 usb0_hsphy1: hs-phy@210 {
0664 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
0665 reg = <0x210 0x10>;
0666 #phy-cells = <0>;
0667 clock-names = "link", "phy";
0668 clocks = <&sys_clk 12>, <&sys_clk 16>;
0669 reset-names = "link", "phy";
0670 resets = <&sys_rst 12>, <&sys_rst 16>;
0671 vbus-supply = <&usb0_vbus1>;
0672 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0673 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
0674 <&usb_hs_i0>;
0675 };
0676
0677 usb0_ssphy0: ss-phy@300 {
0678 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
0679 reg = <0x300 0x10>;
0680 #phy-cells = <0>;
0681 clock-names = "link", "phy";
0682 clocks = <&sys_clk 12>, <&sys_clk 17>;
0683 reset-names = "link", "phy";
0684 resets = <&sys_rst 12>, <&sys_rst 17>;
0685 vbus-supply = <&usb0_vbus0>;
0686 };
0687
0688 usb0_ssphy1: ss-phy@310 {
0689 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
0690 reg = <0x310 0x10>;
0691 #phy-cells = <0>;
0692 clock-names = "link", "phy";
0693 clocks = <&sys_clk 12>, <&sys_clk 18>;
0694 reset-names = "link", "phy";
0695 resets = <&sys_rst 12>, <&sys_rst 18>;
0696 vbus-supply = <&usb0_vbus1>;
0697 };
0698 };
0699
0700 usb1: usb@65c00000 {
0701 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0702 status = "disabled";
0703 reg = <0x65c00000 0xcd00>;
0704 interrupt-names = "dwc_usb3";
0705 interrupts = <0 137 4>;
0706 pinctrl-names = "default";
0707 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
0708 clock-names = "ref", "bus_early", "suspend";
0709 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
0710 resets = <&usb1_rst 15>;
0711 phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
0712 <&usb1_ssphy0>;
0713 dr_mode = "host";
0714 };
0715
0716 usb-glue@65d00000 {
0717 compatible = "socionext,uniphier-pxs3-dwc3-glue",
0718 "simple-mfd";
0719 #address-cells = <1>;
0720 #size-cells = <1>;
0721 ranges = <0 0x65d00000 0x400>;
0722
0723 usb1_rst: reset@0 {
0724 compatible = "socionext,uniphier-pxs3-usb3-reset";
0725 reg = <0x0 0x4>;
0726 #reset-cells = <1>;
0727 clock-names = "link";
0728 clocks = <&sys_clk 13>;
0729 reset-names = "link";
0730 resets = <&sys_rst 13>;
0731 };
0732
0733 usb1_vbus0: regulator@100 {
0734 compatible = "socionext,uniphier-pxs3-usb3-regulator";
0735 reg = <0x100 0x10>;
0736 clock-names = "link";
0737 clocks = <&sys_clk 13>;
0738 reset-names = "link";
0739 resets = <&sys_rst 13>;
0740 };
0741
0742 usb1_vbus1: regulator@110 {
0743 compatible = "socionext,uniphier-pxs3-usb3-regulator";
0744 reg = <0x110 0x10>;
0745 clock-names = "link";
0746 clocks = <&sys_clk 13>;
0747 reset-names = "link";
0748 resets = <&sys_rst 13>;
0749 };
0750
0751 usb1_hsphy0: hs-phy@200 {
0752 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
0753 reg = <0x200 0x10>;
0754 #phy-cells = <0>;
0755 clock-names = "link", "phy", "phy-ext";
0756 clocks = <&sys_clk 13>, <&sys_clk 20>,
0757 <&sys_clk 14>;
0758 reset-names = "link", "phy";
0759 resets = <&sys_rst 13>, <&sys_rst 20>;
0760 vbus-supply = <&usb1_vbus0>;
0761 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0762 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
0763 <&usb_hs_i2>;
0764 };
0765
0766 usb1_hsphy1: hs-phy@210 {
0767 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
0768 reg = <0x210 0x10>;
0769 #phy-cells = <0>;
0770 clock-names = "link", "phy", "phy-ext";
0771 clocks = <&sys_clk 13>, <&sys_clk 20>,
0772 <&sys_clk 14>;
0773 reset-names = "link", "phy";
0774 resets = <&sys_rst 13>, <&sys_rst 20>;
0775 vbus-supply = <&usb1_vbus1>;
0776 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0777 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
0778 <&usb_hs_i2>;
0779 };
0780
0781 usb1_ssphy0: ss-phy@300 {
0782 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
0783 reg = <0x300 0x10>;
0784 #phy-cells = <0>;
0785 clock-names = "link", "phy", "phy-ext";
0786 clocks = <&sys_clk 13>, <&sys_clk 21>,
0787 <&sys_clk 14>;
0788 reset-names = "link", "phy";
0789 resets = <&sys_rst 13>, <&sys_rst 21>;
0790 vbus-supply = <&usb1_vbus0>;
0791 };
0792 };
0793
0794 pcie: pcie@66000000 {
0795 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
0796 status = "disabled";
0797 reg-names = "dbi", "link", "config";
0798 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
0799 <0x2fff0000 0x10000>;
0800 #address-cells = <3>;
0801 #size-cells = <2>;
0802 clocks = <&sys_clk 24>;
0803 resets = <&sys_rst 24>;
0804 num-lanes = <1>;
0805 num-viewport = <1>;
0806 bus-range = <0x0 0xff>;
0807 device_type = "pci";
0808 ranges =
0809 /* downstream I/O */
0810 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
0811 /* non-prefetchable memory */
0812 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
0813 #interrupt-cells = <1>;
0814 interrupt-names = "dma", "msi";
0815 interrupts = <0 224 4>, <0 225 4>;
0816 interrupt-map-mask = <0 0 0 7>;
0817 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
0818 <0 0 0 2 &pcie_intc 1>, /* INTB */
0819 <0 0 0 3 &pcie_intc 2>, /* INTC */
0820 <0 0 0 4 &pcie_intc 3>; /* INTD */
0821 phy-names = "pcie-phy";
0822 phys = <&pcie_phy>;
0823
0824 pcie_intc: legacy-interrupt-controller {
0825 interrupt-controller;
0826 #interrupt-cells = <1>;
0827 interrupt-parent = <&gic>;
0828 interrupts = <0 226 4>;
0829 };
0830 };
0831
0832 pcie_phy: phy@66038000 {
0833 compatible = "socionext,uniphier-pxs3-pcie-phy";
0834 reg = <0x66038000 0x4000>;
0835 #phy-cells = <0>;
0836 clock-names = "link";
0837 clocks = <&sys_clk 24>;
0838 reset-names = "link";
0839 resets = <&sys_rst 24>;
0840 socionext,syscon = <&soc_glue>;
0841 };
0842
0843 nand: nand-controller@68000000 {
0844 compatible = "socionext,uniphier-denali-nand-v5b";
0845 status = "disabled";
0846 reg-names = "nand_data", "denali_reg";
0847 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0848 #address-cells = <1>;
0849 #size-cells = <0>;
0850 interrupts = <0 65 4>;
0851 pinctrl-names = "default";
0852 pinctrl-0 = <&pinctrl_nand>;
0853 clock-names = "nand", "nand_x", "ecc";
0854 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0855 reset-names = "nand", "reg";
0856 resets = <&sys_rst 2>, <&sys_rst 2>;
0857 };
0858 };
0859 };
0860
0861 #include "uniphier-pinctrl.dtsi"
