0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
0004 * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
0005 */
0006
0007 /dts-v1/;
0008 #include "rk3399-roc-pc.dtsi"
0009
0010 / {
0011 model = "Firefly ROC-RK3399-PC Mezzanine Board";
0012 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
0013
0014 aliases {
0015 mmc2 = &sdio0;
0016 };
0017
0018 /* MP8009 PoE PD */
0019 poe_12v: poe-12v {
0020 compatible = "regulator-fixed";
0021 regulator-name = "poe_12v";
0022 regulator-always-on;
0023 regulator-boot-on;
0024 regulator-min-microvolt = <12000000>;
0025 regulator-max-microvolt = <12000000>;
0026 };
0027
0028 vcc3v3_ngff: vcc3v3-ngff {
0029 compatible = "regulator-fixed";
0030 regulator-name = "vcc3v3_ngff";
0031 enable-active-high;
0032 gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&vcc3v3_ngff_en>;
0035 regulator-always-on;
0036 regulator-boot-on;
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 vin-supply = <&sys_12v>;
0040 };
0041
0042 vcc3v3_pcie: vcc3v3-pcie {
0043 compatible = "regulator-fixed";
0044 regulator-name = "vcc3v3_pcie";
0045 enable-active-high;
0046 gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
0047 pinctrl-names = "default";
0048 pinctrl-0 = <&vcc3v3_pcie_en>;
0049 regulator-min-microvolt = <3300000>;
0050 regulator-max-microvolt = <3300000>;
0051 vin-supply = <&sys_12v>;
0052 };
0053 };
0054
0055 &sys_12v {
0056 vin-supply = <&poe_12v>;
0057 };
0058
0059 &pcie_phy {
0060 status = "okay";
0061 };
0062
0063 &pcie0 {
0064 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
0065 num-lanes = <4>;
0066 pinctrl-names = "default";
0067 pinctrl-0 = <&pcie_perst>;
0068 vpcie3v3-supply = <&vcc3v3_pcie>;
0069 vpcie1v8-supply = <&vcc1v8_pmu>;
0070 vpcie0v9-supply = <&vcca_0v9>;
0071 status = "okay";
0072 };
0073
0074 &pinctrl {
0075 ngff {
0076 vcc3v3_ngff_en: vcc3v3-ngff-en {
0077 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
0078 };
0079 };
0080
0081 pcie {
0082 vcc3v3_pcie_en: vcc3v3-pcie-en {
0083 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
0084 };
0085
0086 pcie_perst: pcie-perst {
0087 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
0088 };
0089 };
0090 };
0091
0092 &sdio0 {
0093 bus-width = <4>;
0094 cap-sd-highspeed;
0095 cap-sdio-irq;
0096 keep-power-in-suspend;
0097 mmc-pwrseq = <&sdio_pwrseq>;
0098 non-removable;
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
0101 sd-uhs-sdr104;
0102 vmmc-supply = <&vcc3v3_ngff>;
0103 vqmmc-supply = <&vcc_1v8>;
0104 status = "okay";
0105 };
0106
0107 &uart0 {
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0110 status = "okay";
0111 };
