0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
0004 */
0005
0006 / {
0007 cluster0_opp: opp-table-0 {
0008 compatible = "operating-points-v2";
0009 opp-shared;
0010
0011 opp00 {
0012 opp-hz = /bits/ 64 <408000000>;
0013 opp-microvolt = <800000>;
0014 clock-latency-ns = <40000>;
0015 };
0016 opp01 {
0017 opp-hz = /bits/ 64 <600000000>;
0018 opp-microvolt = <825000>;
0019 };
0020 opp02 {
0021 opp-hz = /bits/ 64 <816000000>;
0022 opp-microvolt = <850000>;
0023 };
0024 opp03 {
0025 opp-hz = /bits/ 64 <1008000000>;
0026 opp-microvolt = <900000>;
0027 };
0028 opp04 {
0029 opp-hz = /bits/ 64 <1200000000>;
0030 opp-microvolt = <975000>;
0031 };
0032 opp05 {
0033 opp-hz = /bits/ 64 <1416000000>;
0034 opp-microvolt = <1100000>;
0035 };
0036 opp06 {
0037 opp-hz = /bits/ 64 <1512000000>;
0038 opp-microvolt = <1150000>;
0039 };
0040 };
0041
0042 cluster1_opp: opp-table-1 {
0043 compatible = "operating-points-v2";
0044 opp-shared;
0045
0046 opp00 {
0047 opp-hz = /bits/ 64 <408000000>;
0048 opp-microvolt = <800000>;
0049 clock-latency-ns = <40000>;
0050 };
0051 opp01 {
0052 opp-hz = /bits/ 64 <600000000>;
0053 opp-microvolt = <800000>;
0054 };
0055 opp02 {
0056 opp-hz = /bits/ 64 <816000000>;
0057 opp-microvolt = <825000>;
0058 };
0059 opp03 {
0060 opp-hz = /bits/ 64 <1008000000>;
0061 opp-microvolt = <850000>;
0062 };
0063 opp04 {
0064 opp-hz = /bits/ 64 <1200000000>;
0065 opp-microvolt = <900000>;
0066 };
0067 opp05 {
0068 opp-hz = /bits/ 64 <1416000000>;
0069 opp-microvolt = <975000>;
0070 };
0071 opp06 {
0072 opp-hz = /bits/ 64 <1608000000>;
0073 opp-microvolt = <1050000>;
0074 };
0075 opp07 {
0076 opp-hz = /bits/ 64 <1800000000>;
0077 opp-microvolt = <1150000>;
0078 };
0079 opp08 {
0080 opp-hz = /bits/ 64 <2016000000>;
0081 opp-microvolt = <1250000>;
0082 };
0083 };
0084
0085 gpu_opp_table: opp-table-2 {
0086 compatible = "operating-points-v2";
0087
0088 opp00 {
0089 opp-hz = /bits/ 64 <200000000>;
0090 opp-microvolt = <800000>;
0091 };
0092 opp01 {
0093 opp-hz = /bits/ 64 <297000000>;
0094 opp-microvolt = <800000>;
0095 };
0096 opp02 {
0097 opp-hz = /bits/ 64 <400000000>;
0098 opp-microvolt = <825000>;
0099 };
0100 opp03 {
0101 opp-hz = /bits/ 64 <500000000>;
0102 opp-microvolt = <850000>;
0103 };
0104 opp04 {
0105 opp-hz = /bits/ 64 <600000000>;
0106 opp-microvolt = <925000>;
0107 };
0108 opp05 {
0109 opp-hz = /bits/ 64 <800000000>;
0110 opp-microvolt = <1075000>;
0111 };
0112 };
0113
0114 dmc_opp_table: dmc_opp_table {
0115 compatible = "operating-points-v2";
0116
0117 opp00 {
0118 opp-hz = /bits/ 64 <400000000>;
0119 opp-microvolt = <900000>;
0120 };
0121 opp01 {
0122 opp-hz = /bits/ 64 <666000000>;
0123 opp-microvolt = <900000>;
0124 };
0125 opp02 {
0126 opp-hz = /bits/ 64 <800000000>;
0127 opp-microvolt = <900000>;
0128 };
0129 opp03 {
0130 opp-hz = /bits/ 64 <928000000>;
0131 opp-microvolt = <925000>;
0132 };
0133 };
0134 };
0135
0136 &cpu_l0 {
0137 operating-points-v2 = <&cluster0_opp>;
0138 };
0139
0140 &cpu_l1 {
0141 operating-points-v2 = <&cluster0_opp>;
0142 };
0143
0144 &cpu_l2 {
0145 operating-points-v2 = <&cluster0_opp>;
0146 };
0147
0148 &cpu_l3 {
0149 operating-points-v2 = <&cluster0_opp>;
0150 };
0151
0152 &cpu_b0 {
0153 operating-points-v2 = <&cluster1_opp>;
0154 };
0155
0156 &cpu_b1 {
0157 operating-points-v2 = <&cluster1_opp>;
0158 };
0159
0160 &dmc {
0161 operating-points-v2 = <&dmc_opp_table>;
0162 };
0163
0164 &gpu {
0165 operating-points-v2 = <&gpu_opp_table>;
0166 };
