0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/G2LC SMARC EVK parts
0004 *
0005 * Copyright (C) 2022 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
0010
0011 /*
0012 * DIP-Switch SW1 setting on SoM
0013 * 1 : High; 0: Low
0014 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
0015 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
0016 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
0017 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
0018 * Please change below macros according to SW1 setting
0019 */
0020
0021 #define SW_SD0_DEV_SEL 1
0022
0023 #define SW_SCIF_CAN 0
0024 #if (SW_SCIF_CAN)
0025 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
0026 #define SW_RSPI_CAN 0
0027 #else
0028 /* Please set SW_RSPI_CAN. Default value is 1 */
0029 #define SW_RSPI_CAN 1
0030 #endif
0031
0032 #if (SW_SCIF_CAN && SW_RSPI_CAN)
0033 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
0034 #endif
0035
0036 #include "rzg2lc-smarc-som.dtsi"
0037 #include "rzg2lc-smarc-pinfunction.dtsi"
0038 #include "rz-smarc-common.dtsi"
0039
0040 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
0041 #define PMOD1_SER0 1
0042
0043 / {
0044 aliases {
0045 serial1 = &scif1;
0046 i2c2 = &i2c2;
0047 };
0048 };
0049
0050 #if (SW_SCIF_CAN || SW_RSPI_CAN)
0051 &canfd {
0052 pinctrl-0 = <&can1_pins>;
0053 /delete-node/ channel@0;
0054 };
0055 #else
0056 &canfd {
0057 /delete-property/ pinctrl-0;
0058 /delete-property/ pinctrl-names;
0059 status = "disabled";
0060 };
0061 #endif
0062
0063 &cpu_dai {
0064 sound-dai = <&ssi0>;
0065 };
0066
0067 &i2c2 {
0068 pinctrl-0 = <&i2c2_pins>;
0069 pinctrl-names = "default";
0070 clock-frequency = <400000>;
0071
0072 status = "okay";
0073
0074 wm8978: codec@1a {
0075 compatible = "wlf,wm8978";
0076 #sound-dai-cells = <0>;
0077 reg = <0x1a>;
0078 };
0079 };
0080
0081 /*
0082 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
0083 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
0084 * SW2 should be at position 2->3 so that SER0_TX line is activated
0085 * SW3 should be at position 2->3 so that SER0_RX line is activated
0086 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
0087 */
0088 #if (!SW_SCIF_CAN && PMOD1_SER0)
0089 &scif1 {
0090 pinctrl-0 = <&scif1_pins>;
0091 pinctrl-names = "default";
0092
0093 uart-has-rtscts;
0094 status = "okay";
0095 };
0096 #endif
0097
0098 &ssi0 {
0099 pinctrl-0 = <&ssi0_pins>;
0100 pinctrl-names = "default";
0101
0102 status = "okay";
0103 };
0104
0105 #if (SW_RSPI_CAN)
0106 &spi1 {
0107 /delete-property/ pinctrl-0;
0108 /delete-property/ pinctrl-names;
0109 status = "disabled";
0110 };
0111 #endif
0112
0113 &vccq_sdhi1 {
0114 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
0115 };
