0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 /*
0003 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
0004 *
0005 * Copyright (C) 2021 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
0010
0011 /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
0012 #define PMOD1_SER0 1
0013
0014 / {
0015 aliases {
0016 serial1 = &scif2;
0017 i2c3 = &i2c3;
0018 };
0019 };
0020
0021 &cpu_dai {
0022 sound-dai = <&ssi0>;
0023 };
0024
0025 &i2c3 {
0026 pinctrl-0 = <&i2c3_pins>;
0027 pinctrl-names = "default";
0028 clock-frequency = <400000>;
0029
0030 status = "okay";
0031
0032 wm8978: codec@1a {
0033 compatible = "wlf,wm8978";
0034 #sound-dai-cells = <0>;
0035 reg = <0x1a>;
0036 };
0037 };
0038
0039 /*
0040 * To enable SCIF2 (SER0) on PMOD1 (CN7)
0041 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
0042 * SW2 should be at position 2->3 so that SER0_TX line is activated
0043 * SW3 should be at position 2->3 so that SER0_RX line is activated
0044 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
0045 */
0046 #if PMOD1_SER0
0047 &scif2 {
0048 pinctrl-0 = <&scif2_pins>;
0049 pinctrl-names = "default";
0050
0051 uart-has-rtscts;
0052 status = "okay";
0053 };
0054 #endif
0055
0056 &ssi0 {
0057 pinctrl-0 = <&ssi0_pins>;
0058 pinctrl-names = "default";
0059
0060 status = "okay";
0061 };
0062
0063 &vccq_sdhi1 {
0064 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
0065 };
