0001 // SPDX-License-Identifier: (GPL-2.0 or MIT)
0002 /*
0003 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
0004 *
0005 * Copyright (C) 2021 Renesas Electronics Corp.
0006 */
0007
0008 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/power/r8a779f0-sysc.h>
0011
0012 / {
0013 compatible = "renesas,r8a779f0";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu-map {
0022 cluster0 {
0023 core0 {
0024 cpu = <&a55_0>;
0025 };
0026 core1 {
0027 cpu = <&a55_1>;
0028 };
0029 };
0030
0031 cluster1 {
0032 core0 {
0033 cpu = <&a55_2>;
0034 };
0035 core1 {
0036 cpu = <&a55_3>;
0037 };
0038 };
0039
0040 cluster2 {
0041 core0 {
0042 cpu = <&a55_4>;
0043 };
0044 core1 {
0045 cpu = <&a55_5>;
0046 };
0047 };
0048
0049 cluster3 {
0050 core0 {
0051 cpu = <&a55_6>;
0052 };
0053 core1 {
0054 cpu = <&a55_7>;
0055 };
0056 };
0057 };
0058
0059 a55_0: cpu@0 {
0060 compatible = "arm,cortex-a55";
0061 reg = <0>;
0062 device_type = "cpu";
0063 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
0064 next-level-cache = <&L3_CA55_0>;
0065 enable-method = "psci";
0066 cpu-idle-states = <&CPU_SLEEP_0>;
0067 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
0068 };
0069
0070 a55_1: cpu@100 {
0071 compatible = "arm,cortex-a55";
0072 reg = <0x100>;
0073 device_type = "cpu";
0074 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
0075 next-level-cache = <&L3_CA55_0>;
0076 enable-method = "psci";
0077 cpu-idle-states = <&CPU_SLEEP_0>;
0078 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
0079 };
0080
0081 a55_2: cpu@10000 {
0082 compatible = "arm,cortex-a55";
0083 reg = <0x10000>;
0084 device_type = "cpu";
0085 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
0086 next-level-cache = <&L3_CA55_1>;
0087 enable-method = "psci";
0088 cpu-idle-states = <&CPU_SLEEP_0>;
0089 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
0090 };
0091
0092 a55_3: cpu@10100 {
0093 compatible = "arm,cortex-a55";
0094 reg = <0x10100>;
0095 device_type = "cpu";
0096 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
0097 next-level-cache = <&L3_CA55_1>;
0098 enable-method = "psci";
0099 cpu-idle-states = <&CPU_SLEEP_0>;
0100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
0101 };
0102
0103 a55_4: cpu@20000 {
0104 compatible = "arm,cortex-a55";
0105 reg = <0x20000>;
0106 device_type = "cpu";
0107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
0108 next-level-cache = <&L3_CA55_2>;
0109 enable-method = "psci";
0110 cpu-idle-states = <&CPU_SLEEP_0>;
0111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
0112 };
0113
0114 a55_5: cpu@20100 {
0115 compatible = "arm,cortex-a55";
0116 reg = <0x20100>;
0117 device_type = "cpu";
0118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
0119 next-level-cache = <&L3_CA55_2>;
0120 enable-method = "psci";
0121 cpu-idle-states = <&CPU_SLEEP_0>;
0122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
0123 };
0124
0125 a55_6: cpu@30000 {
0126 compatible = "arm,cortex-a55";
0127 reg = <0x30000>;
0128 device_type = "cpu";
0129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
0130 next-level-cache = <&L3_CA55_3>;
0131 enable-method = "psci";
0132 cpu-idle-states = <&CPU_SLEEP_0>;
0133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
0134 };
0135
0136 a55_7: cpu@30100 {
0137 compatible = "arm,cortex-a55";
0138 reg = <0x30100>;
0139 device_type = "cpu";
0140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
0141 next-level-cache = <&L3_CA55_3>;
0142 enable-method = "psci";
0143 cpu-idle-states = <&CPU_SLEEP_0>;
0144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
0145 };
0146
0147 L3_CA55_0: cache-controller-0 {
0148 compatible = "cache";
0149 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
0150 cache-unified;
0151 cache-level = <3>;
0152 };
0153
0154 L3_CA55_1: cache-controller-1 {
0155 compatible = "cache";
0156 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
0157 cache-unified;
0158 cache-level = <3>;
0159 };
0160
0161 L3_CA55_2: cache-controller-2 {
0162 compatible = "cache";
0163 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
0164 cache-unified;
0165 cache-level = <3>;
0166 };
0167
0168 L3_CA55_3: cache-controller-3 {
0169 compatible = "cache";
0170 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
0171 cache-unified;
0172 cache-level = <3>;
0173 };
0174
0175 idle-states {
0176 entry-method = "psci";
0177
0178 CPU_SLEEP_0: cpu-sleep-0 {
0179 compatible = "arm,idle-state";
0180 arm,psci-suspend-param = <0x0010000>;
0181 local-timer-stop;
0182 entry-latency-us = <400>;
0183 exit-latency-us = <500>;
0184 min-residency-us = <4000>;
0185 };
0186 };
0187 };
0188
0189 extal_clk: extal {
0190 compatible = "fixed-clock";
0191 #clock-cells = <0>;
0192 /* This value must be overridden by the board */
0193 clock-frequency = <0>;
0194 };
0195
0196 extalr_clk: extalr {
0197 compatible = "fixed-clock";
0198 #clock-cells = <0>;
0199 /* This value must be overridden by the board */
0200 clock-frequency = <0>;
0201 };
0202
0203 pmu_a55 {
0204 compatible = "arm,cortex-a55-pmu";
0205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0206 };
0207
0208 psci {
0209 compatible = "arm,psci-1.0", "arm,psci-0.2";
0210 method = "smc";
0211 };
0212
0213 /* External SCIF clock - to be overridden by boards that provide it */
0214 scif_clk: scif {
0215 compatible = "fixed-clock";
0216 #clock-cells = <0>;
0217 clock-frequency = <0>;
0218 };
0219
0220 soc: soc {
0221 compatible = "simple-bus";
0222 interrupt-parent = <&gic>;
0223 #address-cells = <2>;
0224 #size-cells = <2>;
0225 ranges;
0226
0227 rwdt: watchdog@e6020000 {
0228 compatible = "renesas,r8a779f0-wdt",
0229 "renesas,rcar-gen4-wdt";
0230 reg = <0 0xe6020000 0 0x0c>;
0231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <&cpg CPG_MOD 907>;
0233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0234 resets = <&cpg 907>;
0235 status = "disabled";
0236 };
0237
0238 pfc: pinctrl@e6050000 {
0239 compatible = "renesas,pfc-r8a779f0";
0240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
0241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
0242 };
0243
0244 gpio0: gpio@e6050180 {
0245 compatible = "renesas,gpio-r8a779f0",
0246 "renesas,rcar-gen4-gpio";
0247 reg = <0 0xe6050180 0 0x54>;
0248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
0249 clocks = <&cpg CPG_MOD 915>;
0250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0251 resets = <&cpg 915>;
0252 gpio-controller;
0253 #gpio-cells = <2>;
0254 gpio-ranges = <&pfc 0 0 21>;
0255 interrupt-controller;
0256 #interrupt-cells = <2>;
0257 };
0258
0259 gpio1: gpio@e6050980 {
0260 compatible = "renesas,gpio-r8a779f0",
0261 "renesas,rcar-gen4-gpio";
0262 reg = <0 0xe6050980 0 0x54>;
0263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
0264 clocks = <&cpg CPG_MOD 915>;
0265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0266 resets = <&cpg 915>;
0267 gpio-controller;
0268 #gpio-cells = <2>;
0269 gpio-ranges = <&pfc 0 32 25>;
0270 interrupt-controller;
0271 #interrupt-cells = <2>;
0272 };
0273
0274 gpio2: gpio@e6051180 {
0275 compatible = "renesas,gpio-r8a779f0",
0276 "renesas,rcar-gen4-gpio";
0277 reg = <0 0xe6051180 0 0x54>;
0278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
0279 clocks = <&cpg CPG_MOD 915>;
0280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0281 resets = <&cpg 915>;
0282 gpio-controller;
0283 #gpio-cells = <2>;
0284 gpio-ranges = <&pfc 0 64 17>;
0285 interrupt-controller;
0286 #interrupt-cells = <2>;
0287 };
0288
0289 gpio3: gpio@e6051980 {
0290 compatible = "renesas,gpio-r8a779f0",
0291 "renesas,rcar-gen4-gpio";
0292 reg = <0 0xe6051980 0 0x54>;
0293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
0294 clocks = <&cpg CPG_MOD 915>;
0295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0296 resets = <&cpg 915>;
0297 gpio-controller;
0298 #gpio-cells = <2>;
0299 gpio-ranges = <&pfc 0 96 19>;
0300 interrupt-controller;
0301 #interrupt-cells = <2>;
0302 };
0303
0304 cpg: clock-controller@e6150000 {
0305 compatible = "renesas,r8a779f0-cpg-mssr";
0306 reg = <0 0xe6150000 0 0x4000>;
0307 clocks = <&extal_clk>, <&extalr_clk>;
0308 clock-names = "extal", "extalr";
0309 #clock-cells = <2>;
0310 #power-domain-cells = <0>;
0311 #reset-cells = <1>;
0312 };
0313
0314 rst: reset-controller@e6160000 {
0315 compatible = "renesas,r8a779f0-rst";
0316 reg = <0 0xe6160000 0 0x4000>;
0317 };
0318
0319 sysc: system-controller@e6180000 {
0320 compatible = "renesas,r8a779f0-sysc";
0321 reg = <0 0xe6180000 0 0x4000>;
0322 #power-domain-cells = <1>;
0323 };
0324
0325 tsc: thermal@e6198000 {
0326 compatible = "renesas,r8a779f0-thermal";
0327 /* The 4th sensor is in control domain and not for Linux */
0328 reg = <0 0xe6198000 0 0x200>,
0329 <0 0xe61a0000 0 0x200>,
0330 <0 0xe61a8000 0 0x200>;
0331 clocks = <&cpg CPG_MOD 919>;
0332 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0333 resets = <&cpg 919>;
0334 #thermal-sensor-cells = <1>;
0335 };
0336
0337 i2c0: i2c@e6500000 {
0338 compatible = "renesas,i2c-r8a779f0",
0339 "renesas,rcar-gen4-i2c";
0340 reg = <0 0xe6500000 0 0x40>;
0341 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&cpg CPG_MOD 518>;
0343 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0344 resets = <&cpg 518>;
0345 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
0346 <&dmac1 0x91>, <&dmac1 0x90>;
0347 dma-names = "tx", "rx", "tx", "rx";
0348 i2c-scl-internal-delay-ns = <110>;
0349 #address-cells = <1>;
0350 #size-cells = <0>;
0351 status = "disabled";
0352 };
0353
0354 i2c1: i2c@e6508000 {
0355 compatible = "renesas,i2c-r8a779f0",
0356 "renesas,rcar-gen4-i2c";
0357 reg = <0 0xe6508000 0 0x40>;
0358 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
0359 clocks = <&cpg CPG_MOD 519>;
0360 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0361 resets = <&cpg 519>;
0362 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
0363 <&dmac1 0x93>, <&dmac1 0x92>;
0364 dma-names = "tx", "rx", "tx", "rx";
0365 i2c-scl-internal-delay-ns = <110>;
0366 #address-cells = <1>;
0367 #size-cells = <0>;
0368 status = "disabled";
0369 };
0370
0371 i2c2: i2c@e6510000 {
0372 compatible = "renesas,i2c-r8a779f0",
0373 "renesas,rcar-gen4-i2c";
0374 reg = <0 0xe6510000 0 0x40>;
0375 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
0376 clocks = <&cpg CPG_MOD 520>;
0377 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0378 resets = <&cpg 520>;
0379 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
0380 <&dmac1 0x95>, <&dmac1 0x94>;
0381 dma-names = "tx", "rx", "tx", "rx";
0382 i2c-scl-internal-delay-ns = <110>;
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 status = "disabled";
0386 };
0387
0388 i2c3: i2c@e66d0000 {
0389 compatible = "renesas,i2c-r8a779f0",
0390 "renesas,rcar-gen4-i2c";
0391 reg = <0 0xe66d0000 0 0x40>;
0392 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
0393 clocks = <&cpg CPG_MOD 521>;
0394 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0395 resets = <&cpg 521>;
0396 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
0397 <&dmac1 0x97>, <&dmac1 0x96>;
0398 dma-names = "tx", "rx", "tx", "rx";
0399 i2c-scl-internal-delay-ns = <110>;
0400 #address-cells = <1>;
0401 #size-cells = <0>;
0402 status = "disabled";
0403 };
0404
0405 i2c4: i2c@e66d8000 {
0406 compatible = "renesas,i2c-r8a779f0",
0407 "renesas,rcar-gen4-i2c";
0408 reg = <0 0xe66d8000 0 0x40>;
0409 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
0410 clocks = <&cpg CPG_MOD 522>;
0411 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0412 resets = <&cpg 522>;
0413 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
0414 <&dmac1 0x99>, <&dmac1 0x98>;
0415 dma-names = "tx", "rx", "tx", "rx";
0416 i2c-scl-internal-delay-ns = <110>;
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 status = "disabled";
0420 };
0421
0422 i2c5: i2c@e66e0000 {
0423 compatible = "renesas,i2c-r8a779f0",
0424 "renesas,rcar-gen4-i2c";
0425 reg = <0 0xe66e0000 0 0x40>;
0426 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
0427 clocks = <&cpg CPG_MOD 523>;
0428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0429 resets = <&cpg 523>;
0430 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
0431 <&dmac1 0x9b>, <&dmac1 0x9a>;
0432 dma-names = "tx", "rx", "tx", "rx";
0433 i2c-scl-internal-delay-ns = <110>;
0434 #address-cells = <1>;
0435 #size-cells = <0>;
0436 status = "disabled";
0437 };
0438
0439 hscif0: serial@e6540000 {
0440 compatible = "renesas,hscif-r8a779f0",
0441 "renesas,rcar-gen4-hscif", "renesas,hscif";
0442 reg = <0 0xe6540000 0 0x60>;
0443 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
0444 clocks = <&cpg CPG_MOD 514>,
0445 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
0446 <&scif_clk>;
0447 clock-names = "fck", "brg_int", "scif_clk";
0448 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
0449 <&dmac1 0x31>, <&dmac1 0x30>;
0450 dma-names = "tx", "rx", "tx", "rx";
0451 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0452 resets = <&cpg 514>;
0453 status = "disabled";
0454 };
0455
0456 hscif1: serial@e6550000 {
0457 compatible = "renesas,hscif-r8a779f0",
0458 "renesas,rcar-gen4-hscif", "renesas,hscif";
0459 reg = <0 0xe6550000 0 0x60>;
0460 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
0461 clocks = <&cpg CPG_MOD 515>,
0462 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
0463 <&scif_clk>;
0464 clock-names = "fck", "brg_int", "scif_clk";
0465 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
0466 <&dmac1 0x33>, <&dmac1 0x32>;
0467 dma-names = "tx", "rx", "tx", "rx";
0468 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0469 resets = <&cpg 515>;
0470 status = "disabled";
0471 };
0472
0473 hscif2: serial@e6560000 {
0474 compatible = "renesas,hscif-r8a779f0",
0475 "renesas,rcar-gen4-hscif", "renesas,hscif";
0476 reg = <0 0xe6560000 0 0x60>;
0477 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
0478 clocks = <&cpg CPG_MOD 516>,
0479 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
0480 <&scif_clk>;
0481 clock-names = "fck", "brg_int", "scif_clk";
0482 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
0483 <&dmac1 0x35>, <&dmac1 0x34>;
0484 dma-names = "tx", "rx", "tx", "rx";
0485 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0486 resets = <&cpg 516>;
0487 status = "disabled";
0488 };
0489
0490 hscif3: serial@e66a0000 {
0491 compatible = "renesas,hscif-r8a779f0",
0492 "renesas,rcar-gen4-hscif", "renesas,hscif";
0493 reg = <0 0xe66a0000 0 0x60>;
0494 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
0495 clocks = <&cpg CPG_MOD 517>,
0496 <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
0497 <&scif_clk>;
0498 clock-names = "fck", "brg_int", "scif_clk";
0499 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
0500 <&dmac1 0x37>, <&dmac1 0x36>;
0501 dma-names = "tx", "rx", "tx", "rx";
0502 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0503 resets = <&cpg 517>;
0504 status = "disabled";
0505 };
0506
0507 ufs: ufs@e6860000 {
0508 compatible = "renesas,r8a779f0-ufs";
0509 reg = <0 0xe6860000 0 0x100>;
0510 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
0511 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
0512 clock-names = "fck", "ref_clk";
0513 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
0514 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0515 resets = <&cpg 1514>;
0516 status = "disabled";
0517 };
0518
0519 scif0: serial@e6e60000 {
0520 compatible = "renesas,scif-r8a779f0",
0521 "renesas,rcar-gen4-scif", "renesas,scif";
0522 reg = <0 0xe6e60000 0 64>;
0523 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0524 clocks = <&cpg CPG_MOD 702>,
0525 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
0526 <&scif_clk>;
0527 clock-names = "fck", "brg_int", "scif_clk";
0528 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
0529 <&dmac1 0x51>, <&dmac1 0x50>;
0530 dma-names = "tx", "rx", "tx", "rx";
0531 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0532 resets = <&cpg 702>;
0533 status = "disabled";
0534 };
0535
0536 scif1: serial@e6e68000 {
0537 compatible = "renesas,scif-r8a779f0",
0538 "renesas,rcar-gen4-scif", "renesas,scif";
0539 reg = <0 0xe6e68000 0 64>;
0540 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
0541 clocks = <&cpg CPG_MOD 703>,
0542 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
0543 <&scif_clk>;
0544 clock-names = "fck", "brg_int", "scif_clk";
0545 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
0546 <&dmac1 0x53>, <&dmac1 0x52>;
0547 dma-names = "tx", "rx", "tx", "rx";
0548 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0549 resets = <&cpg 703>;
0550 status = "disabled";
0551 };
0552
0553 scif3: serial@e6c50000 {
0554 compatible = "renesas,scif-r8a779f0",
0555 "renesas,rcar-gen4-scif", "renesas,scif";
0556 reg = <0 0xe6c50000 0 64>;
0557 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
0558 clocks = <&cpg CPG_MOD 704>,
0559 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
0560 <&scif_clk>;
0561 clock-names = "fck", "brg_int", "scif_clk";
0562 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
0563 <&dmac1 0x57>, <&dmac1 0x56>;
0564 dma-names = "tx", "rx", "tx", "rx";
0565 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0566 resets = <&cpg 704>;
0567 status = "disabled";
0568 };
0569
0570 scif4: serial@e6c40000 {
0571 compatible = "renesas,scif-r8a779f0",
0572 "renesas,rcar-gen4-scif", "renesas,scif";
0573 reg = <0 0xe6c40000 0 64>;
0574 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
0575 clocks = <&cpg CPG_MOD 705>,
0576 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
0577 <&scif_clk>;
0578 clock-names = "fck", "brg_int", "scif_clk";
0579 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
0580 <&dmac1 0x59>, <&dmac1 0x58>;
0581 dma-names = "tx", "rx", "tx", "rx";
0582 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0583 resets = <&cpg 705>;
0584 status = "disabled";
0585 };
0586
0587 dmac0: dma-controller@e7350000 {
0588 compatible = "renesas,dmac-r8a779f0",
0589 "renesas,rcar-gen4-dmac";
0590 reg = <0 0xe7350000 0 0x1000>,
0591 <0 0xe7300000 0 0x10000>;
0592 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0593 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0598 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0599 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0600 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0601 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0602 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0603 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0604 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0605 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0606 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0607 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0608 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0609 interrupt-names = "error",
0610 "ch0", "ch1", "ch2", "ch3", "ch4",
0611 "ch5", "ch6", "ch7", "ch8", "ch9",
0612 "ch10", "ch11", "ch12", "ch13",
0613 "ch14", "ch15";
0614 clocks = <&cpg CPG_MOD 709>;
0615 clock-names = "fck";
0616 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0617 resets = <&cpg 709>;
0618 #dma-cells = <1>;
0619 dma-channels = <16>;
0620 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
0621 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
0622 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
0623 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
0624 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
0625 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
0626 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
0627 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
0628 };
0629
0630 dmac1: dma-controller@e7351000 {
0631 compatible = "renesas,dmac-r8a779f0",
0632 "renesas,rcar-gen4-dmac";
0633 reg = <0 0xe7351000 0 0x1000>,
0634 <0 0xe7310000 0 0x10000>;
0635 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0636 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0637 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0638 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0639 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0640 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0641 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0642 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0643 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
0644 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0645 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0646 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0647 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0648 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0649 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0650 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0651 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0652 interrupt-names = "error",
0653 "ch0", "ch1", "ch2", "ch3", "ch4",
0654 "ch5", "ch6", "ch7", "ch8", "ch9",
0655 "ch10", "ch11", "ch12", "ch13",
0656 "ch14", "ch15";
0657 clocks = <&cpg CPG_MOD 710>;
0658 clock-names = "fck";
0659 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0660 resets = <&cpg 710>;
0661 #dma-cells = <1>;
0662 dma-channels = <16>;
0663 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
0664 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
0665 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
0666 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
0667 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
0668 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
0669 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
0670 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
0671 };
0672
0673 ipmmu_rt0: iommu@ee480000 {
0674 compatible = "renesas,ipmmu-r8a779f0",
0675 "renesas,rcar-gen4-ipmmu-vmsa";
0676 reg = <0 0xee480000 0 0x20000>;
0677 renesas,ipmmu-main = <&ipmmu_mm 10>;
0678 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0679 #iommu-cells = <1>;
0680 };
0681
0682 ipmmu_rt1: iommu@ee4c0000 {
0683 compatible = "renesas,ipmmu-r8a779f0",
0684 "renesas,rcar-gen4-ipmmu-vmsa";
0685 reg = <0 0xee4c0000 0 0x20000>;
0686 renesas,ipmmu-main = <&ipmmu_mm 19>;
0687 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0688 #iommu-cells = <1>;
0689 };
0690
0691 ipmmu_ds0: iommu@eed00000 {
0692 compatible = "renesas,ipmmu-r8a779f0",
0693 "renesas,rcar-gen4-ipmmu-vmsa";
0694 reg = <0 0xeed00000 0 0x20000>;
0695 renesas,ipmmu-main = <&ipmmu_mm 0>;
0696 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0697 #iommu-cells = <1>;
0698 };
0699
0700 ipmmu_hc: iommu@eed40000 {
0701 compatible = "renesas,ipmmu-r8a779f0",
0702 "renesas,rcar-gen4-ipmmu-vmsa";
0703 reg = <0 0xeed40000 0 0x20000>;
0704 renesas,ipmmu-main = <&ipmmu_mm 2>;
0705 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0706 #iommu-cells = <1>;
0707 };
0708
0709 ipmmu_mm: iommu@eefc0000 {
0710 compatible = "renesas,ipmmu-r8a779f0",
0711 "renesas,rcar-gen4-ipmmu-vmsa";
0712 reg = <0 0xeefc0000 0 0x20000>;
0713 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0714 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0715 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
0716 #iommu-cells = <1>;
0717 };
0718
0719 gic: interrupt-controller@f1000000 {
0720 compatible = "arm,gic-v3";
0721 #interrupt-cells = <3>;
0722 #address-cells = <0>;
0723 interrupt-controller;
0724 reg = <0x0 0xf1000000 0 0x20000>,
0725 <0x0 0xf1060000 0 0x110000>;
0726 interrupts = <GIC_PPI 9
0727 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0728 };
0729
0730 prr: chipid@fff00044 {
0731 compatible = "renesas,prr";
0732 reg = <0 0xfff00044 0 4>;
0733 };
0734 };
0735
0736 thermal-zones {
0737 sensor_thermal1: sensor1-thermal {
0738 polling-delay-passive = <250>;
0739 polling-delay = <1000>;
0740 thermal-sensors = <&tsc 0>;
0741
0742 trips {
0743 sensor1_crit: sensor1-crit {
0744 temperature = <120000>;
0745 hysteresis = <1000>;
0746 type = "critical";
0747 };
0748 };
0749 };
0750
0751 sensor_thermal2: sensor2-thermal {
0752 polling-delay-passive = <250>;
0753 polling-delay = <1000>;
0754 thermal-sensors = <&tsc 1>;
0755
0756 trips {
0757 sensor2_crit: sensor2-crit {
0758 temperature = <120000>;
0759 hysteresis = <1000>;
0760 type = "critical";
0761 };
0762 };
0763 };
0764
0765 sensor_thermal3: sensor3-thermal {
0766 polling-delay-passive = <250>;
0767 polling-delay = <1000>;
0768 thermal-sensors = <&tsc 2>;
0769
0770 trips {
0771 sensor3_crit: sensor3-crit {
0772 temperature = <120000>;
0773 hysteresis = <1000>;
0774 type = "critical";
0775 };
0776 };
0777 };
0778 };
0779
0780 timer {
0781 compatible = "arm,armv8-timer";
0782 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0783 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0784 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0785 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0786 };
0787
0788 ufs30_clk: ufs30-clk {
0789 compatible = "fixed-clock";
0790 #clock-cells = <0>;
0791 /* This value must be overridden by the board */
0792 clock-frequency = <0>;
0793 };
0794 };
