0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the Condor board with R-Car V3H
0004 *
0005 * Copyright (C) 2018 Renesas Electronics Corp.
0006 * Copyright (C) 2018 Cogent Embedded, Inc.
0007 */
0008
0009 /dts-v1/;
0010 #include "r8a77980.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012
0013 / {
0014 model = "Renesas Condor board based on r8a77980";
0015 compatible = "renesas,condor", "renesas,r8a77980";
0016
0017 aliases {
0018 serial0 = &scif0;
0019 ethernet0 = &gether;
0020 };
0021
0022 chosen {
0023 stdout-path = "serial0:115200n8";
0024 };
0025
0026 d1_8v: regulator-2 {
0027 compatible = "regulator-fixed";
0028 regulator-name = "D1.8V";
0029 regulator-min-microvolt = <1800000>;
0030 regulator-max-microvolt = <1800000>;
0031 regulator-boot-on;
0032 regulator-always-on;
0033 };
0034
0035 d3_3v: regulator-0 {
0036 compatible = "regulator-fixed";
0037 regulator-name = "D3.3V";
0038 regulator-min-microvolt = <3300000>;
0039 regulator-max-microvolt = <3300000>;
0040 regulator-boot-on;
0041 regulator-always-on;
0042 };
0043
0044 hdmi-out {
0045 compatible = "hdmi-connector";
0046 type = "a";
0047
0048 port {
0049 hdmi_con: endpoint {
0050 remote-endpoint = <&adv7511_out>;
0051 };
0052 };
0053 };
0054
0055 lvds-decoder {
0056 compatible = "thine,thc63lvd1024";
0057 vcc-supply = <&d3_3v>;
0058
0059 ports {
0060 #address-cells = <1>;
0061 #size-cells = <0>;
0062
0063 port@0 {
0064 reg = <0>;
0065 thc63lvd1024_in: endpoint {
0066 remote-endpoint = <&lvds0_out>;
0067 };
0068 };
0069
0070 port@2 {
0071 reg = <2>;
0072 thc63lvd1024_out: endpoint {
0073 remote-endpoint = <&adv7511_in>;
0074 };
0075 };
0076 };
0077 };
0078
0079 memory@48000000 {
0080 device_type = "memory";
0081 /* first 128MB is reserved for secure area. */
0082 reg = <0 0x48000000 0 0x78000000>;
0083 };
0084
0085 vddq_vin01: regulator-1 {
0086 compatible = "regulator-fixed";
0087 regulator-name = "VDDQ_VIN01";
0088 regulator-min-microvolt = <1800000>;
0089 regulator-max-microvolt = <1800000>;
0090 regulator-boot-on;
0091 regulator-always-on;
0092 };
0093
0094 x1_clk: x1-clock {
0095 compatible = "fixed-clock";
0096 #clock-cells = <0>;
0097 clock-frequency = <148500000>;
0098 };
0099 };
0100
0101 &canfd {
0102 pinctrl-0 = <&canfd0_pins>;
0103 pinctrl-names = "default";
0104 status = "okay";
0105
0106 channel0 {
0107 status = "okay";
0108 };
0109 };
0110
0111 &csi40 {
0112 status = "okay";
0113
0114 ports {
0115 port@0 {
0116 csi40_in: endpoint {
0117 clock-lanes = <0>;
0118 data-lanes = <1 2 3 4>;
0119 remote-endpoint = <&max9286_out0>;
0120 };
0121 };
0122 };
0123 };
0124
0125 &csi41 {
0126 status = "okay";
0127
0128 ports {
0129 port@0 {
0130 csi41_in: endpoint {
0131 clock-lanes = <0>;
0132 data-lanes = <1 2 3 4>;
0133 remote-endpoint = <&max9286_out1>;
0134 };
0135 };
0136 };
0137 };
0138
0139 &du {
0140 clocks = <&cpg CPG_MOD 724>,
0141 <&x1_clk>;
0142 clock-names = "du.0", "dclkin.0";
0143 status = "okay";
0144 };
0145
0146 &extal_clk {
0147 clock-frequency = <16666666>;
0148 };
0149
0150 &extalr_clk {
0151 clock-frequency = <32768>;
0152 };
0153
0154 &gether {
0155 pinctrl-0 = <&gether_pins>;
0156 pinctrl-names = "default";
0157
0158 phy-mode = "rgmii-id";
0159 phy-handle = <&phy0>;
0160 renesas,no-ether-link;
0161 status = "okay";
0162
0163 phy0: ethernet-phy@0 {
0164 compatible = "ethernet-phy-id0022.1622",
0165 "ethernet-phy-ieee802.3-c22";
0166 rxc-skew-ps = <1500>;
0167 reg = <0>;
0168 interrupt-parent = <&gpio4>;
0169 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
0170 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0171 };
0172 };
0173
0174 &i2c0 {
0175 pinctrl-0 = <&i2c0_pins>;
0176 pinctrl-names = "default";
0177
0178 status = "okay";
0179 clock-frequency = <400000>;
0180
0181 io_expander0: gpio@20 {
0182 compatible = "onnn,pca9654";
0183 reg = <0x20>;
0184 gpio-controller;
0185 #gpio-cells = <2>;
0186 };
0187
0188 io_expander1: gpio@21 {
0189 compatible = "onnn,pca9654";
0190 reg = <0x21>;
0191 gpio-controller;
0192 #gpio-cells = <2>;
0193 };
0194
0195 hdmi@39 {
0196 compatible = "adi,adv7511w";
0197 reg = <0x39>;
0198 interrupt-parent = <&gpio1>;
0199 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0200 avdd-supply = <&d1_8v>;
0201 dvdd-supply = <&d1_8v>;
0202 pvdd-supply = <&d1_8v>;
0203 bgvdd-supply = <&d1_8v>;
0204 dvdd-3v-supply = <&d3_3v>;
0205
0206 adi,input-depth = <8>;
0207 adi,input-colorspace = "rgb";
0208 adi,input-clock = "1x";
0209
0210 ports {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213
0214 port@0 {
0215 reg = <0>;
0216 adv7511_in: endpoint {
0217 remote-endpoint = <&thc63lvd1024_out>;
0218 };
0219 };
0220
0221 port@1 {
0222 reg = <1>;
0223 adv7511_out: endpoint {
0224 remote-endpoint = <&hdmi_con>;
0225 };
0226 };
0227 };
0228 };
0229 };
0230
0231 &i2c1 {
0232 pinctrl-0 = <&i2c1_pins>;
0233 pinctrl-names = "default";
0234
0235 status = "okay";
0236 clock-frequency = <400000>;
0237
0238 gmsl0: gmsl-deserializer@48 {
0239 compatible = "maxim,max9286";
0240 reg = <0x48>;
0241
0242 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
0243 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
0244
0245 ports {
0246 #address-cells = <1>;
0247 #size-cells = <0>;
0248
0249 port@0 {
0250 reg = <0>;
0251 };
0252
0253 port@1 {
0254 reg = <1>;
0255 };
0256
0257 port@2 {
0258 reg = <2>;
0259 };
0260
0261 port@3 {
0262 reg = <3>;
0263 };
0264
0265 port@4 {
0266 reg = <4>;
0267 max9286_out0: endpoint {
0268 clock-lanes = <0>;
0269 data-lanes = <1 2 3 4>;
0270 remote-endpoint = <&csi40_in>;
0271 };
0272 };
0273 };
0274
0275 i2c-mux {
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278
0279 i2c@0 {
0280 #address-cells = <1>;
0281 #size-cells = <0>;
0282 reg = <0>;
0283
0284 status = "disabled";
0285 };
0286
0287 i2c@1 {
0288 #address-cells = <1>;
0289 #size-cells = <0>;
0290 reg = <1>;
0291
0292 status = "disabled";
0293 };
0294
0295 i2c@2 {
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 reg = <2>;
0299
0300 status = "disabled";
0301 };
0302
0303 i2c@3 {
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306 reg = <3>;
0307
0308 status = "disabled";
0309 };
0310 };
0311 };
0312
0313 gmsl1: gmsl-deserializer@4a {
0314 compatible = "maxim,max9286";
0315 reg = <0x4a>;
0316
0317 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
0318 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
0319
0320 ports {
0321 #address-cells = <1>;
0322 #size-cells = <0>;
0323
0324 port@0 {
0325 reg = <0>;
0326 };
0327
0328 port@1 {
0329 reg = <1>;
0330 };
0331
0332 port@2 {
0333 reg = <2>;
0334 };
0335
0336 port@3 {
0337 reg = <3>;
0338 };
0339
0340 port@4 {
0341 reg = <4>;
0342 max9286_out1: endpoint {
0343 clock-lanes = <0>;
0344 data-lanes = <1 2 3 4>;
0345 remote-endpoint = <&csi41_in>;
0346 };
0347 };
0348 };
0349
0350 i2c-mux {
0351 #address-cells = <1>;
0352 #size-cells = <0>;
0353
0354 i2c@0 {
0355 #address-cells = <1>;
0356 #size-cells = <0>;
0357 reg = <0>;
0358
0359 status = "disabled";
0360 };
0361
0362 i2c@1 {
0363 #address-cells = <1>;
0364 #size-cells = <0>;
0365 reg = <1>;
0366
0367 status = "disabled";
0368 };
0369
0370 i2c@2 {
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373 reg = <2>;
0374
0375 status = "disabled";
0376 };
0377
0378 i2c@3 {
0379 #address-cells = <1>;
0380 #size-cells = <0>;
0381 reg = <3>;
0382
0383 status = "disabled";
0384 };
0385 };
0386 };
0387 };
0388
0389 &lvds0 {
0390 status = "okay";
0391
0392 ports {
0393 port@1 {
0394 lvds0_out: endpoint {
0395 remote-endpoint = <&thc63lvd1024_in>;
0396 };
0397 };
0398 };
0399 };
0400
0401 &mmc0 {
0402 pinctrl-0 = <&mmc_pins>;
0403 pinctrl-1 = <&mmc_pins>;
0404 pinctrl-names = "default", "state_uhs";
0405
0406 vmmc-supply = <&d3_3v>;
0407 vqmmc-supply = <&vddq_vin01>;
0408 mmc-hs200-1_8v;
0409 bus-width = <8>;
0410 no-sd;
0411 no-sdio;
0412 non-removable;
0413 status = "okay";
0414 };
0415
0416 &pciec {
0417 status = "okay";
0418 };
0419
0420 &pcie_bus_clk {
0421 clock-frequency = <100000000>;
0422 };
0423
0424 &pcie_phy {
0425 status = "okay";
0426 };
0427
0428 &pfc {
0429 canfd0_pins: canfd0 {
0430 groups = "canfd0_data_a";
0431 function = "canfd0";
0432 };
0433
0434 gether_pins: gether {
0435 groups = "gether_mdio_a", "gether_rgmii",
0436 "gether_txcrefclk", "gether_txcrefclk_mega";
0437 function = "gether";
0438 };
0439
0440 i2c0_pins: i2c0 {
0441 groups = "i2c0";
0442 function = "i2c0";
0443 };
0444
0445 i2c1_pins: i2c1 {
0446 groups = "i2c1";
0447 function = "i2c1";
0448 };
0449
0450 mmc_pins: mmc {
0451 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
0452 function = "mmc";
0453 power-source = <1800>;
0454 };
0455
0456 qspi0_pins: qspi0 {
0457 groups = "qspi0_ctrl", "qspi0_data4";
0458 function = "qspi0";
0459 };
0460
0461 scif0_pins: scif0 {
0462 groups = "scif0_data";
0463 function = "scif0";
0464 };
0465
0466 scif_clk_pins: scif_clk {
0467 groups = "scif_clk_b";
0468 function = "scif_clk";
0469 };
0470 };
0471
0472 &rpc {
0473 pinctrl-0 = <&qspi0_pins>;
0474 pinctrl-names = "default";
0475
0476 status = "okay";
0477
0478 flash@0 {
0479 compatible = "spansion,s25fs512s", "jedec,spi-nor";
0480 reg = <0>;
0481 spi-max-frequency = <50000000>;
0482 spi-rx-bus-width = <4>;
0483
0484 partitions {
0485 compatible = "fixed-partitions";
0486 #address-cells = <1>;
0487 #size-cells = <1>;
0488
0489 bootparam@0 {
0490 reg = <0x00000000 0x040000>;
0491 read-only;
0492 };
0493 cr7@40000 {
0494 reg = <0x00040000 0x080000>;
0495 read-only;
0496 };
0497 cert_header_sa3@c0000 {
0498 reg = <0x000c0000 0x080000>;
0499 read-only;
0500 };
0501 bl2@140000 {
0502 reg = <0x00140000 0x040000>;
0503 read-only;
0504 };
0505 cert_header_sa6@180000 {
0506 reg = <0x00180000 0x040000>;
0507 read-only;
0508 };
0509 bl31@1c0000 {
0510 reg = <0x001c0000 0x460000>;
0511 read-only;
0512 };
0513 uboot@640000 {
0514 reg = <0x00640000 0x0c0000>;
0515 read-only;
0516 };
0517 uboot-env@700000 {
0518 reg = <0x00700000 0x040000>;
0519 read-only;
0520 };
0521 dtb@740000 {
0522 reg = <0x00740000 0x080000>;
0523 };
0524 kernel@7c0000 {
0525 reg = <0x007c0000 0x1400000>;
0526 };
0527 user@1bc0000 {
0528 reg = <0x01bc0000 0x2440000>;
0529 };
0530 };
0531 };
0532 };
0533
0534 &rwdt {
0535 timeout-sec = <60>;
0536 status = "okay";
0537 };
0538
0539 &scif0 {
0540 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
0541 pinctrl-names = "default";
0542
0543 status = "okay";
0544 };
0545
0546 &scif_clk {
0547 clock-frequency = <14745600>;
0548 };
