OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
0008 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
0009 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
0010 #include <dt-bindings/clock/qcom,rpmh.h>
0011 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
0012 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
0013 #include <dt-bindings/dma/qcom-gpi.h>
0014 #include <dt-bindings/gpio/gpio.h>
0015 #include <dt-bindings/interconnect/qcom,osm-l3.h>
0016 #include <dt-bindings/interconnect/qcom,sm8250.h>
0017 #include <dt-bindings/mailbox/qcom-ipcc.h>
0018 #include <dt-bindings/power/qcom-rpmpd.h>
0019 #include <dt-bindings/soc/qcom,apr.h>
0020 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0021 #include <dt-bindings/sound/qcom,q6afe.h>
0022 #include <dt-bindings/thermal/thermal.h>
0023 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
0024 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
0025
0026 / {
0027 interrupt-parent = <&intc>;
0028
0029 #address-cells = <2>;
0030 #size-cells = <2>;
0031
0032 aliases {
0033 i2c0 = &i2c0;
0034 i2c1 = &i2c1;
0035 i2c2 = &i2c2;
0036 i2c3 = &i2c3;
0037 i2c4 = &i2c4;
0038 i2c5 = &i2c5;
0039 i2c6 = &i2c6;
0040 i2c7 = &i2c7;
0041 i2c8 = &i2c8;
0042 i2c9 = &i2c9;
0043 i2c10 = &i2c10;
0044 i2c11 = &i2c11;
0045 i2c12 = &i2c12;
0046 i2c13 = &i2c13;
0047 i2c14 = &i2c14;
0048 i2c15 = &i2c15;
0049 i2c16 = &i2c16;
0050 i2c17 = &i2c17;
0051 i2c18 = &i2c18;
0052 i2c19 = &i2c19;
0053 spi0 = &spi0;
0054 spi1 = &spi1;
0055 spi2 = &spi2;
0056 spi3 = &spi3;
0057 spi4 = &spi4;
0058 spi5 = &spi5;
0059 spi6 = &spi6;
0060 spi7 = &spi7;
0061 spi8 = &spi8;
0062 spi9 = &spi9;
0063 spi10 = &spi10;
0064 spi11 = &spi11;
0065 spi12 = &spi12;
0066 spi13 = &spi13;
0067 spi14 = &spi14;
0068 spi15 = &spi15;
0069 spi16 = &spi16;
0070 spi17 = &spi17;
0071 spi18 = &spi18;
0072 spi19 = &spi19;
0073 };
0074
0075 chosen { };
0076
0077 clocks {
0078 xo_board: xo-board {
0079 compatible = "fixed-clock";
0080 #clock-cells = <0>;
0081 clock-frequency = <38400000>;
0082 clock-output-names = "xo_board";
0083 };
0084
0085 sleep_clk: sleep-clk {
0086 compatible = "fixed-clock";
0087 clock-frequency = <32768>;
0088 #clock-cells = <0>;
0089 };
0090 };
0091
0092 cpus {
0093 #address-cells = <2>;
0094 #size-cells = <0>;
0095
0096 CPU0: cpu@0 {
0097 device_type = "cpu";
0098 compatible = "qcom,kryo485";
0099 reg = <0x0 0x0>;
0100 enable-method = "psci";
0101 capacity-dmips-mhz = <448>;
0102 dynamic-power-coefficient = <205>;
0103 next-level-cache = <&L2_0>;
0104 power-domains = <&CPU_PD0>;
0105 power-domain-names = "psci";
0106 qcom,freq-domain = <&cpufreq_hw 0>;
0107 operating-points-v2 = <&cpu0_opp_table>;
0108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0110 #cooling-cells = <2>;
0111 L2_0: l2-cache {
0112 compatible = "cache";
0113 next-level-cache = <&L3_0>;
0114 L3_0: l3-cache {
0115 compatible = "cache";
0116 };
0117 };
0118 };
0119
0120 CPU1: cpu@100 {
0121 device_type = "cpu";
0122 compatible = "qcom,kryo485";
0123 reg = <0x0 0x100>;
0124 enable-method = "psci";
0125 capacity-dmips-mhz = <448>;
0126 dynamic-power-coefficient = <205>;
0127 next-level-cache = <&L2_100>;
0128 power-domains = <&CPU_PD1>;
0129 power-domain-names = "psci";
0130 qcom,freq-domain = <&cpufreq_hw 0>;
0131 operating-points-v2 = <&cpu0_opp_table>;
0132 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0133 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0134 #cooling-cells = <2>;
0135 L2_100: l2-cache {
0136 compatible = "cache";
0137 next-level-cache = <&L3_0>;
0138 };
0139 };
0140
0141 CPU2: cpu@200 {
0142 device_type = "cpu";
0143 compatible = "qcom,kryo485";
0144 reg = <0x0 0x200>;
0145 enable-method = "psci";
0146 capacity-dmips-mhz = <448>;
0147 dynamic-power-coefficient = <205>;
0148 next-level-cache = <&L2_200>;
0149 power-domains = <&CPU_PD2>;
0150 power-domain-names = "psci";
0151 qcom,freq-domain = <&cpufreq_hw 0>;
0152 operating-points-v2 = <&cpu0_opp_table>;
0153 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0154 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0155 #cooling-cells = <2>;
0156 L2_200: l2-cache {
0157 compatible = "cache";
0158 next-level-cache = <&L3_0>;
0159 };
0160 };
0161
0162 CPU3: cpu@300 {
0163 device_type = "cpu";
0164 compatible = "qcom,kryo485";
0165 reg = <0x0 0x300>;
0166 enable-method = "psci";
0167 capacity-dmips-mhz = <448>;
0168 dynamic-power-coefficient = <205>;
0169 next-level-cache = <&L2_300>;
0170 power-domains = <&CPU_PD3>;
0171 power-domain-names = "psci";
0172 qcom,freq-domain = <&cpufreq_hw 0>;
0173 operating-points-v2 = <&cpu0_opp_table>;
0174 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0175 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0176 #cooling-cells = <2>;
0177 L2_300: l2-cache {
0178 compatible = "cache";
0179 next-level-cache = <&L3_0>;
0180 };
0181 };
0182
0183 CPU4: cpu@400 {
0184 device_type = "cpu";
0185 compatible = "qcom,kryo485";
0186 reg = <0x0 0x400>;
0187 enable-method = "psci";
0188 capacity-dmips-mhz = <1024>;
0189 dynamic-power-coefficient = <379>;
0190 next-level-cache = <&L2_400>;
0191 power-domains = <&CPU_PD4>;
0192 power-domain-names = "psci";
0193 qcom,freq-domain = <&cpufreq_hw 1>;
0194 operating-points-v2 = <&cpu4_opp_table>;
0195 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0196 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0197 #cooling-cells = <2>;
0198 L2_400: l2-cache {
0199 compatible = "cache";
0200 next-level-cache = <&L3_0>;
0201 };
0202 };
0203
0204 CPU5: cpu@500 {
0205 device_type = "cpu";
0206 compatible = "qcom,kryo485";
0207 reg = <0x0 0x500>;
0208 enable-method = "psci";
0209 capacity-dmips-mhz = <1024>;
0210 dynamic-power-coefficient = <379>;
0211 next-level-cache = <&L2_500>;
0212 power-domains = <&CPU_PD5>;
0213 power-domain-names = "psci";
0214 qcom,freq-domain = <&cpufreq_hw 1>;
0215 operating-points-v2 = <&cpu4_opp_table>;
0216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0218 #cooling-cells = <2>;
0219 L2_500: l2-cache {
0220 compatible = "cache";
0221 next-level-cache = <&L3_0>;
0222 };
0223
0224 };
0225
0226 CPU6: cpu@600 {
0227 device_type = "cpu";
0228 compatible = "qcom,kryo485";
0229 reg = <0x0 0x600>;
0230 enable-method = "psci";
0231 capacity-dmips-mhz = <1024>;
0232 dynamic-power-coefficient = <379>;
0233 next-level-cache = <&L2_600>;
0234 power-domains = <&CPU_PD6>;
0235 power-domain-names = "psci";
0236 qcom,freq-domain = <&cpufreq_hw 1>;
0237 operating-points-v2 = <&cpu4_opp_table>;
0238 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0239 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0240 #cooling-cells = <2>;
0241 L2_600: l2-cache {
0242 compatible = "cache";
0243 next-level-cache = <&L3_0>;
0244 };
0245 };
0246
0247 CPU7: cpu@700 {
0248 device_type = "cpu";
0249 compatible = "qcom,kryo485";
0250 reg = <0x0 0x700>;
0251 enable-method = "psci";
0252 capacity-dmips-mhz = <1024>;
0253 dynamic-power-coefficient = <444>;
0254 next-level-cache = <&L2_700>;
0255 power-domains = <&CPU_PD7>;
0256 power-domain-names = "psci";
0257 qcom,freq-domain = <&cpufreq_hw 2>;
0258 operating-points-v2 = <&cpu7_opp_table>;
0259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
0260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
0261 #cooling-cells = <2>;
0262 L2_700: l2-cache {
0263 compatible = "cache";
0264 next-level-cache = <&L3_0>;
0265 };
0266 };
0267
0268 cpu-map {
0269 cluster0 {
0270 core0 {
0271 cpu = <&CPU0>;
0272 };
0273
0274 core1 {
0275 cpu = <&CPU1>;
0276 };
0277
0278 core2 {
0279 cpu = <&CPU2>;
0280 };
0281
0282 core3 {
0283 cpu = <&CPU3>;
0284 };
0285
0286 core4 {
0287 cpu = <&CPU4>;
0288 };
0289
0290 core5 {
0291 cpu = <&CPU5>;
0292 };
0293
0294 core6 {
0295 cpu = <&CPU6>;
0296 };
0297
0298 core7 {
0299 cpu = <&CPU7>;
0300 };
0301 };
0302 };
0303
0304 idle-states {
0305 entry-method = "psci";
0306
0307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
0308 compatible = "arm,idle-state";
0309 idle-state-name = "silver-rail-power-collapse";
0310 arm,psci-suspend-param = <0x40000004>;
0311 entry-latency-us = <360>;
0312 exit-latency-us = <531>;
0313 min-residency-us = <3934>;
0314 local-timer-stop;
0315 };
0316
0317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
0318 compatible = "arm,idle-state";
0319 idle-state-name = "gold-rail-power-collapse";
0320 arm,psci-suspend-param = <0x40000004>;
0321 entry-latency-us = <702>;
0322 exit-latency-us = <1061>;
0323 min-residency-us = <4488>;
0324 local-timer-stop;
0325 };
0326 };
0327
0328 domain-idle-states {
0329 CLUSTER_SLEEP_0: cluster-sleep-0 {
0330 compatible = "domain-idle-state";
0331 idle-state-name = "cluster-llcc-off";
0332 arm,psci-suspend-param = <0x4100c244>;
0333 entry-latency-us = <3264>;
0334 exit-latency-us = <6562>;
0335 min-residency-us = <9987>;
0336 local-timer-stop;
0337 };
0338 };
0339 };
0340
0341 cpu0_opp_table: opp-table-cpu0 {
0342 compatible = "operating-points-v2";
0343 opp-shared;
0344
0345 cpu0_opp1: opp-300000000 {
0346 opp-hz = /bits/ 64 <300000000>;
0347 opp-peak-kBps = <800000 9600000>;
0348 };
0349
0350 cpu0_opp2: opp-403200000 {
0351 opp-hz = /bits/ 64 <403200000>;
0352 opp-peak-kBps = <800000 9600000>;
0353 };
0354
0355 cpu0_opp3: opp-518400000 {
0356 opp-hz = /bits/ 64 <518400000>;
0357 opp-peak-kBps = <800000 16588800>;
0358 };
0359
0360 cpu0_opp4: opp-614400000 {
0361 opp-hz = /bits/ 64 <614400000>;
0362 opp-peak-kBps = <800000 16588800>;
0363 };
0364
0365 cpu0_opp5: opp-691200000 {
0366 opp-hz = /bits/ 64 <691200000>;
0367 opp-peak-kBps = <800000 19660800>;
0368 };
0369
0370 cpu0_opp6: opp-787200000 {
0371 opp-hz = /bits/ 64 <787200000>;
0372 opp-peak-kBps = <1804000 19660800>;
0373 };
0374
0375 cpu0_opp7: opp-883200000 {
0376 opp-hz = /bits/ 64 <883200000>;
0377 opp-peak-kBps = <1804000 23347200>;
0378 };
0379
0380 cpu0_opp8: opp-979200000 {
0381 opp-hz = /bits/ 64 <979200000>;
0382 opp-peak-kBps = <1804000 26419200>;
0383 };
0384
0385 cpu0_opp9: opp-1075200000 {
0386 opp-hz = /bits/ 64 <1075200000>;
0387 opp-peak-kBps = <1804000 29491200>;
0388 };
0389
0390 cpu0_opp10: opp-1171200000 {
0391 opp-hz = /bits/ 64 <1171200000>;
0392 opp-peak-kBps = <1804000 32563200>;
0393 };
0394
0395 cpu0_opp11: opp-1248000000 {
0396 opp-hz = /bits/ 64 <1248000000>;
0397 opp-peak-kBps = <1804000 36249600>;
0398 };
0399
0400 cpu0_opp12: opp-1344000000 {
0401 opp-hz = /bits/ 64 <1344000000>;
0402 opp-peak-kBps = <2188000 36249600>;
0403 };
0404
0405 cpu0_opp13: opp-1420800000 {
0406 opp-hz = /bits/ 64 <1420800000>;
0407 opp-peak-kBps = <2188000 39321600>;
0408 };
0409
0410 cpu0_opp14: opp-1516800000 {
0411 opp-hz = /bits/ 64 <1516800000>;
0412 opp-peak-kBps = <3072000 42393600>;
0413 };
0414
0415 cpu0_opp15: opp-1612800000 {
0416 opp-hz = /bits/ 64 <1612800000>;
0417 opp-peak-kBps = <3072000 42393600>;
0418 };
0419
0420 cpu0_opp16: opp-1708800000 {
0421 opp-hz = /bits/ 64 <1708800000>;
0422 opp-peak-kBps = <4068000 42393600>;
0423 };
0424
0425 cpu0_opp17: opp-1804800000 {
0426 opp-hz = /bits/ 64 <1804800000>;
0427 opp-peak-kBps = <4068000 42393600>;
0428 };
0429 };
0430
0431 cpu4_opp_table: opp-table-cpu4 {
0432 compatible = "operating-points-v2";
0433 opp-shared;
0434
0435 cpu4_opp1: opp-710400000 {
0436 opp-hz = /bits/ 64 <710400000>;
0437 opp-peak-kBps = <1804000 19660800>;
0438 };
0439
0440 cpu4_opp2: opp-825600000 {
0441 opp-hz = /bits/ 64 <825600000>;
0442 opp-peak-kBps = <2188000 23347200>;
0443 };
0444
0445 cpu4_opp3: opp-940800000 {
0446 opp-hz = /bits/ 64 <940800000>;
0447 opp-peak-kBps = <2188000 26419200>;
0448 };
0449
0450 cpu4_opp4: opp-1056000000 {
0451 opp-hz = /bits/ 64 <1056000000>;
0452 opp-peak-kBps = <3072000 26419200>;
0453 };
0454
0455 cpu4_opp5: opp-1171200000 {
0456 opp-hz = /bits/ 64 <1171200000>;
0457 opp-peak-kBps = <3072000 29491200>;
0458 };
0459
0460 cpu4_opp6: opp-1286400000 {
0461 opp-hz = /bits/ 64 <1286400000>;
0462 opp-peak-kBps = <4068000 29491200>;
0463 };
0464
0465 cpu4_opp7: opp-1382400000 {
0466 opp-hz = /bits/ 64 <1382400000>;
0467 opp-peak-kBps = <4068000 32563200>;
0468 };
0469
0470 cpu4_opp8: opp-1478400000 {
0471 opp-hz = /bits/ 64 <1478400000>;
0472 opp-peak-kBps = <4068000 32563200>;
0473 };
0474
0475 cpu4_opp9: opp-1574400000 {
0476 opp-hz = /bits/ 64 <1574400000>;
0477 opp-peak-kBps = <5412000 39321600>;
0478 };
0479
0480 cpu4_opp10: opp-1670400000 {
0481 opp-hz = /bits/ 64 <1670400000>;
0482 opp-peak-kBps = <5412000 42393600>;
0483 };
0484
0485 cpu4_opp11: opp-1766400000 {
0486 opp-hz = /bits/ 64 <1766400000>;
0487 opp-peak-kBps = <5412000 45465600>;
0488 };
0489
0490 cpu4_opp12: opp-1862400000 {
0491 opp-hz = /bits/ 64 <1862400000>;
0492 opp-peak-kBps = <6220000 45465600>;
0493 };
0494
0495 cpu4_opp13: opp-1958400000 {
0496 opp-hz = /bits/ 64 <1958400000>;
0497 opp-peak-kBps = <6220000 48537600>;
0498 };
0499
0500 cpu4_opp14: opp-2054400000 {
0501 opp-hz = /bits/ 64 <2054400000>;
0502 opp-peak-kBps = <7216000 48537600>;
0503 };
0504
0505 cpu4_opp15: opp-2150400000 {
0506 opp-hz = /bits/ 64 <2150400000>;
0507 opp-peak-kBps = <7216000 51609600>;
0508 };
0509
0510 cpu4_opp16: opp-2246400000 {
0511 opp-hz = /bits/ 64 <2246400000>;
0512 opp-peak-kBps = <7216000 51609600>;
0513 };
0514
0515 cpu4_opp17: opp-2342400000 {
0516 opp-hz = /bits/ 64 <2342400000>;
0517 opp-peak-kBps = <8368000 51609600>;
0518 };
0519
0520 cpu4_opp18: opp-2419200000 {
0521 opp-hz = /bits/ 64 <2419200000>;
0522 opp-peak-kBps = <8368000 51609600>;
0523 };
0524 };
0525
0526 cpu7_opp_table: opp-table-cpu7 {
0527 compatible = "operating-points-v2";
0528 opp-shared;
0529
0530 cpu7_opp1: opp-844800000 {
0531 opp-hz = /bits/ 64 <844800000>;
0532 opp-peak-kBps = <2188000 19660800>;
0533 };
0534
0535 cpu7_opp2: opp-960000000 {
0536 opp-hz = /bits/ 64 <960000000>;
0537 opp-peak-kBps = <2188000 26419200>;
0538 };
0539
0540 cpu7_opp3: opp-1075200000 {
0541 opp-hz = /bits/ 64 <1075200000>;
0542 opp-peak-kBps = <3072000 26419200>;
0543 };
0544
0545 cpu7_opp4: opp-1190400000 {
0546 opp-hz = /bits/ 64 <1190400000>;
0547 opp-peak-kBps = <3072000 29491200>;
0548 };
0549
0550 cpu7_opp5: opp-1305600000 {
0551 opp-hz = /bits/ 64 <1305600000>;
0552 opp-peak-kBps = <4068000 32563200>;
0553 };
0554
0555 cpu7_opp6: opp-1401600000 {
0556 opp-hz = /bits/ 64 <1401600000>;
0557 opp-peak-kBps = <4068000 32563200>;
0558 };
0559
0560 cpu7_opp7: opp-1516800000 {
0561 opp-hz = /bits/ 64 <1516800000>;
0562 opp-peak-kBps = <4068000 36249600>;
0563 };
0564
0565 cpu7_opp8: opp-1632000000 {
0566 opp-hz = /bits/ 64 <1632000000>;
0567 opp-peak-kBps = <5412000 39321600>;
0568 };
0569
0570 cpu7_opp9: opp-1747200000 {
0571 opp-hz = /bits/ 64 <1708800000>;
0572 opp-peak-kBps = <5412000 42393600>;
0573 };
0574
0575 cpu7_opp10: opp-1862400000 {
0576 opp-hz = /bits/ 64 <1862400000>;
0577 opp-peak-kBps = <6220000 45465600>;
0578 };
0579
0580 cpu7_opp11: opp-1977600000 {
0581 opp-hz = /bits/ 64 <1977600000>;
0582 opp-peak-kBps = <6220000 48537600>;
0583 };
0584
0585 cpu7_opp12: opp-2073600000 {
0586 opp-hz = /bits/ 64 <2073600000>;
0587 opp-peak-kBps = <7216000 48537600>;
0588 };
0589
0590 cpu7_opp13: opp-2169600000 {
0591 opp-hz = /bits/ 64 <2169600000>;
0592 opp-peak-kBps = <7216000 51609600>;
0593 };
0594
0595 cpu7_opp14: opp-2265600000 {
0596 opp-hz = /bits/ 64 <2265600000>;
0597 opp-peak-kBps = <7216000 51609600>;
0598 };
0599
0600 cpu7_opp15: opp-2361600000 {
0601 opp-hz = /bits/ 64 <2361600000>;
0602 opp-peak-kBps = <8368000 51609600>;
0603 };
0604
0605 cpu7_opp16: opp-2457600000 {
0606 opp-hz = /bits/ 64 <2457600000>;
0607 opp-peak-kBps = <8368000 51609600>;
0608 };
0609
0610 cpu7_opp17: opp-2553600000 {
0611 opp-hz = /bits/ 64 <2553600000>;
0612 opp-peak-kBps = <8368000 51609600>;
0613 };
0614
0615 cpu7_opp18: opp-2649600000 {
0616 opp-hz = /bits/ 64 <2649600000>;
0617 opp-peak-kBps = <8368000 51609600>;
0618 };
0619
0620 cpu7_opp19: opp-2745600000 {
0621 opp-hz = /bits/ 64 <2745600000>;
0622 opp-peak-kBps = <8368000 51609600>;
0623 };
0624
0625 cpu7_opp20: opp-2841600000 {
0626 opp-hz = /bits/ 64 <2841600000>;
0627 opp-peak-kBps = <8368000 51609600>;
0628 };
0629 };
0630
0631 firmware {
0632 scm: scm {
0633 compatible = "qcom,scm-sm8250", "qcom,scm";
0634 #reset-cells = <1>;
0635 };
0636 };
0637
0638 memory@80000000 {
0639 device_type = "memory";
0640 /* We expect the bootloader to fill in the size */
0641 reg = <0x0 0x80000000 0x0 0x0>;
0642 };
0643
0644 pmu {
0645 compatible = "arm,armv8-pmuv3";
0646 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
0647 };
0648
0649 psci {
0650 compatible = "arm,psci-1.0";
0651 method = "smc";
0652
0653 CPU_PD0: cpu0 {
0654 #power-domain-cells = <0>;
0655 power-domains = <&CLUSTER_PD>;
0656 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0657 };
0658
0659 CPU_PD1: cpu1 {
0660 #power-domain-cells = <0>;
0661 power-domains = <&CLUSTER_PD>;
0662 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0663 };
0664
0665 CPU_PD2: cpu2 {
0666 #power-domain-cells = <0>;
0667 power-domains = <&CLUSTER_PD>;
0668 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0669 };
0670
0671 CPU_PD3: cpu3 {
0672 #power-domain-cells = <0>;
0673 power-domains = <&CLUSTER_PD>;
0674 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0675 };
0676
0677 CPU_PD4: cpu4 {
0678 #power-domain-cells = <0>;
0679 power-domains = <&CLUSTER_PD>;
0680 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0681 };
0682
0683 CPU_PD5: cpu5 {
0684 #power-domain-cells = <0>;
0685 power-domains = <&CLUSTER_PD>;
0686 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0687 };
0688
0689 CPU_PD6: cpu6 {
0690 #power-domain-cells = <0>;
0691 power-domains = <&CLUSTER_PD>;
0692 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0693 };
0694
0695 CPU_PD7: cpu7 {
0696 #power-domain-cells = <0>;
0697 power-domains = <&CLUSTER_PD>;
0698 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0699 };
0700
0701 CLUSTER_PD: cpu-cluster0 {
0702 #power-domain-cells = <0>;
0703 domain-idle-states = <&CLUSTER_SLEEP_0>;
0704 };
0705 };
0706
0707 qup_opp_table: opp-table-qup {
0708 compatible = "operating-points-v2";
0709
0710 opp-50000000 {
0711 opp-hz = /bits/ 64 <50000000>;
0712 required-opps = <&rpmhpd_opp_min_svs>;
0713 };
0714
0715 opp-75000000 {
0716 opp-hz = /bits/ 64 <75000000>;
0717 required-opps = <&rpmhpd_opp_low_svs>;
0718 };
0719
0720 opp-120000000 {
0721 opp-hz = /bits/ 64 <120000000>;
0722 required-opps = <&rpmhpd_opp_svs>;
0723 };
0724 };
0725
0726 reserved-memory {
0727 #address-cells = <2>;
0728 #size-cells = <2>;
0729 ranges;
0730
0731 hyp_mem: memory@80000000 {
0732 reg = <0x0 0x80000000 0x0 0x600000>;
0733 no-map;
0734 };
0735
0736 xbl_aop_mem: memory@80700000 {
0737 reg = <0x0 0x80700000 0x0 0x160000>;
0738 no-map;
0739 };
0740
0741 cmd_db: memory@80860000 {
0742 compatible = "qcom,cmd-db";
0743 reg = <0x0 0x80860000 0x0 0x20000>;
0744 no-map;
0745 };
0746
0747 smem_mem: memory@80900000 {
0748 reg = <0x0 0x80900000 0x0 0x200000>;
0749 no-map;
0750 };
0751
0752 removed_mem: memory@80b00000 {
0753 reg = <0x0 0x80b00000 0x0 0x5300000>;
0754 no-map;
0755 };
0756
0757 camera_mem: memory@86200000 {
0758 reg = <0x0 0x86200000 0x0 0x500000>;
0759 no-map;
0760 };
0761
0762 wlan_mem: memory@86700000 {
0763 reg = <0x0 0x86700000 0x0 0x100000>;
0764 no-map;
0765 };
0766
0767 ipa_fw_mem: memory@86800000 {
0768 reg = <0x0 0x86800000 0x0 0x10000>;
0769 no-map;
0770 };
0771
0772 ipa_gsi_mem: memory@86810000 {
0773 reg = <0x0 0x86810000 0x0 0xa000>;
0774 no-map;
0775 };
0776
0777 gpu_mem: memory@8681a000 {
0778 reg = <0x0 0x8681a000 0x0 0x2000>;
0779 no-map;
0780 };
0781
0782 npu_mem: memory@86900000 {
0783 reg = <0x0 0x86900000 0x0 0x500000>;
0784 no-map;
0785 };
0786
0787 video_mem: memory@86e00000 {
0788 reg = <0x0 0x86e00000 0x0 0x500000>;
0789 no-map;
0790 };
0791
0792 cvp_mem: memory@87300000 {
0793 reg = <0x0 0x87300000 0x0 0x500000>;
0794 no-map;
0795 };
0796
0797 cdsp_mem: memory@87800000 {
0798 reg = <0x0 0x87800000 0x0 0x1400000>;
0799 no-map;
0800 };
0801
0802 slpi_mem: memory@88c00000 {
0803 reg = <0x0 0x88c00000 0x0 0x1500000>;
0804 no-map;
0805 };
0806
0807 adsp_mem: memory@8a100000 {
0808 reg = <0x0 0x8a100000 0x0 0x1d00000>;
0809 no-map;
0810 };
0811
0812 spss_mem: memory@8be00000 {
0813 reg = <0x0 0x8be00000 0x0 0x100000>;
0814 no-map;
0815 };
0816
0817 cdsp_secure_heap: memory@8bf00000 {
0818 reg = <0x0 0x8bf00000 0x0 0x4600000>;
0819 no-map;
0820 };
0821 };
0822
0823 smem {
0824 compatible = "qcom,smem";
0825 memory-region = <&smem_mem>;
0826 hwlocks = <&tcsr_mutex 3>;
0827 };
0828
0829 smp2p-adsp {
0830 compatible = "qcom,smp2p";
0831 qcom,smem = <443>, <429>;
0832 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
0833 IPCC_MPROC_SIGNAL_SMP2P
0834 IRQ_TYPE_EDGE_RISING>;
0835 mboxes = <&ipcc IPCC_CLIENT_LPASS
0836 IPCC_MPROC_SIGNAL_SMP2P>;
0837
0838 qcom,local-pid = <0>;
0839 qcom,remote-pid = <2>;
0840
0841 smp2p_adsp_out: master-kernel {
0842 qcom,entry-name = "master-kernel";
0843 #qcom,smem-state-cells = <1>;
0844 };
0845
0846 smp2p_adsp_in: slave-kernel {
0847 qcom,entry-name = "slave-kernel";
0848 interrupt-controller;
0849 #interrupt-cells = <2>;
0850 };
0851 };
0852
0853 smp2p-cdsp {
0854 compatible = "qcom,smp2p";
0855 qcom,smem = <94>, <432>;
0856 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
0857 IPCC_MPROC_SIGNAL_SMP2P
0858 IRQ_TYPE_EDGE_RISING>;
0859 mboxes = <&ipcc IPCC_CLIENT_CDSP
0860 IPCC_MPROC_SIGNAL_SMP2P>;
0861
0862 qcom,local-pid = <0>;
0863 qcom,remote-pid = <5>;
0864
0865 smp2p_cdsp_out: master-kernel {
0866 qcom,entry-name = "master-kernel";
0867 #qcom,smem-state-cells = <1>;
0868 };
0869
0870 smp2p_cdsp_in: slave-kernel {
0871 qcom,entry-name = "slave-kernel";
0872 interrupt-controller;
0873 #interrupt-cells = <2>;
0874 };
0875 };
0876
0877 smp2p-slpi {
0878 compatible = "qcom,smp2p";
0879 qcom,smem = <481>, <430>;
0880 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
0881 IPCC_MPROC_SIGNAL_SMP2P
0882 IRQ_TYPE_EDGE_RISING>;
0883 mboxes = <&ipcc IPCC_CLIENT_SLPI
0884 IPCC_MPROC_SIGNAL_SMP2P>;
0885
0886 qcom,local-pid = <0>;
0887 qcom,remote-pid = <3>;
0888
0889 smp2p_slpi_out: master-kernel {
0890 qcom,entry-name = "master-kernel";
0891 #qcom,smem-state-cells = <1>;
0892 };
0893
0894 smp2p_slpi_in: slave-kernel {
0895 qcom,entry-name = "slave-kernel";
0896 interrupt-controller;
0897 #interrupt-cells = <2>;
0898 };
0899 };
0900
0901 soc: soc@0 {
0902 #address-cells = <2>;
0903 #size-cells = <2>;
0904 ranges = <0 0 0 0 0x10 0>;
0905 dma-ranges = <0 0 0 0 0x10 0>;
0906 compatible = "simple-bus";
0907
0908 gcc: clock-controller@100000 {
0909 compatible = "qcom,gcc-sm8250";
0910 reg = <0x0 0x00100000 0x0 0x1f0000>;
0911 #clock-cells = <1>;
0912 #reset-cells = <1>;
0913 #power-domain-cells = <1>;
0914 clock-names = "bi_tcxo",
0915 "bi_tcxo_ao",
0916 "sleep_clk";
0917 clocks = <&rpmhcc RPMH_CXO_CLK>,
0918 <&rpmhcc RPMH_CXO_CLK_A>,
0919 <&sleep_clk>;
0920 };
0921
0922 ipcc: mailbox@408000 {
0923 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
0924 reg = <0 0x00408000 0 0x1000>;
0925 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
0926 interrupt-controller;
0927 #interrupt-cells = <3>;
0928 #mbox-cells = <2>;
0929 };
0930
0931 rng: rng@793000 {
0932 compatible = "qcom,prng-ee";
0933 reg = <0 0x00793000 0 0x1000>;
0934 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0935 clock-names = "core";
0936 };
0937
0938 gpi_dma2: dma-controller@800000 {
0939 compatible = "qcom,sm8250-gpi-dma";
0940 reg = <0 0x00800000 0 0x70000>;
0941 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
0942 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
0943 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
0944 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
0945 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
0946 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
0947 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
0948 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
0949 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
0950 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
0951 dma-channels = <10>;
0952 dma-channel-mask = <0x3f>;
0953 iommus = <&apps_smmu 0x76 0x0>;
0954 #dma-cells = <3>;
0955 status = "disabled";
0956 };
0957
0958 qupv3_id_2: geniqup@8c0000 {
0959 compatible = "qcom,geni-se-qup";
0960 reg = <0x0 0x008c0000 0x0 0x6000>;
0961 clock-names = "m-ahb", "s-ahb";
0962 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
0963 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
0964 #address-cells = <2>;
0965 #size-cells = <2>;
0966 iommus = <&apps_smmu 0x63 0x0>;
0967 ranges;
0968 status = "disabled";
0969
0970 i2c14: i2c@880000 {
0971 compatible = "qcom,geni-i2c";
0972 reg = <0 0x00880000 0 0x4000>;
0973 clock-names = "se";
0974 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
0975 pinctrl-names = "default";
0976 pinctrl-0 = <&qup_i2c14_default>;
0977 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
0978 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
0979 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
0980 dma-names = "tx", "rx";
0981 #address-cells = <1>;
0982 #size-cells = <0>;
0983 status = "disabled";
0984 };
0985
0986 spi14: spi@880000 {
0987 compatible = "qcom,geni-spi";
0988 reg = <0 0x00880000 0 0x4000>;
0989 clock-names = "se";
0990 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
0991 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
0992 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
0993 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
0994 dma-names = "tx", "rx";
0995 power-domains = <&rpmhpd SM8250_CX>;
0996 operating-points-v2 = <&qup_opp_table>;
0997 #address-cells = <1>;
0998 #size-cells = <0>;
0999 status = "disabled";
1000 };
1001
1002 i2c15: i2c@884000 {
1003 compatible = "qcom,geni-i2c";
1004 reg = <0 0x00884000 0 0x4000>;
1005 clock-names = "se";
1006 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_i2c15_default>;
1009 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1010 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1011 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1012 dma-names = "tx", "rx";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 status = "disabled";
1016 };
1017
1018 spi15: spi@884000 {
1019 compatible = "qcom,geni-spi";
1020 reg = <0 0x00884000 0 0x4000>;
1021 clock-names = "se";
1022 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1023 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1024 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1025 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1026 dma-names = "tx", "rx";
1027 power-domains = <&rpmhpd SM8250_CX>;
1028 operating-points-v2 = <&qup_opp_table>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 status = "disabled";
1032 };
1033
1034 i2c16: i2c@888000 {
1035 compatible = "qcom,geni-i2c";
1036 reg = <0 0x00888000 0 0x4000>;
1037 clock-names = "se";
1038 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&qup_i2c16_default>;
1041 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1042 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1043 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1044 dma-names = "tx", "rx";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 status = "disabled";
1048 };
1049
1050 spi16: spi@888000 {
1051 compatible = "qcom,geni-spi";
1052 reg = <0 0x00888000 0 0x4000>;
1053 clock-names = "se";
1054 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1055 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1056 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1057 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1058 dma-names = "tx", "rx";
1059 power-domains = <&rpmhpd SM8250_CX>;
1060 operating-points-v2 = <&qup_opp_table>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 status = "disabled";
1064 };
1065
1066 i2c17: i2c@88c000 {
1067 compatible = "qcom,geni-i2c";
1068 reg = <0 0x0088c000 0 0x4000>;
1069 clock-names = "se";
1070 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_i2c17_default>;
1073 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1075 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079 status = "disabled";
1080 };
1081
1082 spi17: spi@88c000 {
1083 compatible = "qcom,geni-spi";
1084 reg = <0 0x0088c000 0 0x4000>;
1085 clock-names = "se";
1086 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1087 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1088 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1089 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1090 dma-names = "tx", "rx";
1091 power-domains = <&rpmhpd SM8250_CX>;
1092 operating-points-v2 = <&qup_opp_table>;
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1095 status = "disabled";
1096 };
1097
1098 uart17: serial@88c000 {
1099 compatible = "qcom,geni-uart";
1100 reg = <0 0x0088c000 0 0x4000>;
1101 clock-names = "se";
1102 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&qup_uart17_default>;
1105 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1106 power-domains = <&rpmhpd SM8250_CX>;
1107 operating-points-v2 = <&qup_opp_table>;
1108 status = "disabled";
1109 };
1110
1111 i2c18: i2c@890000 {
1112 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00890000 0 0x4000>;
1114 clock-names = "se";
1115 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c18_default>;
1118 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1120 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1124 status = "disabled";
1125 };
1126
1127 spi18: spi@890000 {
1128 compatible = "qcom,geni-spi";
1129 reg = <0 0x00890000 0 0x4000>;
1130 clock-names = "se";
1131 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1132 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1133 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1134 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1135 dma-names = "tx", "rx";
1136 power-domains = <&rpmhpd SM8250_CX>;
1137 operating-points-v2 = <&qup_opp_table>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 status = "disabled";
1141 };
1142
1143 uart18: serial@890000 {
1144 compatible = "qcom,geni-uart";
1145 reg = <0 0x00890000 0 0x4000>;
1146 clock-names = "se";
1147 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_uart18_default>;
1150 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1151 power-domains = <&rpmhpd SM8250_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1153 status = "disabled";
1154 };
1155
1156 i2c19: i2c@894000 {
1157 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00894000 0 0x4000>;
1159 clock-names = "se";
1160 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c19_default>;
1163 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1165 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1166 dma-names = "tx", "rx";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1169 status = "disabled";
1170 };
1171
1172 spi19: spi@894000 {
1173 compatible = "qcom,geni-spi";
1174 reg = <0 0x00894000 0 0x4000>;
1175 clock-names = "se";
1176 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1177 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1178 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1179 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1180 dma-names = "tx", "rx";
1181 power-domains = <&rpmhpd SM8250_CX>;
1182 operating-points-v2 = <&qup_opp_table>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 status = "disabled";
1186 };
1187 };
1188
1189 gpi_dma0: dma-controller@900000 {
1190 compatible = "qcom,sm8250-gpi-dma";
1191 reg = <0 0x00900000 0 0x70000>;
1192 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1205 dma-channels = <15>;
1206 dma-channel-mask = <0x7ff>;
1207 iommus = <&apps_smmu 0x5b6 0x0>;
1208 #dma-cells = <3>;
1209 status = "disabled";
1210 };
1211
1212 qupv3_id_0: geniqup@9c0000 {
1213 compatible = "qcom,geni-se-qup";
1214 reg = <0x0 0x009c0000 0x0 0x6000>;
1215 clock-names = "m-ahb", "s-ahb";
1216 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1217 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1218 #address-cells = <2>;
1219 #size-cells = <2>;
1220 iommus = <&apps_smmu 0x5a3 0x0>;
1221 ranges;
1222 status = "disabled";
1223
1224 i2c0: i2c@980000 {
1225 compatible = "qcom,geni-i2c";
1226 reg = <0 0x00980000 0 0x4000>;
1227 clock-names = "se";
1228 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_i2c0_default>;
1231 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1232 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1233 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1234 dma-names = "tx", "rx";
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1237 status = "disabled";
1238 };
1239
1240 spi0: spi@980000 {
1241 compatible = "qcom,geni-spi";
1242 reg = <0 0x00980000 0 0x4000>;
1243 clock-names = "se";
1244 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1245 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1246 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1247 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1248 dma-names = "tx", "rx";
1249 power-domains = <&rpmhpd SM8250_CX>;
1250 operating-points-v2 = <&qup_opp_table>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 status = "disabled";
1254 };
1255
1256 i2c1: i2c@984000 {
1257 compatible = "qcom,geni-i2c";
1258 reg = <0 0x00984000 0 0x4000>;
1259 clock-names = "se";
1260 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&qup_i2c1_default>;
1263 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1264 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1265 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1266 dma-names = "tx", "rx";
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1269 status = "disabled";
1270 };
1271
1272 spi1: spi@984000 {
1273 compatible = "qcom,geni-spi";
1274 reg = <0 0x00984000 0 0x4000>;
1275 clock-names = "se";
1276 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1277 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1278 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1279 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1280 dma-names = "tx", "rx";
1281 power-domains = <&rpmhpd SM8250_CX>;
1282 operating-points-v2 = <&qup_opp_table>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1285 status = "disabled";
1286 };
1287
1288 i2c2: i2c@988000 {
1289 compatible = "qcom,geni-i2c";
1290 reg = <0 0x00988000 0 0x4000>;
1291 clock-names = "se";
1292 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&qup_i2c2_default>;
1295 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1296 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1297 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1298 dma-names = "tx", "rx";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 status = "disabled";
1302 };
1303
1304 spi2: spi@988000 {
1305 compatible = "qcom,geni-spi";
1306 reg = <0 0x00988000 0 0x4000>;
1307 clock-names = "se";
1308 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1309 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1310 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1311 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1312 dma-names = "tx", "rx";
1313 power-domains = <&rpmhpd SM8250_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 status = "disabled";
1318 };
1319
1320 uart2: serial@988000 {
1321 compatible = "qcom,geni-debug-uart";
1322 reg = <0 0x00988000 0 0x4000>;
1323 clock-names = "se";
1324 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&qup_uart2_default>;
1327 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1328 power-domains = <&rpmhpd SM8250_CX>;
1329 operating-points-v2 = <&qup_opp_table>;
1330 status = "disabled";
1331 };
1332
1333 i2c3: i2c@98c000 {
1334 compatible = "qcom,geni-i2c";
1335 reg = <0 0x0098c000 0 0x4000>;
1336 clock-names = "se";
1337 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c3_default>;
1340 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1341 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1342 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1343 dma-names = "tx", "rx";
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1346 status = "disabled";
1347 };
1348
1349 spi3: spi@98c000 {
1350 compatible = "qcom,geni-spi";
1351 reg = <0 0x0098c000 0 0x4000>;
1352 clock-names = "se";
1353 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1354 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1356 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1357 dma-names = "tx", "rx";
1358 power-domains = <&rpmhpd SM8250_CX>;
1359 operating-points-v2 = <&qup_opp_table>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1364
1365 i2c4: i2c@990000 {
1366 compatible = "qcom,geni-i2c";
1367 reg = <0 0x00990000 0 0x4000>;
1368 clock-names = "se";
1369 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_i2c4_default>;
1372 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1373 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1374 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1375 dma-names = "tx", "rx";
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1378 status = "disabled";
1379 };
1380
1381 spi4: spi@990000 {
1382 compatible = "qcom,geni-spi";
1383 reg = <0 0x00990000 0 0x4000>;
1384 clock-names = "se";
1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1386 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1387 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1388 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1389 dma-names = "tx", "rx";
1390 power-domains = <&rpmhpd SM8250_CX>;
1391 operating-points-v2 = <&qup_opp_table>;
1392 #address-cells = <1>;
1393 #size-cells = <0>;
1394 status = "disabled";
1395 };
1396
1397 i2c5: i2c@994000 {
1398 compatible = "qcom,geni-i2c";
1399 reg = <0 0x00994000 0 0x4000>;
1400 clock-names = "se";
1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1402 pinctrl-names = "default";
1403 pinctrl-0 = <&qup_i2c5_default>;
1404 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1405 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1406 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1407 dma-names = "tx", "rx";
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1410 status = "disabled";
1411 };
1412
1413 spi5: spi@994000 {
1414 compatible = "qcom,geni-spi";
1415 reg = <0 0x00994000 0 0x4000>;
1416 clock-names = "se";
1417 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1418 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1419 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1420 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1421 dma-names = "tx", "rx";
1422 power-domains = <&rpmhpd SM8250_CX>;
1423 operating-points-v2 = <&qup_opp_table>;
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1426 status = "disabled";
1427 };
1428
1429 i2c6: i2c@998000 {
1430 compatible = "qcom,geni-i2c";
1431 reg = <0 0x00998000 0 0x4000>;
1432 clock-names = "se";
1433 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1434 pinctrl-names = "default";
1435 pinctrl-0 = <&qup_i2c6_default>;
1436 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1437 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1438 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1439 dma-names = "tx", "rx";
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1442 status = "disabled";
1443 };
1444
1445 spi6: spi@998000 {
1446 compatible = "qcom,geni-spi";
1447 reg = <0 0x00998000 0 0x4000>;
1448 clock-names = "se";
1449 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1450 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1452 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1453 dma-names = "tx", "rx";
1454 power-domains = <&rpmhpd SM8250_CX>;
1455 operating-points-v2 = <&qup_opp_table>;
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 status = "disabled";
1459 };
1460
1461 uart6: serial@998000 {
1462 compatible = "qcom,geni-uart";
1463 reg = <0 0x00998000 0 0x4000>;
1464 clock-names = "se";
1465 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_uart6_default>;
1468 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1469 power-domains = <&rpmhpd SM8250_CX>;
1470 operating-points-v2 = <&qup_opp_table>;
1471 status = "disabled";
1472 };
1473
1474 i2c7: i2c@99c000 {
1475 compatible = "qcom,geni-i2c";
1476 reg = <0 0x0099c000 0 0x4000>;
1477 clock-names = "se";
1478 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_i2c7_default>;
1481 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1482 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1483 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1484 dma-names = "tx", "rx";
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1487 status = "disabled";
1488 };
1489
1490 spi7: spi@99c000 {
1491 compatible = "qcom,geni-spi";
1492 reg = <0 0x0099c000 0 0x4000>;
1493 clock-names = "se";
1494 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1495 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1496 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1497 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1498 dma-names = "tx", "rx";
1499 power-domains = <&rpmhpd SM8250_CX>;
1500 operating-points-v2 = <&qup_opp_table>;
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503 status = "disabled";
1504 };
1505 };
1506
1507 gpi_dma1: dma-controller@a00000 {
1508 compatible = "qcom,sm8250-gpi-dma";
1509 reg = <0 0x00a00000 0 0x70000>;
1510 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1520 dma-channels = <10>;
1521 dma-channel-mask = <0x3f>;
1522 iommus = <&apps_smmu 0x56 0x0>;
1523 #dma-cells = <3>;
1524 status = "disabled";
1525 };
1526
1527 qupv3_id_1: geniqup@ac0000 {
1528 compatible = "qcom,geni-se-qup";
1529 reg = <0x0 0x00ac0000 0x0 0x6000>;
1530 clock-names = "m-ahb", "s-ahb";
1531 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1532 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1533 #address-cells = <2>;
1534 #size-cells = <2>;
1535 iommus = <&apps_smmu 0x43 0x0>;
1536 ranges;
1537 status = "disabled";
1538
1539 i2c8: i2c@a80000 {
1540 compatible = "qcom,geni-i2c";
1541 reg = <0 0x00a80000 0 0x4000>;
1542 clock-names = "se";
1543 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1544 pinctrl-names = "default";
1545 pinctrl-0 = <&qup_i2c8_default>;
1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1547 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1548 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1549 dma-names = "tx", "rx";
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1552 status = "disabled";
1553 };
1554
1555 spi8: spi@a80000 {
1556 compatible = "qcom,geni-spi";
1557 reg = <0 0x00a80000 0 0x4000>;
1558 clock-names = "se";
1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1560 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1561 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1562 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1563 dma-names = "tx", "rx";
1564 power-domains = <&rpmhpd SM8250_CX>;
1565 operating-points-v2 = <&qup_opp_table>;
1566 #address-cells = <1>;
1567 #size-cells = <0>;
1568 status = "disabled";
1569 };
1570
1571 i2c9: i2c@a84000 {
1572 compatible = "qcom,geni-i2c";
1573 reg = <0 0x00a84000 0 0x4000>;
1574 clock-names = "se";
1575 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1576 pinctrl-names = "default";
1577 pinctrl-0 = <&qup_i2c9_default>;
1578 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1580 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1581 dma-names = "tx", "rx";
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1584 status = "disabled";
1585 };
1586
1587 spi9: spi@a84000 {
1588 compatible = "qcom,geni-spi";
1589 reg = <0 0x00a84000 0 0x4000>;
1590 clock-names = "se";
1591 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1593 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1594 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1595 dma-names = "tx", "rx";
1596 power-domains = <&rpmhpd SM8250_CX>;
1597 operating-points-v2 = <&qup_opp_table>;
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1600 status = "disabled";
1601 };
1602
1603 i2c10: i2c@a88000 {
1604 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00a88000 0 0x4000>;
1606 clock-names = "se";
1607 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_i2c10_default>;
1610 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1612 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1613 dma-names = "tx", "rx";
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 status = "disabled";
1617 };
1618
1619 spi10: spi@a88000 {
1620 compatible = "qcom,geni-spi";
1621 reg = <0 0x00a88000 0 0x4000>;
1622 clock-names = "se";
1623 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1624 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1626 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1627 dma-names = "tx", "rx";
1628 power-domains = <&rpmhpd SM8250_CX>;
1629 operating-points-v2 = <&qup_opp_table>;
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1632 status = "disabled";
1633 };
1634
1635 i2c11: i2c@a8c000 {
1636 compatible = "qcom,geni-i2c";
1637 reg = <0 0x00a8c000 0 0x4000>;
1638 clock-names = "se";
1639 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1640 pinctrl-names = "default";
1641 pinctrl-0 = <&qup_i2c11_default>;
1642 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1644 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1645 dma-names = "tx", "rx";
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 status = "disabled";
1649 };
1650
1651 spi11: spi@a8c000 {
1652 compatible = "qcom,geni-spi";
1653 reg = <0 0x00a8c000 0 0x4000>;
1654 clock-names = "se";
1655 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1657 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1658 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1659 dma-names = "tx", "rx";
1660 power-domains = <&rpmhpd SM8250_CX>;
1661 operating-points-v2 = <&qup_opp_table>;
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1664 status = "disabled";
1665 };
1666
1667 i2c12: i2c@a90000 {
1668 compatible = "qcom,geni-i2c";
1669 reg = <0 0x00a90000 0 0x4000>;
1670 clock-names = "se";
1671 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1672 pinctrl-names = "default";
1673 pinctrl-0 = <&qup_i2c12_default>;
1674 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1675 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1676 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1677 dma-names = "tx", "rx";
1678 #address-cells = <1>;
1679 #size-cells = <0>;
1680 status = "disabled";
1681 };
1682
1683 spi12: spi@a90000 {
1684 compatible = "qcom,geni-spi";
1685 reg = <0 0x00a90000 0 0x4000>;
1686 clock-names = "se";
1687 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1688 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1689 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1690 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1691 dma-names = "tx", "rx";
1692 power-domains = <&rpmhpd SM8250_CX>;
1693 operating-points-v2 = <&qup_opp_table>;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1696 status = "disabled";
1697 };
1698
1699 uart12: serial@a90000 {
1700 compatible = "qcom,geni-debug-uart";
1701 reg = <0x0 0x00a90000 0x0 0x4000>;
1702 clock-names = "se";
1703 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_uart12_default>;
1706 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1707 power-domains = <&rpmhpd SM8250_CX>;
1708 operating-points-v2 = <&qup_opp_table>;
1709 status = "disabled";
1710 };
1711
1712 i2c13: i2c@a94000 {
1713 compatible = "qcom,geni-i2c";
1714 reg = <0 0x00a94000 0 0x4000>;
1715 clock-names = "se";
1716 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c13_default>;
1719 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1720 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1721 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1722 dma-names = "tx", "rx";
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1725 status = "disabled";
1726 };
1727
1728 spi13: spi@a94000 {
1729 compatible = "qcom,geni-spi";
1730 reg = <0 0x00a94000 0 0x4000>;
1731 clock-names = "se";
1732 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1733 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1734 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1735 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1736 dma-names = "tx", "rx";
1737 power-domains = <&rpmhpd SM8250_CX>;
1738 operating-points-v2 = <&qup_opp_table>;
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1741 status = "disabled";
1742 };
1743 };
1744
1745 config_noc: interconnect@1500000 {
1746 compatible = "qcom,sm8250-config-noc";
1747 reg = <0 0x01500000 0 0xa580>;
1748 #interconnect-cells = <1>;
1749 qcom,bcm-voters = <&apps_bcm_voter>;
1750 };
1751
1752 system_noc: interconnect@1620000 {
1753 compatible = "qcom,sm8250-system-noc";
1754 reg = <0 0x01620000 0 0x1c200>;
1755 #interconnect-cells = <1>;
1756 qcom,bcm-voters = <&apps_bcm_voter>;
1757 };
1758
1759 mc_virt: interconnect@163d000 {
1760 compatible = "qcom,sm8250-mc-virt";
1761 reg = <0 0x0163d000 0 0x1000>;
1762 #interconnect-cells = <1>;
1763 qcom,bcm-voters = <&apps_bcm_voter>;
1764 };
1765
1766 aggre1_noc: interconnect@16e0000 {
1767 compatible = "qcom,sm8250-aggre1-noc";
1768 reg = <0 0x016e0000 0 0x1f180>;
1769 #interconnect-cells = <1>;
1770 qcom,bcm-voters = <&apps_bcm_voter>;
1771 };
1772
1773 aggre2_noc: interconnect@1700000 {
1774 compatible = "qcom,sm8250-aggre2-noc";
1775 reg = <0 0x01700000 0 0x33000>;
1776 #interconnect-cells = <1>;
1777 qcom,bcm-voters = <&apps_bcm_voter>;
1778 };
1779
1780 compute_noc: interconnect@1733000 {
1781 compatible = "qcom,sm8250-compute-noc";
1782 reg = <0 0x01733000 0 0xa180>;
1783 #interconnect-cells = <1>;
1784 qcom,bcm-voters = <&apps_bcm_voter>;
1785 };
1786
1787 mmss_noc: interconnect@1740000 {
1788 compatible = "qcom,sm8250-mmss-noc";
1789 reg = <0 0x01740000 0 0x1f080>;
1790 #interconnect-cells = <1>;
1791 qcom,bcm-voters = <&apps_bcm_voter>;
1792 };
1793
1794 pcie0: pci@1c00000 {
1795 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1796 reg = <0 0x01c00000 0 0x3000>,
1797 <0 0x60000000 0 0xf1d>,
1798 <0 0x60000f20 0 0xa8>,
1799 <0 0x60001000 0 0x1000>,
1800 <0 0x60100000 0 0x100000>;
1801 reg-names = "parf", "dbi", "elbi", "atu", "config";
1802 device_type = "pci";
1803 linux,pci-domain = <0>;
1804 bus-range = <0x00 0xff>;
1805 num-lanes = <1>;
1806
1807 #address-cells = <3>;
1808 #size-cells = <2>;
1809
1810 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1811 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1812
1813 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1814 interrupt-names = "msi";
1815 #interrupt-cells = <1>;
1816 interrupt-map-mask = <0 0 0 0x7>;
1817 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1818 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1819 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1820 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1821
1822 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1823 <&gcc GCC_PCIE_0_AUX_CLK>,
1824 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1825 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1826 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1827 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1828 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1829 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1830 clock-names = "pipe",
1831 "aux",
1832 "cfg",
1833 "bus_master",
1834 "bus_slave",
1835 "slave_q2a",
1836 "tbu",
1837 "ddrss_sf_tbu";
1838
1839 iommus = <&apps_smmu 0x1c00 0x7f>;
1840 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1841 <0x100 &apps_smmu 0x1c01 0x1>;
1842
1843 resets = <&gcc GCC_PCIE_0_BCR>;
1844 reset-names = "pci";
1845
1846 power-domains = <&gcc PCIE_0_GDSC>;
1847
1848 phys = <&pcie0_lane>;
1849 phy-names = "pciephy";
1850
1851 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1852 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1853
1854 pinctrl-names = "default";
1855 pinctrl-0 = <&pcie0_default_state>;
1856
1857 status = "disabled";
1858 };
1859
1860 pcie0_phy: phy@1c06000 {
1861 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1862 reg = <0 0x01c06000 0 0x1c0>;
1863 #address-cells = <2>;
1864 #size-cells = <2>;
1865 ranges;
1866 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1867 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1868 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1869 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1870 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1871
1872 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1873 reset-names = "phy";
1874
1875 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1876 assigned-clock-rates = <100000000>;
1877
1878 status = "disabled";
1879
1880 pcie0_lane: phy@1c06200 {
1881 reg = <0 0x1c06200 0 0x170>, /* tx */
1882 <0 0x1c06400 0 0x200>, /* rx */
1883 <0 0x1c06800 0 0x1f0>, /* pcs */
1884 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1885 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1886 clock-names = "pipe0";
1887
1888 #phy-cells = <0>;
1889
1890 #clock-cells = <0>;
1891 clock-output-names = "pcie_0_pipe_clk";
1892 };
1893 };
1894
1895 pcie1: pci@1c08000 {
1896 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1897 reg = <0 0x01c08000 0 0x3000>,
1898 <0 0x40000000 0 0xf1d>,
1899 <0 0x40000f20 0 0xa8>,
1900 <0 0x40001000 0 0x1000>,
1901 <0 0x40100000 0 0x100000>;
1902 reg-names = "parf", "dbi", "elbi", "atu", "config";
1903 device_type = "pci";
1904 linux,pci-domain = <1>;
1905 bus-range = <0x00 0xff>;
1906 num-lanes = <2>;
1907
1908 #address-cells = <3>;
1909 #size-cells = <2>;
1910
1911 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1912 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1913
1914 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1915 interrupt-names = "msi";
1916 #interrupt-cells = <1>;
1917 interrupt-map-mask = <0 0 0 0x7>;
1918 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1919 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1920 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1921 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1922
1923 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1924 <&gcc GCC_PCIE_1_AUX_CLK>,
1925 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1926 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1927 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1928 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1929 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1930 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1931 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1932 clock-names = "pipe",
1933 "aux",
1934 "cfg",
1935 "bus_master",
1936 "bus_slave",
1937 "slave_q2a",
1938 "ref",
1939 "tbu",
1940 "ddrss_sf_tbu";
1941
1942 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1943 assigned-clock-rates = <19200000>;
1944
1945 iommus = <&apps_smmu 0x1c80 0x7f>;
1946 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1947 <0x100 &apps_smmu 0x1c81 0x1>;
1948
1949 resets = <&gcc GCC_PCIE_1_BCR>;
1950 reset-names = "pci";
1951
1952 power-domains = <&gcc PCIE_1_GDSC>;
1953
1954 phys = <&pcie1_lane>;
1955 phy-names = "pciephy";
1956
1957 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1958 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1959
1960 pinctrl-names = "default";
1961 pinctrl-0 = <&pcie1_default_state>;
1962
1963 status = "disabled";
1964 };
1965
1966 pcie1_phy: phy@1c0e000 {
1967 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1968 reg = <0 0x01c0e000 0 0x1c0>;
1969 #address-cells = <2>;
1970 #size-cells = <2>;
1971 ranges;
1972 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1973 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1974 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1975 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1976 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1977
1978 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1979 reset-names = "phy";
1980
1981 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1982 assigned-clock-rates = <100000000>;
1983
1984 status = "disabled";
1985
1986 pcie1_lane: phy@1c0e200 {
1987 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1988 <0 0x1c0e400 0 0x200>, /* rx0 */
1989 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1990 <0 0x1c0e600 0 0x170>, /* tx1 */
1991 <0 0x1c0e800 0 0x200>, /* rx1 */
1992 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1993 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1994 clock-names = "pipe0";
1995
1996 #phy-cells = <0>;
1997
1998 #clock-cells = <0>;
1999 clock-output-names = "pcie_1_pipe_clk";
2000 };
2001 };
2002
2003 pcie2: pci@1c10000 {
2004 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2005 reg = <0 0x01c10000 0 0x3000>,
2006 <0 0x64000000 0 0xf1d>,
2007 <0 0x64000f20 0 0xa8>,
2008 <0 0x64001000 0 0x1000>,
2009 <0 0x64100000 0 0x100000>;
2010 reg-names = "parf", "dbi", "elbi", "atu", "config";
2011 device_type = "pci";
2012 linux,pci-domain = <2>;
2013 bus-range = <0x00 0xff>;
2014 num-lanes = <2>;
2015
2016 #address-cells = <3>;
2017 #size-cells = <2>;
2018
2019 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2020 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2021
2022 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2023 interrupt-names = "msi";
2024 #interrupt-cells = <1>;
2025 interrupt-map-mask = <0 0 0 0x7>;
2026 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2027 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2028 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2029 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2030
2031 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2032 <&gcc GCC_PCIE_2_AUX_CLK>,
2033 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2034 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2035 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2036 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2037 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2038 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2039 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2040 clock-names = "pipe",
2041 "aux",
2042 "cfg",
2043 "bus_master",
2044 "bus_slave",
2045 "slave_q2a",
2046 "ref",
2047 "tbu",
2048 "ddrss_sf_tbu";
2049
2050 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2051 assigned-clock-rates = <19200000>;
2052
2053 iommus = <&apps_smmu 0x1d00 0x7f>;
2054 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2055 <0x100 &apps_smmu 0x1d01 0x1>;
2056
2057 resets = <&gcc GCC_PCIE_2_BCR>;
2058 reset-names = "pci";
2059
2060 power-domains = <&gcc PCIE_2_GDSC>;
2061
2062 phys = <&pcie2_lane>;
2063 phy-names = "pciephy";
2064
2065 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2066 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2067
2068 pinctrl-names = "default";
2069 pinctrl-0 = <&pcie2_default_state>;
2070
2071 status = "disabled";
2072 };
2073
2074 pcie2_phy: phy@1c16000 {
2075 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2076 reg = <0 0x1c16000 0 0x1c0>;
2077 #address-cells = <2>;
2078 #size-cells = <2>;
2079 ranges;
2080 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2081 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2082 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2083 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2084 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2085
2086 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2087 reset-names = "phy";
2088
2089 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2090 assigned-clock-rates = <100000000>;
2091
2092 status = "disabled";
2093
2094 pcie2_lane: phy@1c16200 {
2095 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2096 <0 0x1c16400 0 0x200>, /* rx0 */
2097 <0 0x1c16a00 0 0x1f0>, /* pcs */
2098 <0 0x1c16600 0 0x170>, /* tx1 */
2099 <0 0x1c16800 0 0x200>, /* rx1 */
2100 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2101 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2102 clock-names = "pipe0";
2103
2104 #phy-cells = <0>;
2105
2106 #clock-cells = <0>;
2107 clock-output-names = "pcie_2_pipe_clk";
2108 };
2109 };
2110
2111 ufs_mem_hc: ufshc@1d84000 {
2112 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2113 "jedec,ufs-2.0";
2114 reg = <0 0x01d84000 0 0x3000>;
2115 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2116 phys = <&ufs_mem_phy_lanes>;
2117 phy-names = "ufsphy";
2118 lanes-per-direction = <2>;
2119 #reset-cells = <1>;
2120 resets = <&gcc GCC_UFS_PHY_BCR>;
2121 reset-names = "rst";
2122
2123 power-domains = <&gcc UFS_PHY_GDSC>;
2124
2125 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2126
2127 clock-names =
2128 "core_clk",
2129 "bus_aggr_clk",
2130 "iface_clk",
2131 "core_clk_unipro",
2132 "ref_clk",
2133 "tx_lane0_sync_clk",
2134 "rx_lane0_sync_clk",
2135 "rx_lane1_sync_clk";
2136 clocks =
2137 <&gcc GCC_UFS_PHY_AXI_CLK>,
2138 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2139 <&gcc GCC_UFS_PHY_AHB_CLK>,
2140 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2141 <&rpmhcc RPMH_CXO_CLK>,
2142 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2143 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2144 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2145 freq-table-hz =
2146 <37500000 300000000>,
2147 <0 0>,
2148 <0 0>,
2149 <37500000 300000000>,
2150 <0 0>,
2151 <0 0>,
2152 <0 0>,
2153 <0 0>;
2154
2155 status = "disabled";
2156 };
2157
2158 ufs_mem_phy: phy@1d87000 {
2159 compatible = "qcom,sm8250-qmp-ufs-phy";
2160 reg = <0 0x01d87000 0 0x1c0>;
2161 #address-cells = <2>;
2162 #size-cells = <2>;
2163 ranges;
2164 clock-names = "ref",
2165 "ref_aux";
2166 clocks = <&rpmhcc RPMH_CXO_CLK>,
2167 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2168
2169 resets = <&ufs_mem_hc 0>;
2170 reset-names = "ufsphy";
2171 status = "disabled";
2172
2173 ufs_mem_phy_lanes: phy@1d87400 {
2174 reg = <0 0x01d87400 0 0x108>,
2175 <0 0x01d87600 0 0x1e0>,
2176 <0 0x01d87c00 0 0x1dc>,
2177 <0 0x01d87800 0 0x108>,
2178 <0 0x01d87a00 0 0x1e0>;
2179 #phy-cells = <0>;
2180 };
2181 };
2182
2183 ipa_virt: interconnect@1e00000 {
2184 compatible = "qcom,sm8250-ipa-virt";
2185 reg = <0 0x01e00000 0 0x1000>;
2186 #interconnect-cells = <1>;
2187 qcom,bcm-voters = <&apps_bcm_voter>;
2188 };
2189
2190 tcsr_mutex: hwlock@1f40000 {
2191 compatible = "qcom,tcsr-mutex";
2192 reg = <0x0 0x01f40000 0x0 0x40000>;
2193 #hwlock-cells = <1>;
2194 };
2195
2196 wsamacro: codec@3240000 {
2197 compatible = "qcom,sm8250-lpass-wsa-macro";
2198 reg = <0 0x03240000 0 0x1000>;
2199 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2200 <&audiocc LPASS_CDC_WSA_NPL>,
2201 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2202 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2203 <&aoncc LPASS_CDC_VA_MCLK>,
2204 <&vamacro>;
2205
2206 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2207
2208 #clock-cells = <0>;
2209 clock-frequency = <9600000>;
2210 clock-output-names = "mclk";
2211 #sound-dai-cells = <1>;
2212
2213 pinctrl-names = "default";
2214 pinctrl-0 = <&wsa_swr_active>;
2215 };
2216
2217 swr0: soundwire-controller@3250000 {
2218 reg = <0 0x03250000 0 0x2000>;
2219 compatible = "qcom,soundwire-v1.5.1";
2220 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2221 clocks = <&wsamacro>;
2222 clock-names = "iface";
2223
2224 qcom,din-ports = <2>;
2225 qcom,dout-ports = <6>;
2226
2227 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2228 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2229 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2230 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2231
2232 #sound-dai-cells = <1>;
2233 #address-cells = <2>;
2234 #size-cells = <0>;
2235 };
2236
2237 audiocc: clock-controller@3300000 {
2238 compatible = "qcom,sm8250-lpass-audiocc";
2239 reg = <0 0x03300000 0 0x30000>;
2240 #clock-cells = <1>;
2241 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2242 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2243 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2244 clock-names = "core", "audio", "bus";
2245 };
2246
2247 vamacro: codec@3370000 {
2248 compatible = "qcom,sm8250-lpass-va-macro";
2249 reg = <0 0x03370000 0 0x1000>;
2250 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2251 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2252 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2253
2254 clock-names = "mclk", "macro", "dcodec";
2255
2256 #clock-cells = <0>;
2257 clock-frequency = <9600000>;
2258 clock-output-names = "fsgen";
2259 #sound-dai-cells = <1>;
2260 };
2261
2262 rxmacro: rxmacro@3200000 {
2263 pinctrl-names = "default";
2264 pinctrl-0 = <&rx_swr_active>;
2265 compatible = "qcom,sm8250-lpass-rx-macro";
2266 reg = <0 0x3200000 0 0x1000>;
2267 status = "disabled";
2268
2269 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2270 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2271 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2272 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2273 <&vamacro>;
2274
2275 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2276
2277 #clock-cells = <0>;
2278 clock-frequency = <9600000>;
2279 clock-output-names = "mclk";
2280 #sound-dai-cells = <1>;
2281 };
2282
2283 swr1: soundwire-controller@3210000 {
2284 reg = <0 0x3210000 0 0x2000>;
2285 compatible = "qcom,soundwire-v1.5.1";
2286 status = "disabled";
2287 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2288 clocks = <&rxmacro>;
2289 clock-names = "iface";
2290 label = "RX";
2291 qcom,din-ports = <0>;
2292 qcom,dout-ports = <5>;
2293
2294 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2295 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2296 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2297 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2298 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2299 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2300 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2301 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2302 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2303
2304 #sound-dai-cells = <1>;
2305 #address-cells = <2>;
2306 #size-cells = <0>;
2307 };
2308
2309 txmacro: txmacro@3220000 {
2310 pinctrl-names = "default";
2311 pinctrl-0 = <&tx_swr_active>;
2312 compatible = "qcom,sm8250-lpass-tx-macro";
2313 reg = <0 0x3220000 0 0x1000>;
2314 status = "disabled";
2315
2316 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2317 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2318 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2319 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2320 <&vamacro>;
2321
2322 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2323
2324 #clock-cells = <0>;
2325 clock-frequency = <9600000>;
2326 clock-output-names = "mclk";
2327 #address-cells = <2>;
2328 #size-cells = <2>;
2329 #sound-dai-cells = <1>;
2330 };
2331
2332 /* tx macro */
2333 swr2: soundwire-controller@3230000 {
2334 reg = <0 0x3230000 0 0x2000>;
2335 compatible = "qcom,soundwire-v1.5.1";
2336 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2337 interrupt-names = "core";
2338 status = "disabled";
2339
2340 clocks = <&txmacro>;
2341 clock-names = "iface";
2342 label = "TX";
2343
2344 qcom,din-ports = <5>;
2345 qcom,dout-ports = <0>;
2346 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2347 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2348 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2349 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2350 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2351 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2352 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2353 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2354 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2355 qcom,port-offset = <1>;
2356 #sound-dai-cells = <1>;
2357 #address-cells = <2>;
2358 #size-cells = <0>;
2359 };
2360
2361 aoncc: clock-controller@3380000 {
2362 compatible = "qcom,sm8250-lpass-aoncc";
2363 reg = <0 0x03380000 0 0x40000>;
2364 #clock-cells = <1>;
2365 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2366 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2367 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2368 clock-names = "core", "audio", "bus";
2369 };
2370
2371 lpass_tlmm: pinctrl@33c0000{
2372 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2373 reg = <0 0x033c0000 0x0 0x20000>,
2374 <0 0x03550000 0x0 0x10000>;
2375 gpio-controller;
2376 #gpio-cells = <2>;
2377 gpio-ranges = <&lpass_tlmm 0 0 14>;
2378
2379 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2380 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2381 clock-names = "core", "audio";
2382
2383 wsa_swr_active: wsa-swr-active-pins {
2384 clk {
2385 pins = "gpio10";
2386 function = "wsa_swr_clk";
2387 drive-strength = <2>;
2388 slew-rate = <1>;
2389 bias-disable;
2390 };
2391
2392 data {
2393 pins = "gpio11";
2394 function = "wsa_swr_data";
2395 drive-strength = <2>;
2396 slew-rate = <1>;
2397 bias-bus-hold;
2398
2399 };
2400 };
2401
2402 wsa_swr_sleep: wsa-swr-sleep-pins {
2403 clk {
2404 pins = "gpio10";
2405 function = "wsa_swr_clk";
2406 drive-strength = <2>;
2407 input-enable;
2408 bias-pull-down;
2409 };
2410
2411 data {
2412 pins = "gpio11";
2413 function = "wsa_swr_data";
2414 drive-strength = <2>;
2415 input-enable;
2416 bias-pull-down;
2417
2418 };
2419 };
2420
2421 dmic01_active: dmic01-active-pins {
2422 clk {
2423 pins = "gpio6";
2424 function = "dmic1_clk";
2425 drive-strength = <8>;
2426 output-high;
2427 };
2428 data {
2429 pins = "gpio7";
2430 function = "dmic1_data";
2431 drive-strength = <8>;
2432 input-enable;
2433 };
2434 };
2435
2436 dmic01_sleep: dmic01-sleep-pins {
2437 clk {
2438 pins = "gpio6";
2439 function = "dmic1_clk";
2440 drive-strength = <2>;
2441 bias-disable;
2442 output-low;
2443 };
2444
2445 data {
2446 pins = "gpio7";
2447 function = "dmic1_data";
2448 drive-strength = <2>;
2449 pull-down;
2450 input-enable;
2451 };
2452 };
2453
2454 rx_swr_active: rx_swr-active-pins {
2455 clk {
2456 pins = "gpio3";
2457 function = "swr_rx_clk";
2458 drive-strength = <2>;
2459 slew-rate = <1>;
2460 bias-disable;
2461 };
2462
2463 data {
2464 pins = "gpio4", "gpio5";
2465 function = "swr_rx_data";
2466 drive-strength = <2>;
2467 slew-rate = <1>;
2468 bias-bus-hold;
2469 };
2470 };
2471
2472 tx_swr_active: tx_swr-active-pins {
2473 clk {
2474 pins = "gpio0";
2475 function = "swr_tx_clk";
2476 drive-strength = <2>;
2477 slew-rate = <1>;
2478 bias-disable;
2479 };
2480
2481 data {
2482 pins = "gpio1", "gpio2";
2483 function = "swr_tx_data";
2484 drive-strength = <2>;
2485 slew-rate = <1>;
2486 bias-bus-hold;
2487 };
2488 };
2489
2490 tx_swr_sleep: tx_swr-sleep-pins {
2491 clk {
2492 pins = "gpio0";
2493 function = "swr_tx_clk";
2494 drive-strength = <2>;
2495 input-enable;
2496 bias-pull-down;
2497 };
2498
2499 data1 {
2500 pins = "gpio1";
2501 function = "swr_tx_data";
2502 drive-strength = <2>;
2503 input-enable;
2504 bias-bus-hold;
2505 };
2506
2507 data2 {
2508 pins = "gpio2";
2509 function = "swr_tx_data";
2510 drive-strength = <2>;
2511 input-enable;
2512 bias-pull-down;
2513 };
2514 };
2515 };
2516
2517 gpu: gpu@3d00000 {
2518 compatible = "qcom,adreno-650.2",
2519 "qcom,adreno";
2520
2521 reg = <0 0x03d00000 0 0x40000>;
2522 reg-names = "kgsl_3d0_reg_memory";
2523
2524 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2525
2526 iommus = <&adreno_smmu 0 0x401>;
2527
2528 operating-points-v2 = <&gpu_opp_table>;
2529
2530 qcom,gmu = <&gmu>;
2531
2532 status = "disabled";
2533
2534 zap-shader {
2535 memory-region = <&gpu_mem>;
2536 };
2537
2538 /* note: downstream checks gpu binning for 670 Mhz */
2539 gpu_opp_table: opp-table {
2540 compatible = "operating-points-v2";
2541
2542 opp-670000000 {
2543 opp-hz = /bits/ 64 <670000000>;
2544 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2545 };
2546
2547 opp-587000000 {
2548 opp-hz = /bits/ 64 <587000000>;
2549 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2550 };
2551
2552 opp-525000000 {
2553 opp-hz = /bits/ 64 <525000000>;
2554 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2555 };
2556
2557 opp-490000000 {
2558 opp-hz = /bits/ 64 <490000000>;
2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2560 };
2561
2562 opp-441600000 {
2563 opp-hz = /bits/ 64 <441600000>;
2564 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2565 };
2566
2567 opp-400000000 {
2568 opp-hz = /bits/ 64 <400000000>;
2569 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2570 };
2571
2572 opp-305000000 {
2573 opp-hz = /bits/ 64 <305000000>;
2574 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2575 };
2576 };
2577 };
2578
2579 gmu: gmu@3d6a000 {
2580 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2581
2582 reg = <0 0x03d6a000 0 0x30000>,
2583 <0 0x3de0000 0 0x10000>,
2584 <0 0xb290000 0 0x10000>,
2585 <0 0xb490000 0 0x10000>;
2586 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2587
2588 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2590 interrupt-names = "hfi", "gmu";
2591
2592 clocks = <&gpucc GPU_CC_AHB_CLK>,
2593 <&gpucc GPU_CC_CX_GMU_CLK>,
2594 <&gpucc GPU_CC_CXO_CLK>,
2595 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2596 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2597 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2598
2599 power-domains = <&gpucc GPU_CX_GDSC>,
2600 <&gpucc GPU_GX_GDSC>;
2601 power-domain-names = "cx", "gx";
2602
2603 iommus = <&adreno_smmu 5 0x400>;
2604
2605 operating-points-v2 = <&gmu_opp_table>;
2606
2607 status = "disabled";
2608
2609 gmu_opp_table: opp-table {
2610 compatible = "operating-points-v2";
2611
2612 opp-200000000 {
2613 opp-hz = /bits/ 64 <200000000>;
2614 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2615 };
2616 };
2617 };
2618
2619 gpucc: clock-controller@3d90000 {
2620 compatible = "qcom,sm8250-gpucc";
2621 reg = <0 0x03d90000 0 0x9000>;
2622 clocks = <&rpmhcc RPMH_CXO_CLK>,
2623 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2624 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2625 clock-names = "bi_tcxo",
2626 "gcc_gpu_gpll0_clk_src",
2627 "gcc_gpu_gpll0_div_clk_src";
2628 #clock-cells = <1>;
2629 #reset-cells = <1>;
2630 #power-domain-cells = <1>;
2631 };
2632
2633 adreno_smmu: iommu@3da0000 {
2634 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2635 reg = <0 0x03da0000 0 0x10000>;
2636 #iommu-cells = <2>;
2637 #global-interrupts = <2>;
2638 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2639 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2640 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2641 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2643 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2644 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2645 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2646 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2647 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2648 clocks = <&gpucc GPU_CC_AHB_CLK>,
2649 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2650 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2651 clock-names = "ahb", "bus", "iface";
2652
2653 power-domains = <&gpucc GPU_CX_GDSC>;
2654 };
2655
2656 slpi: remoteproc@5c00000 {
2657 compatible = "qcom,sm8250-slpi-pas";
2658 reg = <0 0x05c00000 0 0x4000>;
2659
2660 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2661 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2662 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2663 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2664 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2665 interrupt-names = "wdog", "fatal", "ready",
2666 "handover", "stop-ack";
2667
2668 clocks = <&rpmhcc RPMH_CXO_CLK>;
2669 clock-names = "xo";
2670
2671 power-domains = <&rpmhpd SM8250_LCX>,
2672 <&rpmhpd SM8250_LMX>;
2673 power-domain-names = "lcx", "lmx";
2674
2675 memory-region = <&slpi_mem>;
2676
2677 qcom,qmp = <&aoss_qmp>;
2678
2679 qcom,smem-states = <&smp2p_slpi_out 0>;
2680 qcom,smem-state-names = "stop";
2681
2682 status = "disabled";
2683
2684 glink-edge {
2685 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2686 IPCC_MPROC_SIGNAL_GLINK_QMP
2687 IRQ_TYPE_EDGE_RISING>;
2688 mboxes = <&ipcc IPCC_CLIENT_SLPI
2689 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2690
2691 label = "slpi";
2692 qcom,remote-pid = <3>;
2693
2694 fastrpc {
2695 compatible = "qcom,fastrpc";
2696 qcom,glink-channels = "fastrpcglink-apps-dsp";
2697 label = "sdsp";
2698 qcom,non-secure-domain;
2699 #address-cells = <1>;
2700 #size-cells = <0>;
2701
2702 compute-cb@1 {
2703 compatible = "qcom,fastrpc-compute-cb";
2704 reg = <1>;
2705 iommus = <&apps_smmu 0x0541 0x0>;
2706 };
2707
2708 compute-cb@2 {
2709 compatible = "qcom,fastrpc-compute-cb";
2710 reg = <2>;
2711 iommus = <&apps_smmu 0x0542 0x0>;
2712 };
2713
2714 compute-cb@3 {
2715 compatible = "qcom,fastrpc-compute-cb";
2716 reg = <3>;
2717 iommus = <&apps_smmu 0x0543 0x0>;
2718 /* note: shared-cb = <4> in downstream */
2719 };
2720 };
2721 };
2722 };
2723
2724 cdsp: remoteproc@8300000 {
2725 compatible = "qcom,sm8250-cdsp-pas";
2726 reg = <0 0x08300000 0 0x10000>;
2727
2728 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2729 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2730 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2731 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2732 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2733 interrupt-names = "wdog", "fatal", "ready",
2734 "handover", "stop-ack";
2735
2736 clocks = <&rpmhcc RPMH_CXO_CLK>;
2737 clock-names = "xo";
2738
2739 power-domains = <&rpmhpd SM8250_CX>;
2740
2741 memory-region = <&cdsp_mem>;
2742
2743 qcom,qmp = <&aoss_qmp>;
2744
2745 qcom,smem-states = <&smp2p_cdsp_out 0>;
2746 qcom,smem-state-names = "stop";
2747
2748 status = "disabled";
2749
2750 glink-edge {
2751 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2752 IPCC_MPROC_SIGNAL_GLINK_QMP
2753 IRQ_TYPE_EDGE_RISING>;
2754 mboxes = <&ipcc IPCC_CLIENT_CDSP
2755 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2756
2757 label = "cdsp";
2758 qcom,remote-pid = <5>;
2759
2760 fastrpc {
2761 compatible = "qcom,fastrpc";
2762 qcom,glink-channels = "fastrpcglink-apps-dsp";
2763 label = "cdsp";
2764 qcom,non-secure-domain;
2765 #address-cells = <1>;
2766 #size-cells = <0>;
2767
2768 compute-cb@1 {
2769 compatible = "qcom,fastrpc-compute-cb";
2770 reg = <1>;
2771 iommus = <&apps_smmu 0x1001 0x0460>;
2772 };
2773
2774 compute-cb@2 {
2775 compatible = "qcom,fastrpc-compute-cb";
2776 reg = <2>;
2777 iommus = <&apps_smmu 0x1002 0x0460>;
2778 };
2779
2780 compute-cb@3 {
2781 compatible = "qcom,fastrpc-compute-cb";
2782 reg = <3>;
2783 iommus = <&apps_smmu 0x1003 0x0460>;
2784 };
2785
2786 compute-cb@4 {
2787 compatible = "qcom,fastrpc-compute-cb";
2788 reg = <4>;
2789 iommus = <&apps_smmu 0x1004 0x0460>;
2790 };
2791
2792 compute-cb@5 {
2793 compatible = "qcom,fastrpc-compute-cb";
2794 reg = <5>;
2795 iommus = <&apps_smmu 0x1005 0x0460>;
2796 };
2797
2798 compute-cb@6 {
2799 compatible = "qcom,fastrpc-compute-cb";
2800 reg = <6>;
2801 iommus = <&apps_smmu 0x1006 0x0460>;
2802 };
2803
2804 compute-cb@7 {
2805 compatible = "qcom,fastrpc-compute-cb";
2806 reg = <7>;
2807 iommus = <&apps_smmu 0x1007 0x0460>;
2808 };
2809
2810 compute-cb@8 {
2811 compatible = "qcom,fastrpc-compute-cb";
2812 reg = <8>;
2813 iommus = <&apps_smmu 0x1008 0x0460>;
2814 };
2815
2816 /* note: secure cb9 in downstream */
2817 };
2818 };
2819 };
2820
2821 sound: sound {
2822 };
2823
2824 usb_1_hsphy: phy@88e3000 {
2825 compatible = "qcom,sm8250-usb-hs-phy",
2826 "qcom,usb-snps-hs-7nm-phy";
2827 reg = <0 0x088e3000 0 0x400>;
2828 status = "disabled";
2829 #phy-cells = <0>;
2830
2831 clocks = <&rpmhcc RPMH_CXO_CLK>;
2832 clock-names = "ref";
2833
2834 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2835 };
2836
2837 usb_2_hsphy: phy@88e4000 {
2838 compatible = "qcom,sm8250-usb-hs-phy",
2839 "qcom,usb-snps-hs-7nm-phy";
2840 reg = <0 0x088e4000 0 0x400>;
2841 status = "disabled";
2842 #phy-cells = <0>;
2843
2844 clocks = <&rpmhcc RPMH_CXO_CLK>;
2845 clock-names = "ref";
2846
2847 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2848 };
2849
2850 usb_1_qmpphy: phy@88e9000 {
2851 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2852 reg = <0 0x088e9000 0 0x200>,
2853 <0 0x088e8000 0 0x40>,
2854 <0 0x088ea000 0 0x200>;
2855 status = "disabled";
2856 #address-cells = <2>;
2857 #size-cells = <2>;
2858 ranges;
2859
2860 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2861 <&rpmhcc RPMH_CXO_CLK>,
2862 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2863 clock-names = "aux", "ref_clk_src", "com_aux";
2864
2865 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2866 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2867 reset-names = "phy", "common";
2868
2869 usb_1_ssphy: usb3-phy@88e9200 {
2870 reg = <0 0x088e9200 0 0x200>,
2871 <0 0x088e9400 0 0x200>,
2872 <0 0x088e9c00 0 0x400>,
2873 <0 0x088e9600 0 0x200>,
2874 <0 0x088e9800 0 0x200>,
2875 <0 0x088e9a00 0 0x100>;
2876 #clock-cells = <0>;
2877 #phy-cells = <0>;
2878 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2879 clock-names = "pipe0";
2880 clock-output-names = "usb3_phy_pipe_clk_src";
2881 };
2882
2883 dp_phy: dp-phy@88ea200 {
2884 reg = <0 0x088ea200 0 0x200>,
2885 <0 0x088ea400 0 0x200>,
2886 <0 0x088eac00 0 0x400>,
2887 <0 0x088ea600 0 0x200>,
2888 <0 0x088ea800 0 0x200>,
2889 <0 0x088eaa00 0 0x100>;
2890 #phy-cells = <0>;
2891 #clock-cells = <1>;
2892 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2893 clock-names = "pipe0";
2894 clock-output-names = "usb3_phy_pipe_clk_src";
2895 };
2896 };
2897
2898 usb_2_qmpphy: phy@88eb000 {
2899 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2900 reg = <0 0x088eb000 0 0x200>;
2901 status = "disabled";
2902 #address-cells = <2>;
2903 #size-cells = <2>;
2904 ranges;
2905
2906 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2907 <&rpmhcc RPMH_CXO_CLK>,
2908 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2909 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2910 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2911
2912 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2913 <&gcc GCC_USB3_PHY_SEC_BCR>;
2914 reset-names = "phy", "common";
2915
2916 usb_2_ssphy: phy@88eb200 {
2917 reg = <0 0x088eb200 0 0x200>,
2918 <0 0x088eb400 0 0x200>,
2919 <0 0x088eb800 0 0x800>;
2920 #clock-cells = <0>;
2921 #phy-cells = <0>;
2922 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2923 clock-names = "pipe0";
2924 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2925 };
2926 };
2927
2928 sdhc_2: mmc@8804000 {
2929 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2930 reg = <0 0x08804000 0 0x1000>;
2931
2932 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2933 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2934 interrupt-names = "hc_irq", "pwr_irq";
2935
2936 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2937 <&gcc GCC_SDCC2_APPS_CLK>,
2938 <&rpmhcc RPMH_CXO_CLK>;
2939 clock-names = "iface", "core", "xo";
2940 iommus = <&apps_smmu 0x4a0 0x0>;
2941 qcom,dll-config = <0x0007642c>;
2942 qcom,ddr-config = <0x80040868>;
2943 power-domains = <&rpmhpd SM8250_CX>;
2944 operating-points-v2 = <&sdhc2_opp_table>;
2945
2946 status = "disabled";
2947
2948 sdhc2_opp_table: opp-table {
2949 compatible = "operating-points-v2";
2950
2951 opp-19200000 {
2952 opp-hz = /bits/ 64 <19200000>;
2953 required-opps = <&rpmhpd_opp_min_svs>;
2954 };
2955
2956 opp-50000000 {
2957 opp-hz = /bits/ 64 <50000000>;
2958 required-opps = <&rpmhpd_opp_low_svs>;
2959 };
2960
2961 opp-100000000 {
2962 opp-hz = /bits/ 64 <100000000>;
2963 required-opps = <&rpmhpd_opp_svs>;
2964 };
2965
2966 opp-202000000 {
2967 opp-hz = /bits/ 64 <202000000>;
2968 required-opps = <&rpmhpd_opp_svs_l1>;
2969 };
2970 };
2971 };
2972
2973 dc_noc: interconnect@90c0000 {
2974 compatible = "qcom,sm8250-dc-noc";
2975 reg = <0 0x090c0000 0 0x4200>;
2976 #interconnect-cells = <1>;
2977 qcom,bcm-voters = <&apps_bcm_voter>;
2978 };
2979
2980 gem_noc: interconnect@9100000 {
2981 compatible = "qcom,sm8250-gem-noc";
2982 reg = <0 0x09100000 0 0xb4000>;
2983 #interconnect-cells = <1>;
2984 qcom,bcm-voters = <&apps_bcm_voter>;
2985 };
2986
2987 npu_noc: interconnect@9990000 {
2988 compatible = "qcom,sm8250-npu-noc";
2989 reg = <0 0x09990000 0 0x1600>;
2990 #interconnect-cells = <1>;
2991 qcom,bcm-voters = <&apps_bcm_voter>;
2992 };
2993
2994 usb_1: usb@a6f8800 {
2995 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2996 reg = <0 0x0a6f8800 0 0x400>;
2997 status = "disabled";
2998 #address-cells = <2>;
2999 #size-cells = <2>;
3000 ranges;
3001 dma-ranges;
3002
3003 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3004 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3005 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3006 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3007 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3008 <&gcc GCC_USB3_SEC_CLKREF_EN>;
3009 clock-names = "cfg_noc",
3010 "core",
3011 "iface",
3012 "sleep",
3013 "mock_utmi",
3014 "xo";
3015
3016 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3017 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3018 assigned-clock-rates = <19200000>, <200000000>;
3019
3020 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3021 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3022 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3023 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3024 interrupt-names = "hs_phy_irq",
3025 "ss_phy_irq",
3026 "dm_hs_phy_irq",
3027 "dp_hs_phy_irq";
3028
3029 power-domains = <&gcc USB30_PRIM_GDSC>;
3030
3031 resets = <&gcc GCC_USB30_PRIM_BCR>;
3032
3033 usb_1_dwc3: usb@a600000 {
3034 compatible = "snps,dwc3";
3035 reg = <0 0x0a600000 0 0xcd00>;
3036 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3037 iommus = <&apps_smmu 0x0 0x0>;
3038 snps,dis_u2_susphy_quirk;
3039 snps,dis_enblslpm_quirk;
3040 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3041 phy-names = "usb2-phy", "usb3-phy";
3042 };
3043 };
3044
3045 system-cache-controller@9200000 {
3046 compatible = "qcom,sm8250-llcc";
3047 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3048 reg-names = "llcc_base", "llcc_broadcast_base";
3049 };
3050
3051 usb_2: usb@a8f8800 {
3052 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3053 reg = <0 0x0a8f8800 0 0x400>;
3054 status = "disabled";
3055 #address-cells = <2>;
3056 #size-cells = <2>;
3057 ranges;
3058 dma-ranges;
3059
3060 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3061 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3062 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3063 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3064 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3065 <&gcc GCC_USB3_SEC_CLKREF_EN>;
3066 clock-names = "cfg_noc",
3067 "core",
3068 "iface",
3069 "sleep",
3070 "mock_utmi",
3071 "xo";
3072
3073 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3074 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3075 assigned-clock-rates = <19200000>, <200000000>;
3076
3077 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3078 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3079 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3080 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
3081 interrupt-names = "hs_phy_irq",
3082 "ss_phy_irq",
3083 "dm_hs_phy_irq",
3084 "dp_hs_phy_irq";
3085
3086 power-domains = <&gcc USB30_SEC_GDSC>;
3087
3088 resets = <&gcc GCC_USB30_SEC_BCR>;
3089
3090 usb_2_dwc3: usb@a800000 {
3091 compatible = "snps,dwc3";
3092 reg = <0 0x0a800000 0 0xcd00>;
3093 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3094 iommus = <&apps_smmu 0x20 0>;
3095 snps,dis_u2_susphy_quirk;
3096 snps,dis_enblslpm_quirk;
3097 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3098 phy-names = "usb2-phy", "usb3-phy";
3099 };
3100 };
3101
3102 venus: video-codec@aa00000 {
3103 compatible = "qcom,sm8250-venus";
3104 reg = <0 0x0aa00000 0 0x100000>;
3105 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3106 power-domains = <&videocc MVS0C_GDSC>,
3107 <&videocc MVS0_GDSC>,
3108 <&rpmhpd SM8250_MX>;
3109 power-domain-names = "venus", "vcodec0", "mx";
3110 operating-points-v2 = <&venus_opp_table>;
3111
3112 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3113 <&videocc VIDEO_CC_MVS0C_CLK>,
3114 <&videocc VIDEO_CC_MVS0_CLK>;
3115 clock-names = "iface", "core", "vcodec0_core";
3116
3117 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
3118 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
3119 interconnect-names = "cpu-cfg", "video-mem";
3120
3121 iommus = <&apps_smmu 0x2100 0x0400>;
3122 memory-region = <&video_mem>;
3123
3124 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3125 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3126 reset-names = "bus", "core";
3127
3128 status = "disabled";
3129
3130 video-decoder {
3131 compatible = "venus-decoder";
3132 };
3133
3134 video-encoder {
3135 compatible = "venus-encoder";
3136 };
3137
3138 venus_opp_table: opp-table {
3139 compatible = "operating-points-v2";
3140
3141 opp-720000000 {
3142 opp-hz = /bits/ 64 <720000000>;
3143 required-opps = <&rpmhpd_opp_low_svs>;
3144 };
3145
3146 opp-1014000000 {
3147 opp-hz = /bits/ 64 <1014000000>;
3148 required-opps = <&rpmhpd_opp_svs>;
3149 };
3150
3151 opp-1098000000 {
3152 opp-hz = /bits/ 64 <1098000000>;
3153 required-opps = <&rpmhpd_opp_svs_l1>;
3154 };
3155
3156 opp-1332000000 {
3157 opp-hz = /bits/ 64 <1332000000>;
3158 required-opps = <&rpmhpd_opp_nom>;
3159 };
3160 };
3161 };
3162
3163 videocc: clock-controller@abf0000 {
3164 compatible = "qcom,sm8250-videocc";
3165 reg = <0 0x0abf0000 0 0x10000>;
3166 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3167 <&rpmhcc RPMH_CXO_CLK>,
3168 <&rpmhcc RPMH_CXO_CLK_A>;
3169 power-domains = <&rpmhpd SM8250_MMCX>;
3170 required-opps = <&rpmhpd_opp_low_svs>;
3171 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3172 #clock-cells = <1>;
3173 #reset-cells = <1>;
3174 #power-domain-cells = <1>;
3175 };
3176
3177 cci0: cci@ac4f000 {
3178 compatible = "qcom,sm8250-cci";
3179 #address-cells = <1>;
3180 #size-cells = <0>;
3181
3182 reg = <0 0x0ac4f000 0 0x1000>;
3183 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3184 power-domains = <&camcc TITAN_TOP_GDSC>;
3185
3186 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3187 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3188 <&camcc CAM_CC_CPAS_AHB_CLK>,
3189 <&camcc CAM_CC_CCI_0_CLK>,
3190 <&camcc CAM_CC_CCI_0_CLK_SRC>;
3191 clock-names = "camnoc_axi",
3192 "slow_ahb_src",
3193 "cpas_ahb",
3194 "cci",
3195 "cci_src";
3196
3197 pinctrl-0 = <&cci0_default>;
3198 pinctrl-1 = <&cci0_sleep>;
3199 pinctrl-names = "default", "sleep";
3200
3201 status = "disabled";
3202
3203 cci0_i2c0: i2c-bus@0 {
3204 reg = <0>;
3205 clock-frequency = <1000000>;
3206 #address-cells = <1>;
3207 #size-cells = <0>;
3208 };
3209
3210 cci0_i2c1: i2c-bus@1 {
3211 reg = <1>;
3212 clock-frequency = <1000000>;
3213 #address-cells = <1>;
3214 #size-cells = <0>;
3215 };
3216 };
3217
3218 cci1: cci@ac50000 {
3219 compatible = "qcom,sm8250-cci";
3220 #address-cells = <1>;
3221 #size-cells = <0>;
3222
3223 reg = <0 0x0ac50000 0 0x1000>;
3224 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3225 power-domains = <&camcc TITAN_TOP_GDSC>;
3226
3227 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3228 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3229 <&camcc CAM_CC_CPAS_AHB_CLK>,
3230 <&camcc CAM_CC_CCI_1_CLK>,
3231 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3232 clock-names = "camnoc_axi",
3233 "slow_ahb_src",
3234 "cpas_ahb",
3235 "cci",
3236 "cci_src";
3237
3238 pinctrl-0 = <&cci1_default>;
3239 pinctrl-1 = <&cci1_sleep>;
3240 pinctrl-names = "default", "sleep";
3241
3242 status = "disabled";
3243
3244 cci1_i2c0: i2c-bus@0 {
3245 reg = <0>;
3246 clock-frequency = <1000000>;
3247 #address-cells = <1>;
3248 #size-cells = <0>;
3249 };
3250
3251 cci1_i2c1: i2c-bus@1 {
3252 reg = <1>;
3253 clock-frequency = <1000000>;
3254 #address-cells = <1>;
3255 #size-cells = <0>;
3256 };
3257 };
3258
3259 camss: camss@ac6a000 {
3260 compatible = "qcom,sm8250-camss";
3261 status = "disabled";
3262
3263 reg = <0 0xac6a000 0 0x2000>,
3264 <0 0xac6c000 0 0x2000>,
3265 <0 0xac6e000 0 0x1000>,
3266 <0 0xac70000 0 0x1000>,
3267 <0 0xac72000 0 0x1000>,
3268 <0 0xac74000 0 0x1000>,
3269 <0 0xacb4000 0 0xd000>,
3270 <0 0xacc3000 0 0xd000>,
3271 <0 0xacd9000 0 0x2200>,
3272 <0 0xacdb200 0 0x2200>;
3273 reg-names = "csiphy0",
3274 "csiphy1",
3275 "csiphy2",
3276 "csiphy3",
3277 "csiphy4",
3278 "csiphy5",
3279 "vfe0",
3280 "vfe1",
3281 "vfe_lite0",
3282 "vfe_lite1";
3283
3284 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3287 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3288 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3289 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3290 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3291 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3292 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3293 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3297 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3298 interrupt-names = "csiphy0",
3299 "csiphy1",
3300 "csiphy2",
3301 "csiphy3",
3302 "csiphy4",
3303 "csiphy5",
3304 "csid0",
3305 "csid1",
3306 "csid2",
3307 "csid3",
3308 "vfe0",
3309 "vfe1",
3310 "vfe_lite0",
3311 "vfe_lite1";
3312
3313 power-domains = <&camcc IFE_0_GDSC>,
3314 <&camcc IFE_1_GDSC>,
3315 <&camcc TITAN_TOP_GDSC>;
3316
3317 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3318 <&gcc GCC_CAMERA_HF_AXI_CLK>,
3319 <&gcc GCC_CAMERA_SF_AXI_CLK>,
3320 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3321 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3322 <&camcc CAM_CC_CORE_AHB_CLK>,
3323 <&camcc CAM_CC_CPAS_AHB_CLK>,
3324 <&camcc CAM_CC_CSIPHY0_CLK>,
3325 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3326 <&camcc CAM_CC_CSIPHY1_CLK>,
3327 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3328 <&camcc CAM_CC_CSIPHY2_CLK>,
3329 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3330 <&camcc CAM_CC_CSIPHY3_CLK>,
3331 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3332 <&camcc CAM_CC_CSIPHY4_CLK>,
3333 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3334 <&camcc CAM_CC_CSIPHY5_CLK>,
3335 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3336 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3337 <&camcc CAM_CC_IFE_0_AHB_CLK>,
3338 <&camcc CAM_CC_IFE_0_AXI_CLK>,
3339 <&camcc CAM_CC_IFE_0_CLK>,
3340 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3341 <&camcc CAM_CC_IFE_0_CSID_CLK>,
3342 <&camcc CAM_CC_IFE_0_AREG_CLK>,
3343 <&camcc CAM_CC_IFE_1_AHB_CLK>,
3344 <&camcc CAM_CC_IFE_1_AXI_CLK>,
3345 <&camcc CAM_CC_IFE_1_CLK>,
3346 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3347 <&camcc CAM_CC_IFE_1_CSID_CLK>,
3348 <&camcc CAM_CC_IFE_1_AREG_CLK>,
3349 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3350 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3351 <&camcc CAM_CC_IFE_LITE_CLK>,
3352 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3353 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3354
3355 clock-names = "cam_ahb_clk",
3356 "cam_hf_axi",
3357 "cam_sf_axi",
3358 "camnoc_axi",
3359 "camnoc_axi_src",
3360 "core_ahb",
3361 "cpas_ahb",
3362 "csiphy0",
3363 "csiphy0_timer",
3364 "csiphy1",
3365 "csiphy1_timer",
3366 "csiphy2",
3367 "csiphy2_timer",
3368 "csiphy3",
3369 "csiphy3_timer",
3370 "csiphy4",
3371 "csiphy4_timer",
3372 "csiphy5",
3373 "csiphy5_timer",
3374 "slow_ahb_src",
3375 "vfe0_ahb",
3376 "vfe0_axi",
3377 "vfe0",
3378 "vfe0_cphy_rx",
3379 "vfe0_csid",
3380 "vfe0_areg",
3381 "vfe1_ahb",
3382 "vfe1_axi",
3383 "vfe1",
3384 "vfe1_cphy_rx",
3385 "vfe1_csid",
3386 "vfe1_areg",
3387 "vfe_lite_ahb",
3388 "vfe_lite_axi",
3389 "vfe_lite",
3390 "vfe_lite_cphy_rx",
3391 "vfe_lite_csid";
3392
3393 iommus = <&apps_smmu 0x800 0x400>,
3394 <&apps_smmu 0x801 0x400>,
3395 <&apps_smmu 0x840 0x400>,
3396 <&apps_smmu 0x841 0x400>,
3397 <&apps_smmu 0xc00 0x400>,
3398 <&apps_smmu 0xc01 0x400>,
3399 <&apps_smmu 0xc40 0x400>,
3400 <&apps_smmu 0xc41 0x400>;
3401
3402 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3403 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3404 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3405 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3406 interconnect-names = "cam_ahb",
3407 "cam_hf_0_mnoc",
3408 "cam_sf_0_mnoc",
3409 "cam_sf_icp_mnoc";
3410 };
3411
3412 camcc: clock-controller@ad00000 {
3413 compatible = "qcom,sm8250-camcc";
3414 reg = <0 0x0ad00000 0 0x10000>;
3415 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3416 <&rpmhcc RPMH_CXO_CLK>,
3417 <&rpmhcc RPMH_CXO_CLK_A>,
3418 <&sleep_clk>;
3419 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3420 power-domains = <&rpmhpd SM8250_MMCX>;
3421 required-opps = <&rpmhpd_opp_low_svs>;
3422 status = "disabled";
3423 #clock-cells = <1>;
3424 #reset-cells = <1>;
3425 #power-domain-cells = <1>;
3426 };
3427
3428 mdss: mdss@ae00000 {
3429 compatible = "qcom,sm8250-mdss";
3430 reg = <0 0x0ae00000 0 0x1000>;
3431 reg-names = "mdss";
3432
3433 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3434 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3435 interconnect-names = "mdp0-mem", "mdp1-mem";
3436
3437 power-domains = <&dispcc MDSS_GDSC>;
3438
3439 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3440 <&gcc GCC_DISP_HF_AXI_CLK>,
3441 <&gcc GCC_DISP_SF_AXI_CLK>,
3442 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3443 clock-names = "iface", "bus", "nrt_bus", "core";
3444
3445 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3446 interrupt-controller;
3447 #interrupt-cells = <1>;
3448
3449 iommus = <&apps_smmu 0x820 0x402>;
3450
3451 status = "disabled";
3452
3453 #address-cells = <2>;
3454 #size-cells = <2>;
3455 ranges;
3456
3457 mdss_mdp: display-controller@ae01000 {
3458 compatible = "qcom,sm8250-dpu";
3459 reg = <0 0x0ae01000 0 0x8f000>,
3460 <0 0x0aeb0000 0 0x2008>;
3461 reg-names = "mdp", "vbif";
3462
3463 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3464 <&gcc GCC_DISP_HF_AXI_CLK>,
3465 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3466 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3467 clock-names = "iface", "bus", "core", "vsync";
3468
3469 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3470 assigned-clock-rates = <19200000>;
3471
3472 operating-points-v2 = <&mdp_opp_table>;
3473 power-domains = <&rpmhpd SM8250_MMCX>;
3474
3475 interrupt-parent = <&mdss>;
3476 interrupts = <0>;
3477
3478 ports {
3479 #address-cells = <1>;
3480 #size-cells = <0>;
3481
3482 port@0 {
3483 reg = <0>;
3484 dpu_intf1_out: endpoint {
3485 remote-endpoint = <&dsi0_in>;
3486 };
3487 };
3488
3489 port@1 {
3490 reg = <1>;
3491 dpu_intf2_out: endpoint {
3492 remote-endpoint = <&dsi1_in>;
3493 };
3494 };
3495 };
3496
3497 mdp_opp_table: opp-table {
3498 compatible = "operating-points-v2";
3499
3500 opp-200000000 {
3501 opp-hz = /bits/ 64 <200000000>;
3502 required-opps = <&rpmhpd_opp_low_svs>;
3503 };
3504
3505 opp-300000000 {
3506 opp-hz = /bits/ 64 <300000000>;
3507 required-opps = <&rpmhpd_opp_svs>;
3508 };
3509
3510 opp-345000000 {
3511 opp-hz = /bits/ 64 <345000000>;
3512 required-opps = <&rpmhpd_opp_svs_l1>;
3513 };
3514
3515 opp-460000000 {
3516 opp-hz = /bits/ 64 <460000000>;
3517 required-opps = <&rpmhpd_opp_nom>;
3518 };
3519 };
3520 };
3521
3522 dsi0: dsi@ae94000 {
3523 compatible = "qcom,mdss-dsi-ctrl";
3524 reg = <0 0x0ae94000 0 0x400>;
3525 reg-names = "dsi_ctrl";
3526
3527 interrupt-parent = <&mdss>;
3528 interrupts = <4>;
3529
3530 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3531 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3532 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3533 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3534 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3535 <&gcc GCC_DISP_HF_AXI_CLK>;
3536 clock-names = "byte",
3537 "byte_intf",
3538 "pixel",
3539 "core",
3540 "iface",
3541 "bus";
3542
3543 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3544 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3545
3546 operating-points-v2 = <&dsi_opp_table>;
3547 power-domains = <&rpmhpd SM8250_MMCX>;
3548
3549 phys = <&dsi0_phy>;
3550 phy-names = "dsi";
3551
3552 status = "disabled";
3553
3554 #address-cells = <1>;
3555 #size-cells = <0>;
3556
3557 ports {
3558 #address-cells = <1>;
3559 #size-cells = <0>;
3560
3561 port@0 {
3562 reg = <0>;
3563 dsi0_in: endpoint {
3564 remote-endpoint = <&dpu_intf1_out>;
3565 };
3566 };
3567
3568 port@1 {
3569 reg = <1>;
3570 dsi0_out: endpoint {
3571 };
3572 };
3573 };
3574 };
3575
3576 dsi0_phy: dsi-phy@ae94400 {
3577 compatible = "qcom,dsi-phy-7nm";
3578 reg = <0 0x0ae94400 0 0x200>,
3579 <0 0x0ae94600 0 0x280>,
3580 <0 0x0ae94900 0 0x260>;
3581 reg-names = "dsi_phy",
3582 "dsi_phy_lane",
3583 "dsi_pll";
3584
3585 #clock-cells = <1>;
3586 #phy-cells = <0>;
3587
3588 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3589 <&rpmhcc RPMH_CXO_CLK>;
3590 clock-names = "iface", "ref";
3591
3592 status = "disabled";
3593 };
3594
3595 dsi1: dsi@ae96000 {
3596 compatible = "qcom,mdss-dsi-ctrl";
3597 reg = <0 0x0ae96000 0 0x400>;
3598 reg-names = "dsi_ctrl";
3599
3600 interrupt-parent = <&mdss>;
3601 interrupts = <5>;
3602
3603 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3604 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3605 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3606 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3607 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3608 <&gcc GCC_DISP_HF_AXI_CLK>;
3609 clock-names = "byte",
3610 "byte_intf",
3611 "pixel",
3612 "core",
3613 "iface",
3614 "bus";
3615
3616 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3617 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3618
3619 operating-points-v2 = <&dsi_opp_table>;
3620 power-domains = <&rpmhpd SM8250_MMCX>;
3621
3622 phys = <&dsi1_phy>;
3623 phy-names = "dsi";
3624
3625 status = "disabled";
3626
3627 #address-cells = <1>;
3628 #size-cells = <0>;
3629
3630 ports {
3631 #address-cells = <1>;
3632 #size-cells = <0>;
3633
3634 port@0 {
3635 reg = <0>;
3636 dsi1_in: endpoint {
3637 remote-endpoint = <&dpu_intf2_out>;
3638 };
3639 };
3640
3641 port@1 {
3642 reg = <1>;
3643 dsi1_out: endpoint {
3644 };
3645 };
3646 };
3647 };
3648
3649 dsi1_phy: dsi-phy@ae96400 {
3650 compatible = "qcom,dsi-phy-7nm";
3651 reg = <0 0x0ae96400 0 0x200>,
3652 <0 0x0ae96600 0 0x280>,
3653 <0 0x0ae96900 0 0x260>;
3654 reg-names = "dsi_phy",
3655 "dsi_phy_lane",
3656 "dsi_pll";
3657
3658 #clock-cells = <1>;
3659 #phy-cells = <0>;
3660
3661 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3662 <&rpmhcc RPMH_CXO_CLK>;
3663 clock-names = "iface", "ref";
3664
3665 status = "disabled";
3666
3667 dsi_opp_table: opp-table {
3668 compatible = "operating-points-v2";
3669
3670 opp-187500000 {
3671 opp-hz = /bits/ 64 <187500000>;
3672 required-opps = <&rpmhpd_opp_low_svs>;
3673 };
3674
3675 opp-300000000 {
3676 opp-hz = /bits/ 64 <300000000>;
3677 required-opps = <&rpmhpd_opp_svs>;
3678 };
3679
3680 opp-358000000 {
3681 opp-hz = /bits/ 64 <358000000>;
3682 required-opps = <&rpmhpd_opp_svs_l1>;
3683 };
3684 };
3685 };
3686 };
3687
3688 dispcc: clock-controller@af00000 {
3689 compatible = "qcom,sm8250-dispcc";
3690 reg = <0 0x0af00000 0 0x10000>;
3691 power-domains = <&rpmhpd SM8250_MMCX>;
3692 required-opps = <&rpmhpd_opp_low_svs>;
3693 clocks = <&rpmhcc RPMH_CXO_CLK>,
3694 <&dsi0_phy 0>,
3695 <&dsi0_phy 1>,
3696 <&dsi1_phy 0>,
3697 <&dsi1_phy 1>,
3698 <&dp_phy 0>,
3699 <&dp_phy 1>;
3700 clock-names = "bi_tcxo",
3701 "dsi0_phy_pll_out_byteclk",
3702 "dsi0_phy_pll_out_dsiclk",
3703 "dsi1_phy_pll_out_byteclk",
3704 "dsi1_phy_pll_out_dsiclk",
3705 "dp_phy_pll_link_clk",
3706 "dp_phy_pll_vco_div_clk";
3707 #clock-cells = <1>;
3708 #reset-cells = <1>;
3709 #power-domain-cells = <1>;
3710 };
3711
3712 pdc: interrupt-controller@b220000 {
3713 compatible = "qcom,sm8250-pdc", "qcom,pdc";
3714 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3715 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3716 <125 63 1>, <126 716 12>;
3717 #interrupt-cells = <2>;
3718 interrupt-parent = <&intc>;
3719 interrupt-controller;
3720 };
3721
3722 tsens0: thermal-sensor@c263000 {
3723 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3724 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3725 <0 0x0c222000 0 0x1ff>; /* SROT */
3726 #qcom,sensors = <16>;
3727 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3728 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3729 interrupt-names = "uplow", "critical";
3730 #thermal-sensor-cells = <1>;
3731 };
3732
3733 tsens1: thermal-sensor@c265000 {
3734 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3735 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3736 <0 0x0c223000 0 0x1ff>; /* SROT */
3737 #qcom,sensors = <9>;
3738 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3739 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3740 interrupt-names = "uplow", "critical";
3741 #thermal-sensor-cells = <1>;
3742 };
3743
3744 aoss_qmp: power-controller@c300000 {
3745 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
3746 reg = <0 0x0c300000 0 0x400>;
3747 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3748 IPCC_MPROC_SIGNAL_GLINK_QMP
3749 IRQ_TYPE_EDGE_RISING>;
3750 mboxes = <&ipcc IPCC_CLIENT_AOP
3751 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3752
3753 #clock-cells = <0>;
3754 };
3755
3756 sram@c3f0000 {
3757 compatible = "qcom,rpmh-stats";
3758 reg = <0 0x0c3f0000 0 0x400>;
3759 };
3760
3761 spmi_bus: spmi@c440000 {
3762 compatible = "qcom,spmi-pmic-arb";
3763 reg = <0x0 0x0c440000 0x0 0x0001100>,
3764 <0x0 0x0c600000 0x0 0x2000000>,
3765 <0x0 0x0e600000 0x0 0x0100000>,
3766 <0x0 0x0e700000 0x0 0x00a0000>,
3767 <0x0 0x0c40a000 0x0 0x0026000>;
3768 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3769 interrupt-names = "periph_irq";
3770 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3771 qcom,ee = <0>;
3772 qcom,channel = <0>;
3773 #address-cells = <2>;
3774 #size-cells = <0>;
3775 interrupt-controller;
3776 #interrupt-cells = <4>;
3777 };
3778
3779 tlmm: pinctrl@f100000 {
3780 compatible = "qcom,sm8250-pinctrl";
3781 reg = <0 0x0f100000 0 0x300000>,
3782 <0 0x0f500000 0 0x300000>,
3783 <0 0x0f900000 0 0x300000>;
3784 reg-names = "west", "south", "north";
3785 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3786 gpio-controller;
3787 #gpio-cells = <2>;
3788 interrupt-controller;
3789 #interrupt-cells = <2>;
3790 gpio-ranges = <&tlmm 0 0 181>;
3791 wakeup-parent = <&pdc>;
3792
3793 cci0_default: cci0-default {
3794 cci0_i2c0_default: cci0-i2c0-default {
3795 /* SDA, SCL */
3796 pins = "gpio101", "gpio102";
3797 function = "cci_i2c";
3798
3799 bias-pull-up;
3800 drive-strength = <2>; /* 2 mA */
3801 };
3802
3803 cci0_i2c1_default: cci0-i2c1-default {
3804 /* SDA, SCL */
3805 pins = "gpio103", "gpio104";
3806 function = "cci_i2c";
3807
3808 bias-pull-up;
3809 drive-strength = <2>; /* 2 mA */
3810 };
3811 };
3812
3813 cci0_sleep: cci0-sleep {
3814 cci0_i2c0_sleep: cci0-i2c0-sleep {
3815 /* SDA, SCL */
3816 pins = "gpio101", "gpio102";
3817 function = "cci_i2c";
3818
3819 drive-strength = <2>; /* 2 mA */
3820 bias-pull-down;
3821 };
3822
3823 cci0_i2c1_sleep: cci0-i2c1-sleep {
3824 /* SDA, SCL */
3825 pins = "gpio103", "gpio104";
3826 function = "cci_i2c";
3827
3828 drive-strength = <2>; /* 2 mA */
3829 bias-pull-down;
3830 };
3831 };
3832
3833 cci1_default: cci1-default {
3834 cci1_i2c0_default: cci1-i2c0-default {
3835 /* SDA, SCL */
3836 pins = "gpio105","gpio106";
3837 function = "cci_i2c";
3838
3839 bias-pull-up;
3840 drive-strength = <2>; /* 2 mA */
3841 };
3842
3843 cci1_i2c1_default: cci1-i2c1-default {
3844 /* SDA, SCL */
3845 pins = "gpio107","gpio108";
3846 function = "cci_i2c";
3847
3848 bias-pull-up;
3849 drive-strength = <2>; /* 2 mA */
3850 };
3851 };
3852
3853 cci1_sleep: cci1-sleep {
3854 cci1_i2c0_sleep: cci1-i2c0-sleep {
3855 /* SDA, SCL */
3856 pins = "gpio105","gpio106";
3857 function = "cci_i2c";
3858
3859 bias-pull-down;
3860 drive-strength = <2>; /* 2 mA */
3861 };
3862
3863 cci1_i2c1_sleep: cci1-i2c1-sleep {
3864 /* SDA, SCL */
3865 pins = "gpio107","gpio108";
3866 function = "cci_i2c";
3867
3868 bias-pull-down;
3869 drive-strength = <2>; /* 2 mA */
3870 };
3871 };
3872
3873 pri_mi2s_active: pri-mi2s-active {
3874 sclk {
3875 pins = "gpio138";
3876 function = "mi2s0_sck";
3877 drive-strength = <8>;
3878 bias-disable;
3879 };
3880
3881 ws {
3882 pins = "gpio141";
3883 function = "mi2s0_ws";
3884 drive-strength = <8>;
3885 output-high;
3886 };
3887
3888 data0 {
3889 pins = "gpio139";
3890 function = "mi2s0_data0";
3891 drive-strength = <8>;
3892 bias-disable;
3893 output-high;
3894 };
3895
3896 data1 {
3897 pins = "gpio140";
3898 function = "mi2s0_data1";
3899 drive-strength = <8>;
3900 output-high;
3901 };
3902 };
3903
3904 qup_i2c0_default: qup-i2c0-default {
3905 mux {
3906 pins = "gpio28", "gpio29";
3907 function = "qup0";
3908 };
3909
3910 config {
3911 pins = "gpio28", "gpio29";
3912 drive-strength = <2>;
3913 bias-disable;
3914 };
3915 };
3916
3917 qup_i2c1_default: qup-i2c1-default {
3918 pinmux {
3919 pins = "gpio4", "gpio5";
3920 function = "qup1";
3921 };
3922
3923 config {
3924 pins = "gpio4", "gpio5";
3925 drive-strength = <2>;
3926 bias-disable;
3927 };
3928 };
3929
3930 qup_i2c2_default: qup-i2c2-default {
3931 mux {
3932 pins = "gpio115", "gpio116";
3933 function = "qup2";
3934 };
3935
3936 config {
3937 pins = "gpio115", "gpio116";
3938 drive-strength = <2>;
3939 bias-disable;
3940 };
3941 };
3942
3943 qup_i2c3_default: qup-i2c3-default {
3944 mux {
3945 pins = "gpio119", "gpio120";
3946 function = "qup3";
3947 };
3948
3949 config {
3950 pins = "gpio119", "gpio120";
3951 drive-strength = <2>;
3952 bias-disable;
3953 };
3954 };
3955
3956 qup_i2c4_default: qup-i2c4-default {
3957 mux {
3958 pins = "gpio8", "gpio9";
3959 function = "qup4";
3960 };
3961
3962 config {
3963 pins = "gpio8", "gpio9";
3964 drive-strength = <2>;
3965 bias-disable;
3966 };
3967 };
3968
3969 qup_i2c5_default: qup-i2c5-default {
3970 mux {
3971 pins = "gpio12", "gpio13";
3972 function = "qup5";
3973 };
3974
3975 config {
3976 pins = "gpio12", "gpio13";
3977 drive-strength = <2>;
3978 bias-disable;
3979 };
3980 };
3981
3982 qup_i2c6_default: qup-i2c6-default {
3983 mux {
3984 pins = "gpio16", "gpio17";
3985 function = "qup6";
3986 };
3987
3988 config {
3989 pins = "gpio16", "gpio17";
3990 drive-strength = <2>;
3991 bias-disable;
3992 };
3993 };
3994
3995 qup_i2c7_default: qup-i2c7-default {
3996 mux {
3997 pins = "gpio20", "gpio21";
3998 function = "qup7";
3999 };
4000
4001 config {
4002 pins = "gpio20", "gpio21";
4003 drive-strength = <2>;
4004 bias-disable;
4005 };
4006 };
4007
4008 qup_i2c8_default: qup-i2c8-default {
4009 mux {
4010 pins = "gpio24", "gpio25";
4011 function = "qup8";
4012 };
4013
4014 config {
4015 pins = "gpio24", "gpio25";
4016 drive-strength = <2>;
4017 bias-disable;
4018 };
4019 };
4020
4021 qup_i2c9_default: qup-i2c9-default {
4022 mux {
4023 pins = "gpio125", "gpio126";
4024 function = "qup9";
4025 };
4026
4027 config {
4028 pins = "gpio125", "gpio126";
4029 drive-strength = <2>;
4030 bias-disable;
4031 };
4032 };
4033
4034 qup_i2c10_default: qup-i2c10-default {
4035 mux {
4036 pins = "gpio129", "gpio130";
4037 function = "qup10";
4038 };
4039
4040 config {
4041 pins = "gpio129", "gpio130";
4042 drive-strength = <2>;
4043 bias-disable;
4044 };
4045 };
4046
4047 qup_i2c11_default: qup-i2c11-default {
4048 mux {
4049 pins = "gpio60", "gpio61";
4050 function = "qup11";
4051 };
4052
4053 config {
4054 pins = "gpio60", "gpio61";
4055 drive-strength = <2>;
4056 bias-disable;
4057 };
4058 };
4059
4060 qup_i2c12_default: qup-i2c12-default {
4061 mux {
4062 pins = "gpio32", "gpio33";
4063 function = "qup12";
4064 };
4065
4066 config {
4067 pins = "gpio32", "gpio33";
4068 drive-strength = <2>;
4069 bias-disable;
4070 };
4071 };
4072
4073 qup_i2c13_default: qup-i2c13-default {
4074 mux {
4075 pins = "gpio36", "gpio37";
4076 function = "qup13";
4077 };
4078
4079 config {
4080 pins = "gpio36", "gpio37";
4081 drive-strength = <2>;
4082 bias-disable;
4083 };
4084 };
4085
4086 qup_i2c14_default: qup-i2c14-default {
4087 mux {
4088 pins = "gpio40", "gpio41";
4089 function = "qup14";
4090 };
4091
4092 config {
4093 pins = "gpio40", "gpio41";
4094 drive-strength = <2>;
4095 bias-disable;
4096 };
4097 };
4098
4099 qup_i2c15_default: qup-i2c15-default {
4100 mux {
4101 pins = "gpio44", "gpio45";
4102 function = "qup15";
4103 };
4104
4105 config {
4106 pins = "gpio44", "gpio45";
4107 drive-strength = <2>;
4108 bias-disable;
4109 };
4110 };
4111
4112 qup_i2c16_default: qup-i2c16-default {
4113 mux {
4114 pins = "gpio48", "gpio49";
4115 function = "qup16";
4116 };
4117
4118 config {
4119 pins = "gpio48", "gpio49";
4120 drive-strength = <2>;
4121 bias-disable;
4122 };
4123 };
4124
4125 qup_i2c17_default: qup-i2c17-default {
4126 mux {
4127 pins = "gpio52", "gpio53";
4128 function = "qup17";
4129 };
4130
4131 config {
4132 pins = "gpio52", "gpio53";
4133 drive-strength = <2>;
4134 bias-disable;
4135 };
4136 };
4137
4138 qup_i2c18_default: qup-i2c18-default {
4139 mux {
4140 pins = "gpio56", "gpio57";
4141 function = "qup18";
4142 };
4143
4144 config {
4145 pins = "gpio56", "gpio57";
4146 drive-strength = <2>;
4147 bias-disable;
4148 };
4149 };
4150
4151 qup_i2c19_default: qup-i2c19-default {
4152 mux {
4153 pins = "gpio0", "gpio1";
4154 function = "qup19";
4155 };
4156
4157 config {
4158 pins = "gpio0", "gpio1";
4159 drive-strength = <2>;
4160 bias-disable;
4161 };
4162 };
4163
4164 qup_spi0_cs: qup-spi0-cs {
4165 pins = "gpio31";
4166 function = "qup0";
4167 };
4168
4169 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4170 pins = "gpio31";
4171 function = "gpio";
4172 };
4173
4174 qup_spi0_data_clk: qup-spi0-data-clk {
4175 pins = "gpio28", "gpio29",
4176 "gpio30";
4177 function = "qup0";
4178 };
4179
4180 qup_spi1_cs: qup-spi1-cs {
4181 pins = "gpio7";
4182 function = "qup1";
4183 };
4184
4185 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4186 pins = "gpio7";
4187 function = "gpio";
4188 };
4189
4190 qup_spi1_data_clk: qup-spi1-data-clk {
4191 pins = "gpio4", "gpio5",
4192 "gpio6";
4193 function = "qup1";
4194 };
4195
4196 qup_spi2_cs: qup-spi2-cs {
4197 pins = "gpio118";
4198 function = "qup2";
4199 };
4200
4201 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4202 pins = "gpio118";
4203 function = "gpio";
4204 };
4205
4206 qup_spi2_data_clk: qup-spi2-data-clk {
4207 pins = "gpio115", "gpio116",
4208 "gpio117";
4209 function = "qup2";
4210 };
4211
4212 qup_spi3_cs: qup-spi3-cs {
4213 pins = "gpio122";
4214 function = "qup3";
4215 };
4216
4217 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4218 pins = "gpio122";
4219 function = "gpio";
4220 };
4221
4222 qup_spi3_data_clk: qup-spi3-data-clk {
4223 pins = "gpio119", "gpio120",
4224 "gpio121";
4225 function = "qup3";
4226 };
4227
4228 qup_spi4_cs: qup-spi4-cs {
4229 pins = "gpio11";
4230 function = "qup4";
4231 };
4232
4233 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4234 pins = "gpio11";
4235 function = "gpio";
4236 };
4237
4238 qup_spi4_data_clk: qup-spi4-data-clk {
4239 pins = "gpio8", "gpio9",
4240 "gpio10";
4241 function = "qup4";
4242 };
4243
4244 qup_spi5_cs: qup-spi5-cs {
4245 pins = "gpio15";
4246 function = "qup5";
4247 };
4248
4249 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4250 pins = "gpio15";
4251 function = "gpio";
4252 };
4253
4254 qup_spi5_data_clk: qup-spi5-data-clk {
4255 pins = "gpio12", "gpio13",
4256 "gpio14";
4257 function = "qup5";
4258 };
4259
4260 qup_spi6_cs: qup-spi6-cs {
4261 pins = "gpio19";
4262 function = "qup6";
4263 };
4264
4265 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4266 pins = "gpio19";
4267 function = "gpio";
4268 };
4269
4270 qup_spi6_data_clk: qup-spi6-data-clk {
4271 pins = "gpio16", "gpio17",
4272 "gpio18";
4273 function = "qup6";
4274 };
4275
4276 qup_spi7_cs: qup-spi7-cs {
4277 pins = "gpio23";
4278 function = "qup7";
4279 };
4280
4281 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4282 pins = "gpio23";
4283 function = "gpio";
4284 };
4285
4286 qup_spi7_data_clk: qup-spi7-data-clk {
4287 pins = "gpio20", "gpio21",
4288 "gpio22";
4289 function = "qup7";
4290 };
4291
4292 qup_spi8_cs: qup-spi8-cs {
4293 pins = "gpio27";
4294 function = "qup8";
4295 };
4296
4297 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4298 pins = "gpio27";
4299 function = "gpio";
4300 };
4301
4302 qup_spi8_data_clk: qup-spi8-data-clk {
4303 pins = "gpio24", "gpio25",
4304 "gpio26";
4305 function = "qup8";
4306 };
4307
4308 qup_spi9_cs: qup-spi9-cs {
4309 pins = "gpio128";
4310 function = "qup9";
4311 };
4312
4313 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4314 pins = "gpio128";
4315 function = "gpio";
4316 };
4317
4318 qup_spi9_data_clk: qup-spi9-data-clk {
4319 pins = "gpio125", "gpio126",
4320 "gpio127";
4321 function = "qup9";
4322 };
4323
4324 qup_spi10_cs: qup-spi10-cs {
4325 pins = "gpio132";
4326 function = "qup10";
4327 };
4328
4329 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4330 pins = "gpio132";
4331 function = "gpio";
4332 };
4333
4334 qup_spi10_data_clk: qup-spi10-data-clk {
4335 pins = "gpio129", "gpio130",
4336 "gpio131";
4337 function = "qup10";
4338 };
4339
4340 qup_spi11_cs: qup-spi11-cs {
4341 pins = "gpio63";
4342 function = "qup11";
4343 };
4344
4345 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4346 pins = "gpio63";
4347 function = "gpio";
4348 };
4349
4350 qup_spi11_data_clk: qup-spi11-data-clk {
4351 pins = "gpio60", "gpio61",
4352 "gpio62";
4353 function = "qup11";
4354 };
4355
4356 qup_spi12_cs: qup-spi12-cs {
4357 pins = "gpio35";
4358 function = "qup12";
4359 };
4360
4361 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4362 pins = "gpio35";
4363 function = "gpio";
4364 };
4365
4366 qup_spi12_data_clk: qup-spi12-data-clk {
4367 pins = "gpio32", "gpio33",
4368 "gpio34";
4369 function = "qup12";
4370 };
4371
4372 qup_spi13_cs: qup-spi13-cs {
4373 pins = "gpio39";
4374 function = "qup13";
4375 };
4376
4377 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4378 pins = "gpio39";
4379 function = "gpio";
4380 };
4381
4382 qup_spi13_data_clk: qup-spi13-data-clk {
4383 pins = "gpio36", "gpio37",
4384 "gpio38";
4385 function = "qup13";
4386 };
4387
4388 qup_spi14_cs: qup-spi14-cs {
4389 pins = "gpio43";
4390 function = "qup14";
4391 };
4392
4393 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4394 pins = "gpio43";
4395 function = "gpio";
4396 };
4397
4398 qup_spi14_data_clk: qup-spi14-data-clk {
4399 pins = "gpio40", "gpio41",
4400 "gpio42";
4401 function = "qup14";
4402 };
4403
4404 qup_spi15_cs: qup-spi15-cs {
4405 pins = "gpio47";
4406 function = "qup15";
4407 };
4408
4409 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4410 pins = "gpio47";
4411 function = "gpio";
4412 };
4413
4414 qup_spi15_data_clk: qup-spi15-data-clk {
4415 pins = "gpio44", "gpio45",
4416 "gpio46";
4417 function = "qup15";
4418 };
4419
4420 qup_spi16_cs: qup-spi16-cs {
4421 pins = "gpio51";
4422 function = "qup16";
4423 };
4424
4425 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
4426 pins = "gpio51";
4427 function = "gpio";
4428 };
4429
4430 qup_spi16_data_clk: qup-spi16-data-clk {
4431 pins = "gpio48", "gpio49",
4432 "gpio50";
4433 function = "qup16";
4434 };
4435
4436 qup_spi17_cs: qup-spi17-cs {
4437 pins = "gpio55";
4438 function = "qup17";
4439 };
4440
4441 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
4442 pins = "gpio55";
4443 function = "gpio";
4444 };
4445
4446 qup_spi17_data_clk: qup-spi17-data-clk {
4447 pins = "gpio52", "gpio53",
4448 "gpio54";
4449 function = "qup17";
4450 };
4451
4452 qup_spi18_cs: qup-spi18-cs {
4453 pins = "gpio59";
4454 function = "qup18";
4455 };
4456
4457 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
4458 pins = "gpio59";
4459 function = "gpio";
4460 };
4461
4462 qup_spi18_data_clk: qup-spi18-data-clk {
4463 pins = "gpio56", "gpio57",
4464 "gpio58";
4465 function = "qup18";
4466 };
4467
4468 qup_spi19_cs: qup-spi19-cs {
4469 pins = "gpio3";
4470 function = "qup19";
4471 };
4472
4473 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
4474 pins = "gpio3";
4475 function = "gpio";
4476 };
4477
4478 qup_spi19_data_clk: qup-spi19-data-clk {
4479 pins = "gpio0", "gpio1",
4480 "gpio2";
4481 function = "qup19";
4482 };
4483
4484 qup_uart2_default: qup-uart2-default {
4485 mux {
4486 pins = "gpio117", "gpio118";
4487 function = "qup2";
4488 };
4489 };
4490
4491 qup_uart6_default: qup-uart6-default {
4492 mux {
4493 pins = "gpio16", "gpio17",
4494 "gpio18", "gpio19";
4495 function = "qup6";
4496 };
4497 };
4498
4499 qup_uart12_default: qup-uart12-default {
4500 mux {
4501 pins = "gpio34", "gpio35";
4502 function = "qup12";
4503 };
4504 };
4505
4506 qup_uart17_default: qup-uart17-default {
4507 mux {
4508 pins = "gpio52", "gpio53",
4509 "gpio54", "gpio55";
4510 function = "qup17";
4511 };
4512 };
4513
4514 qup_uart18_default: qup-uart18-default {
4515 mux {
4516 pins = "gpio58", "gpio59";
4517 function = "qup18";
4518 };
4519 };
4520
4521 tert_mi2s_active: tert-mi2s-active {
4522 sck {
4523 pins = "gpio133";
4524 function = "mi2s2_sck";
4525 drive-strength = <8>;
4526 bias-disable;
4527 };
4528
4529 data0 {
4530 pins = "gpio134";
4531 function = "mi2s2_data0";
4532 drive-strength = <8>;
4533 bias-disable;
4534 output-high;
4535 };
4536
4537 ws {
4538 pins = "gpio135";
4539 function = "mi2s2_ws";
4540 drive-strength = <8>;
4541 output-high;
4542 };
4543 };
4544
4545 sdc2_sleep_state: sdc2-sleep {
4546 clk {
4547 pins = "sdc2_clk";
4548 drive-strength = <2>;
4549 bias-disable;
4550 };
4551
4552 cmd {
4553 pins = "sdc2_cmd";
4554 drive-strength = <2>;
4555 bias-pull-up;
4556 };
4557
4558 data {
4559 pins = "sdc2_data";
4560 drive-strength = <2>;
4561 bias-pull-up;
4562 };
4563 };
4564
4565 pcie0_default_state: pcie0-default {
4566 perst {
4567 pins = "gpio79";
4568 function = "gpio";
4569 drive-strength = <2>;
4570 bias-pull-down;
4571 };
4572
4573 clkreq {
4574 pins = "gpio80";
4575 function = "pci_e0";
4576 drive-strength = <2>;
4577 bias-pull-up;
4578 };
4579
4580 wake {
4581 pins = "gpio81";
4582 function = "gpio";
4583 drive-strength = <2>;
4584 bias-pull-up;
4585 };
4586 };
4587
4588 pcie1_default_state: pcie1-default {
4589 perst {
4590 pins = "gpio82";
4591 function = "gpio";
4592 drive-strength = <2>;
4593 bias-pull-down;
4594 };
4595
4596 clkreq {
4597 pins = "gpio83";
4598 function = "pci_e1";
4599 drive-strength = <2>;
4600 bias-pull-up;
4601 };
4602
4603 wake {
4604 pins = "gpio84";
4605 function = "gpio";
4606 drive-strength = <2>;
4607 bias-pull-up;
4608 };
4609 };
4610
4611 pcie2_default_state: pcie2-default {
4612 perst {
4613 pins = "gpio85";
4614 function = "gpio";
4615 drive-strength = <2>;
4616 bias-pull-down;
4617 };
4618
4619 clkreq {
4620 pins = "gpio86";
4621 function = "pci_e2";
4622 drive-strength = <2>;
4623 bias-pull-up;
4624 };
4625
4626 wake {
4627 pins = "gpio87";
4628 function = "gpio";
4629 drive-strength = <2>;
4630 bias-pull-up;
4631 };
4632 };
4633 };
4634
4635 apps_smmu: iommu@15000000 {
4636 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
4637 reg = <0 0x15000000 0 0x100000>;
4638 #iommu-cells = <2>;
4639 #global-interrupts = <2>;
4640 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4641 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4642 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4643 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4644 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4645 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4646 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4647 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4648 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4649 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4650 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4651 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4652 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4653 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4654 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4655 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4656 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4657 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4658 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4659 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4660 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4661 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4662 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4663 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4664 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4665 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4666 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4667 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4668 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4669 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4670 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4671 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4672 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4673 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4674 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4675 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4680 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4683 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4684 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4685 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4686 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4687 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4688 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4689 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4690 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4691 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4692 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4693 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4694 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4695 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4696 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4697 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4698 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4699 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4700 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4701 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4702 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4703 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4704 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4705 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4706 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4707 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4708 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4709 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4710 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4711 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4712 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4713 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4714 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4715 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4716 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4717 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4718 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4719 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4720 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4721 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4722 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4723 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4724 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4725 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4726 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4727 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4728 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4729 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4730 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4731 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4732 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4733 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4734 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4735 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4736 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
4737 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
4738 };
4739
4740 adsp: remoteproc@17300000 {
4741 compatible = "qcom,sm8250-adsp-pas";
4742 reg = <0 0x17300000 0 0x100>;
4743
4744 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
4745 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4746 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4747 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4748 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4749 interrupt-names = "wdog", "fatal", "ready",
4750 "handover", "stop-ack";
4751
4752 clocks = <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = "xo";
4754
4755 power-domains = <&rpmhpd SM8250_LCX>,
4756 <&rpmhpd SM8250_LMX>;
4757 power-domain-names = "lcx", "lmx";
4758
4759 memory-region = <&adsp_mem>;
4760
4761 qcom,qmp = <&aoss_qmp>;
4762
4763 qcom,smem-states = <&smp2p_adsp_out 0>;
4764 qcom,smem-state-names = "stop";
4765
4766 status = "disabled";
4767
4768 glink-edge {
4769 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4770 IPCC_MPROC_SIGNAL_GLINK_QMP
4771 IRQ_TYPE_EDGE_RISING>;
4772 mboxes = <&ipcc IPCC_CLIENT_LPASS
4773 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4774
4775 label = "lpass";
4776 qcom,remote-pid = <2>;
4777
4778 apr {
4779 compatible = "qcom,apr-v2";
4780 qcom,glink-channels = "apr_audio_svc";
4781 qcom,domain = <APR_DOMAIN_ADSP>;
4782 #address-cells = <1>;
4783 #size-cells = <0>;
4784
4785 apr-service@3 {
4786 reg = <APR_SVC_ADSP_CORE>;
4787 compatible = "qcom,q6core";
4788 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4789 };
4790
4791 q6afe: apr-service@4 {
4792 compatible = "qcom,q6afe";
4793 reg = <APR_SVC_AFE>;
4794 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4795 q6afedai: dais {
4796 compatible = "qcom,q6afe-dais";
4797 #address-cells = <1>;
4798 #size-cells = <0>;
4799 #sound-dai-cells = <1>;
4800 };
4801
4802 q6afecc: cc {
4803 compatible = "qcom,q6afe-clocks";
4804 #clock-cells = <2>;
4805 };
4806 };
4807
4808 q6asm: apr-service@7 {
4809 compatible = "qcom,q6asm";
4810 reg = <APR_SVC_ASM>;
4811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4812 q6asmdai: dais {
4813 compatible = "qcom,q6asm-dais";
4814 #address-cells = <1>;
4815 #size-cells = <0>;
4816 #sound-dai-cells = <1>;
4817 iommus = <&apps_smmu 0x1801 0x0>;
4818 };
4819 };
4820
4821 q6adm: apr-service@8 {
4822 compatible = "qcom,q6adm";
4823 reg = <APR_SVC_ADM>;
4824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4825 q6routing: routing {
4826 compatible = "qcom,q6adm-routing";
4827 #sound-dai-cells = <0>;
4828 };
4829 };
4830 };
4831
4832 fastrpc {
4833 compatible = "qcom,fastrpc";
4834 qcom,glink-channels = "fastrpcglink-apps-dsp";
4835 label = "adsp";
4836 qcom,non-secure-domain;
4837 #address-cells = <1>;
4838 #size-cells = <0>;
4839
4840 compute-cb@3 {
4841 compatible = "qcom,fastrpc-compute-cb";
4842 reg = <3>;
4843 iommus = <&apps_smmu 0x1803 0x0>;
4844 };
4845
4846 compute-cb@4 {
4847 compatible = "qcom,fastrpc-compute-cb";
4848 reg = <4>;
4849 iommus = <&apps_smmu 0x1804 0x0>;
4850 };
4851
4852 compute-cb@5 {
4853 compatible = "qcom,fastrpc-compute-cb";
4854 reg = <5>;
4855 iommus = <&apps_smmu 0x1805 0x0>;
4856 };
4857 };
4858 };
4859 };
4860
4861 intc: interrupt-controller@17a00000 {
4862 compatible = "arm,gic-v3";
4863 #interrupt-cells = <3>;
4864 interrupt-controller;
4865 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4866 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4867 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4868 };
4869
4870 watchdog@17c10000 {
4871 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
4872 reg = <0 0x17c10000 0 0x1000>;
4873 clocks = <&sleep_clk>;
4874 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4875 };
4876
4877 timer@17c20000 {
4878 #address-cells = <1>;
4879 #size-cells = <1>;
4880 ranges = <0 0 0 0x20000000>;
4881 compatible = "arm,armv7-timer-mem";
4882 reg = <0x0 0x17c20000 0x0 0x1000>;
4883 clock-frequency = <19200000>;
4884
4885 frame@17c21000 {
4886 frame-number = <0>;
4887 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4888 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4889 reg = <0x17c21000 0x1000>,
4890 <0x17c22000 0x1000>;
4891 };
4892
4893 frame@17c23000 {
4894 frame-number = <1>;
4895 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4896 reg = <0x17c23000 0x1000>;
4897 status = "disabled";
4898 };
4899
4900 frame@17c25000 {
4901 frame-number = <2>;
4902 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4903 reg = <0x17c25000 0x1000>;
4904 status = "disabled";
4905 };
4906
4907 frame@17c27000 {
4908 frame-number = <3>;
4909 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4910 reg = <0x17c27000 0x1000>;
4911 status = "disabled";
4912 };
4913
4914 frame@17c29000 {
4915 frame-number = <4>;
4916 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4917 reg = <0x17c29000 0x1000>;
4918 status = "disabled";
4919 };
4920
4921 frame@17c2b000 {
4922 frame-number = <5>;
4923 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4924 reg = <0x17c2b000 0x1000>;
4925 status = "disabled";
4926 };
4927
4928 frame@17c2d000 {
4929 frame-number = <6>;
4930 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4931 reg = <0x17c2d000 0x1000>;
4932 status = "disabled";
4933 };
4934 };
4935
4936 apps_rsc: rsc@18200000 {
4937 label = "apps_rsc";
4938 compatible = "qcom,rpmh-rsc";
4939 reg = <0x0 0x18200000 0x0 0x10000>,
4940 <0x0 0x18210000 0x0 0x10000>,
4941 <0x0 0x18220000 0x0 0x10000>;
4942 reg-names = "drv-0", "drv-1", "drv-2";
4943 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4944 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4945 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4946 qcom,tcs-offset = <0xd00>;
4947 qcom,drv-id = <2>;
4948 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4949 <WAKE_TCS 3>, <CONTROL_TCS 1>;
4950
4951 rpmhcc: clock-controller {
4952 compatible = "qcom,sm8250-rpmh-clk";
4953 #clock-cells = <1>;
4954 clock-names = "xo";
4955 clocks = <&xo_board>;
4956 };
4957
4958 rpmhpd: power-controller {
4959 compatible = "qcom,sm8250-rpmhpd";
4960 #power-domain-cells = <1>;
4961 operating-points-v2 = <&rpmhpd_opp_table>;
4962
4963 rpmhpd_opp_table: opp-table {
4964 compatible = "operating-points-v2";
4965
4966 rpmhpd_opp_ret: opp1 {
4967 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4968 };
4969
4970 rpmhpd_opp_min_svs: opp2 {
4971 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4972 };
4973
4974 rpmhpd_opp_low_svs: opp3 {
4975 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4976 };
4977
4978 rpmhpd_opp_svs: opp4 {
4979 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4980 };
4981
4982 rpmhpd_opp_svs_l1: opp5 {
4983 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4984 };
4985
4986 rpmhpd_opp_nom: opp6 {
4987 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4988 };
4989
4990 rpmhpd_opp_nom_l1: opp7 {
4991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4992 };
4993
4994 rpmhpd_opp_nom_l2: opp8 {
4995 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4996 };
4997
4998 rpmhpd_opp_turbo: opp9 {
4999 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5000 };
5001
5002 rpmhpd_opp_turbo_l1: opp10 {
5003 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5004 };
5005 };
5006 };
5007
5008 apps_bcm_voter: bcm-voter {
5009 compatible = "qcom,bcm-voter";
5010 };
5011 };
5012
5013 epss_l3: interconnect@18590000 {
5014 compatible = "qcom,sm8250-epss-l3";
5015 reg = <0 0x18590000 0 0x1000>;
5016
5017 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5018 clock-names = "xo", "alternate";
5019
5020 #interconnect-cells = <1>;
5021 };
5022
5023 cpufreq_hw: cpufreq@18591000 {
5024 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5025 reg = <0 0x18591000 0 0x1000>,
5026 <0 0x18592000 0 0x1000>,
5027 <0 0x18593000 0 0x1000>;
5028 reg-names = "freq-domain0", "freq-domain1",
5029 "freq-domain2";
5030
5031 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5032 clock-names = "xo", "alternate";
5033 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5034 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5035 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5036 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5037 #freq-domain-cells = <1>;
5038 };
5039 };
5040
5041 timer {
5042 compatible = "arm,armv8-timer";
5043 interrupts = <GIC_PPI 13
5044 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5045 <GIC_PPI 14
5046 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5047 <GIC_PPI 11
5048 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5049 <GIC_PPI 10
5050 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5051 };
5052
5053 thermal-zones {
5054 cpu0-thermal {
5055 polling-delay-passive = <250>;
5056 polling-delay = <1000>;
5057
5058 thermal-sensors = <&tsens0 1>;
5059
5060 trips {
5061 cpu0_alert0: trip-point0 {
5062 temperature = <90000>;
5063 hysteresis = <2000>;
5064 type = "passive";
5065 };
5066
5067 cpu0_alert1: trip-point1 {
5068 temperature = <95000>;
5069 hysteresis = <2000>;
5070 type = "passive";
5071 };
5072
5073 cpu0_crit: cpu_crit {
5074 temperature = <110000>;
5075 hysteresis = <1000>;
5076 type = "critical";
5077 };
5078 };
5079
5080 cooling-maps {
5081 map0 {
5082 trip = <&cpu0_alert0>;
5083 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5084 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5085 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5086 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5087 };
5088 map1 {
5089 trip = <&cpu0_alert1>;
5090 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5091 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5092 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5093 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5094 };
5095 };
5096 };
5097
5098 cpu1-thermal {
5099 polling-delay-passive = <250>;
5100 polling-delay = <1000>;
5101
5102 thermal-sensors = <&tsens0 2>;
5103
5104 trips {
5105 cpu1_alert0: trip-point0 {
5106 temperature = <90000>;
5107 hysteresis = <2000>;
5108 type = "passive";
5109 };
5110
5111 cpu1_alert1: trip-point1 {
5112 temperature = <95000>;
5113 hysteresis = <2000>;
5114 type = "passive";
5115 };
5116
5117 cpu1_crit: cpu_crit {
5118 temperature = <110000>;
5119 hysteresis = <1000>;
5120 type = "critical";
5121 };
5122 };
5123
5124 cooling-maps {
5125 map0 {
5126 trip = <&cpu1_alert0>;
5127 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5128 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5129 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5130 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5131 };
5132 map1 {
5133 trip = <&cpu1_alert1>;
5134 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5135 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5136 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5137 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5138 };
5139 };
5140 };
5141
5142 cpu2-thermal {
5143 polling-delay-passive = <250>;
5144 polling-delay = <1000>;
5145
5146 thermal-sensors = <&tsens0 3>;
5147
5148 trips {
5149 cpu2_alert0: trip-point0 {
5150 temperature = <90000>;
5151 hysteresis = <2000>;
5152 type = "passive";
5153 };
5154
5155 cpu2_alert1: trip-point1 {
5156 temperature = <95000>;
5157 hysteresis = <2000>;
5158 type = "passive";
5159 };
5160
5161 cpu2_crit: cpu_crit {
5162 temperature = <110000>;
5163 hysteresis = <1000>;
5164 type = "critical";
5165 };
5166 };
5167
5168 cooling-maps {
5169 map0 {
5170 trip = <&cpu2_alert0>;
5171 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5172 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5173 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5174 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5175 };
5176 map1 {
5177 trip = <&cpu2_alert1>;
5178 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5179 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5180 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5181 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5182 };
5183 };
5184 };
5185
5186 cpu3-thermal {
5187 polling-delay-passive = <250>;
5188 polling-delay = <1000>;
5189
5190 thermal-sensors = <&tsens0 4>;
5191
5192 trips {
5193 cpu3_alert0: trip-point0 {
5194 temperature = <90000>;
5195 hysteresis = <2000>;
5196 type = "passive";
5197 };
5198
5199 cpu3_alert1: trip-point1 {
5200 temperature = <95000>;
5201 hysteresis = <2000>;
5202 type = "passive";
5203 };
5204
5205 cpu3_crit: cpu_crit {
5206 temperature = <110000>;
5207 hysteresis = <1000>;
5208 type = "critical";
5209 };
5210 };
5211
5212 cooling-maps {
5213 map0 {
5214 trip = <&cpu3_alert0>;
5215 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5216 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5217 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5218 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5219 };
5220 map1 {
5221 trip = <&cpu3_alert1>;
5222 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5223 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5224 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5225 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5226 };
5227 };
5228 };
5229
5230 cpu4-top-thermal {
5231 polling-delay-passive = <250>;
5232 polling-delay = <1000>;
5233
5234 thermal-sensors = <&tsens0 7>;
5235
5236 trips {
5237 cpu4_top_alert0: trip-point0 {
5238 temperature = <90000>;
5239 hysteresis = <2000>;
5240 type = "passive";
5241 };
5242
5243 cpu4_top_alert1: trip-point1 {
5244 temperature = <95000>;
5245 hysteresis = <2000>;
5246 type = "passive";
5247 };
5248
5249 cpu4_top_crit: cpu_crit {
5250 temperature = <110000>;
5251 hysteresis = <1000>;
5252 type = "critical";
5253 };
5254 };
5255
5256 cooling-maps {
5257 map0 {
5258 trip = <&cpu4_top_alert0>;
5259 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5260 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5261 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5262 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5263 };
5264 map1 {
5265 trip = <&cpu4_top_alert1>;
5266 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5267 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5268 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5269 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5270 };
5271 };
5272 };
5273
5274 cpu5-top-thermal {
5275 polling-delay-passive = <250>;
5276 polling-delay = <1000>;
5277
5278 thermal-sensors = <&tsens0 8>;
5279
5280 trips {
5281 cpu5_top_alert0: trip-point0 {
5282 temperature = <90000>;
5283 hysteresis = <2000>;
5284 type = "passive";
5285 };
5286
5287 cpu5_top_alert1: trip-point1 {
5288 temperature = <95000>;
5289 hysteresis = <2000>;
5290 type = "passive";
5291 };
5292
5293 cpu5_top_crit: cpu_crit {
5294 temperature = <110000>;
5295 hysteresis = <1000>;
5296 type = "critical";
5297 };
5298 };
5299
5300 cooling-maps {
5301 map0 {
5302 trip = <&cpu5_top_alert0>;
5303 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5304 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5305 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5306 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5307 };
5308 map1 {
5309 trip = <&cpu5_top_alert1>;
5310 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5311 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5312 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5313 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5314 };
5315 };
5316 };
5317
5318 cpu6-top-thermal {
5319 polling-delay-passive = <250>;
5320 polling-delay = <1000>;
5321
5322 thermal-sensors = <&tsens0 9>;
5323
5324 trips {
5325 cpu6_top_alert0: trip-point0 {
5326 temperature = <90000>;
5327 hysteresis = <2000>;
5328 type = "passive";
5329 };
5330
5331 cpu6_top_alert1: trip-point1 {
5332 temperature = <95000>;
5333 hysteresis = <2000>;
5334 type = "passive";
5335 };
5336
5337 cpu6_top_crit: cpu_crit {
5338 temperature = <110000>;
5339 hysteresis = <1000>;
5340 type = "critical";
5341 };
5342 };
5343
5344 cooling-maps {
5345 map0 {
5346 trip = <&cpu6_top_alert0>;
5347 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5348 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5349 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5350 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5351 };
5352 map1 {
5353 trip = <&cpu6_top_alert1>;
5354 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5355 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5356 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5357 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5358 };
5359 };
5360 };
5361
5362 cpu7-top-thermal {
5363 polling-delay-passive = <250>;
5364 polling-delay = <1000>;
5365
5366 thermal-sensors = <&tsens0 10>;
5367
5368 trips {
5369 cpu7_top_alert0: trip-point0 {
5370 temperature = <90000>;
5371 hysteresis = <2000>;
5372 type = "passive";
5373 };
5374
5375 cpu7_top_alert1: trip-point1 {
5376 temperature = <95000>;
5377 hysteresis = <2000>;
5378 type = "passive";
5379 };
5380
5381 cpu7_top_crit: cpu_crit {
5382 temperature = <110000>;
5383 hysteresis = <1000>;
5384 type = "critical";
5385 };
5386 };
5387
5388 cooling-maps {
5389 map0 {
5390 trip = <&cpu7_top_alert0>;
5391 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5392 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5393 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5394 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5395 };
5396 map1 {
5397 trip = <&cpu7_top_alert1>;
5398 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5399 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5400 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5401 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5402 };
5403 };
5404 };
5405
5406 cpu4-bottom-thermal {
5407 polling-delay-passive = <250>;
5408 polling-delay = <1000>;
5409
5410 thermal-sensors = <&tsens0 11>;
5411
5412 trips {
5413 cpu4_bottom_alert0: trip-point0 {
5414 temperature = <90000>;
5415 hysteresis = <2000>;
5416 type = "passive";
5417 };
5418
5419 cpu4_bottom_alert1: trip-point1 {
5420 temperature = <95000>;
5421 hysteresis = <2000>;
5422 type = "passive";
5423 };
5424
5425 cpu4_bottom_crit: cpu_crit {
5426 temperature = <110000>;
5427 hysteresis = <1000>;
5428 type = "critical";
5429 };
5430 };
5431
5432 cooling-maps {
5433 map0 {
5434 trip = <&cpu4_bottom_alert0>;
5435 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5436 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5437 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5438 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5439 };
5440 map1 {
5441 trip = <&cpu4_bottom_alert1>;
5442 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5443 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5444 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5445 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5446 };
5447 };
5448 };
5449
5450 cpu5-bottom-thermal {
5451 polling-delay-passive = <250>;
5452 polling-delay = <1000>;
5453
5454 thermal-sensors = <&tsens0 12>;
5455
5456 trips {
5457 cpu5_bottom_alert0: trip-point0 {
5458 temperature = <90000>;
5459 hysteresis = <2000>;
5460 type = "passive";
5461 };
5462
5463 cpu5_bottom_alert1: trip-point1 {
5464 temperature = <95000>;
5465 hysteresis = <2000>;
5466 type = "passive";
5467 };
5468
5469 cpu5_bottom_crit: cpu_crit {
5470 temperature = <110000>;
5471 hysteresis = <1000>;
5472 type = "critical";
5473 };
5474 };
5475
5476 cooling-maps {
5477 map0 {
5478 trip = <&cpu5_bottom_alert0>;
5479 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5480 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5481 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5482 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5483 };
5484 map1 {
5485 trip = <&cpu5_bottom_alert1>;
5486 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5487 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5488 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5489 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5490 };
5491 };
5492 };
5493
5494 cpu6-bottom-thermal {
5495 polling-delay-passive = <250>;
5496 polling-delay = <1000>;
5497
5498 thermal-sensors = <&tsens0 13>;
5499
5500 trips {
5501 cpu6_bottom_alert0: trip-point0 {
5502 temperature = <90000>;
5503 hysteresis = <2000>;
5504 type = "passive";
5505 };
5506
5507 cpu6_bottom_alert1: trip-point1 {
5508 temperature = <95000>;
5509 hysteresis = <2000>;
5510 type = "passive";
5511 };
5512
5513 cpu6_bottom_crit: cpu_crit {
5514 temperature = <110000>;
5515 hysteresis = <1000>;
5516 type = "critical";
5517 };
5518 };
5519
5520 cooling-maps {
5521 map0 {
5522 trip = <&cpu6_bottom_alert0>;
5523 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5524 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5525 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5526 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5527 };
5528 map1 {
5529 trip = <&cpu6_bottom_alert1>;
5530 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5531 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5532 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5533 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5534 };
5535 };
5536 };
5537
5538 cpu7-bottom-thermal {
5539 polling-delay-passive = <250>;
5540 polling-delay = <1000>;
5541
5542 thermal-sensors = <&tsens0 14>;
5543
5544 trips {
5545 cpu7_bottom_alert0: trip-point0 {
5546 temperature = <90000>;
5547 hysteresis = <2000>;
5548 type = "passive";
5549 };
5550
5551 cpu7_bottom_alert1: trip-point1 {
5552 temperature = <95000>;
5553 hysteresis = <2000>;
5554 type = "passive";
5555 };
5556
5557 cpu7_bottom_crit: cpu_crit {
5558 temperature = <110000>;
5559 hysteresis = <1000>;
5560 type = "critical";
5561 };
5562 };
5563
5564 cooling-maps {
5565 map0 {
5566 trip = <&cpu7_bottom_alert0>;
5567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5571 };
5572 map1 {
5573 trip = <&cpu7_bottom_alert1>;
5574 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5575 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5576 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5577 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5578 };
5579 };
5580 };
5581
5582 aoss0-thermal {
5583 polling-delay-passive = <250>;
5584 polling-delay = <1000>;
5585
5586 thermal-sensors = <&tsens0 0>;
5587
5588 trips {
5589 aoss0_alert0: trip-point0 {
5590 temperature = <90000>;
5591 hysteresis = <2000>;
5592 type = "hot";
5593 };
5594 };
5595 };
5596
5597 cluster0-thermal {
5598 polling-delay-passive = <250>;
5599 polling-delay = <1000>;
5600
5601 thermal-sensors = <&tsens0 5>;
5602
5603 trips {
5604 cluster0_alert0: trip-point0 {
5605 temperature = <90000>;
5606 hysteresis = <2000>;
5607 type = "hot";
5608 };
5609 cluster0_crit: cluster0_crit {
5610 temperature = <110000>;
5611 hysteresis = <2000>;
5612 type = "critical";
5613 };
5614 };
5615 };
5616
5617 cluster1-thermal {
5618 polling-delay-passive = <250>;
5619 polling-delay = <1000>;
5620
5621 thermal-sensors = <&tsens0 6>;
5622
5623 trips {
5624 cluster1_alert0: trip-point0 {
5625 temperature = <90000>;
5626 hysteresis = <2000>;
5627 type = "hot";
5628 };
5629 cluster1_crit: cluster1_crit {
5630 temperature = <110000>;
5631 hysteresis = <2000>;
5632 type = "critical";
5633 };
5634 };
5635 };
5636
5637 gpu-top-thermal {
5638 polling-delay-passive = <250>;
5639 polling-delay = <1000>;
5640
5641 thermal-sensors = <&tsens0 15>;
5642
5643 trips {
5644 gpu1_alert0: trip-point0 {
5645 temperature = <90000>;
5646 hysteresis = <2000>;
5647 type = "hot";
5648 };
5649 };
5650 };
5651
5652 aoss1-thermal {
5653 polling-delay-passive = <250>;
5654 polling-delay = <1000>;
5655
5656 thermal-sensors = <&tsens1 0>;
5657
5658 trips {
5659 aoss1_alert0: trip-point0 {
5660 temperature = <90000>;
5661 hysteresis = <2000>;
5662 type = "hot";
5663 };
5664 };
5665 };
5666
5667 wlan-thermal {
5668 polling-delay-passive = <250>;
5669 polling-delay = <1000>;
5670
5671 thermal-sensors = <&tsens1 1>;
5672
5673 trips {
5674 wlan_alert0: trip-point0 {
5675 temperature = <90000>;
5676 hysteresis = <2000>;
5677 type = "hot";
5678 };
5679 };
5680 };
5681
5682 video-thermal {
5683 polling-delay-passive = <250>;
5684 polling-delay = <1000>;
5685
5686 thermal-sensors = <&tsens1 2>;
5687
5688 trips {
5689 video_alert0: trip-point0 {
5690 temperature = <90000>;
5691 hysteresis = <2000>;
5692 type = "hot";
5693 };
5694 };
5695 };
5696
5697 mem-thermal {
5698 polling-delay-passive = <250>;
5699 polling-delay = <1000>;
5700
5701 thermal-sensors = <&tsens1 3>;
5702
5703 trips {
5704 mem_alert0: trip-point0 {
5705 temperature = <90000>;
5706 hysteresis = <2000>;
5707 type = "hot";
5708 };
5709 };
5710 };
5711
5712 q6-hvx-thermal {
5713 polling-delay-passive = <250>;
5714 polling-delay = <1000>;
5715
5716 thermal-sensors = <&tsens1 4>;
5717
5718 trips {
5719 q6_hvx_alert0: trip-point0 {
5720 temperature = <90000>;
5721 hysteresis = <2000>;
5722 type = "hot";
5723 };
5724 };
5725 };
5726
5727 camera-thermal {
5728 polling-delay-passive = <250>;
5729 polling-delay = <1000>;
5730
5731 thermal-sensors = <&tsens1 5>;
5732
5733 trips {
5734 camera_alert0: trip-point0 {
5735 temperature = <90000>;
5736 hysteresis = <2000>;
5737 type = "hot";
5738 };
5739 };
5740 };
5741
5742 compute-thermal {
5743 polling-delay-passive = <250>;
5744 polling-delay = <1000>;
5745
5746 thermal-sensors = <&tsens1 6>;
5747
5748 trips {
5749 compute_alert0: trip-point0 {
5750 temperature = <90000>;
5751 hysteresis = <2000>;
5752 type = "hot";
5753 };
5754 };
5755 };
5756
5757 npu-thermal {
5758 polling-delay-passive = <250>;
5759 polling-delay = <1000>;
5760
5761 thermal-sensors = <&tsens1 7>;
5762
5763 trips {
5764 npu_alert0: trip-point0 {
5765 temperature = <90000>;
5766 hysteresis = <2000>;
5767 type = "hot";
5768 };
5769 };
5770 };
5771
5772 gpu-bottom-thermal {
5773 polling-delay-passive = <250>;
5774 polling-delay = <1000>;
5775
5776 thermal-sensors = <&tsens1 8>;
5777
5778 trips {
5779 gpu2_alert0: trip-point0 {
5780 temperature = <90000>;
5781 hysteresis = <2000>;
5782 type = "hot";
5783 };
5784 };
5785 };
5786 };
5787 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|