0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
0004 * Copyright (c) 2022, Linaro Limited
0005 */
0006
0007 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
0008 #include <dt-bindings/clock/qcom,rpmh.h>
0009 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/mailbox/qcom-ipcc.h>
0012 #include <dt-bindings/power/qcom-rpmpd.h>
0013 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0014 #include <dt-bindings/thermal/thermal.h>
0015
0016 / {
0017 interrupt-parent = <&intc>;
0018
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 clocks {
0023 xo_board_clk: xo-board-clk {
0024 compatible = "fixed-clock";
0025 #clock-cells = <0>;
0026 };
0027
0028 sleep_clk: sleep-clk {
0029 compatible = "fixed-clock";
0030 #clock-cells = <0>;
0031 clock-frequency = <32764>;
0032 };
0033 };
0034
0035 cpu0_opp_table: cpu0-opp-table {
0036 compatible = "operating-points-v2";
0037 opp-shared;
0038
0039 opp-300000000 {
0040 opp-hz = /bits/ 64 <300000000>;
0041 };
0042 opp-403200000 {
0043 opp-hz = /bits/ 64 <403200000>;
0044 };
0045 opp-499200000 {
0046 opp-hz = /bits/ 64 <499200000>;
0047 };
0048 opp-595200000 {
0049 opp-hz = /bits/ 64 <595200000>;
0050 };
0051 opp-691200000 {
0052 opp-hz = /bits/ 64 <691200000>;
0053 };
0054 opp-806400000 {
0055 opp-hz = /bits/ 64 <806400000>;
0056 };
0057 opp-902400000 {
0058 opp-hz = /bits/ 64 <902400000>;
0059 };
0060 opp-1017600000 {
0061 opp-hz = /bits/ 64 <1017600000>;
0062 };
0063 opp-1113600000 {
0064 opp-hz = /bits/ 64 <1113600000>;
0065 };
0066 opp-1209600000 {
0067 opp-hz = /bits/ 64 <1209600000>;
0068 };
0069 opp-1324800000 {
0070 opp-hz = /bits/ 64 <1324800000>;
0071 };
0072 opp-1440000000 {
0073 opp-hz = /bits/ 64 <1440000000>;
0074 };
0075 opp-1555200000 {
0076 opp-hz = /bits/ 64 <1555200000>;
0077 };
0078 opp-1670400000 {
0079 opp-hz = /bits/ 64 <1670400000>;
0080 };
0081 opp-1785600000 {
0082 opp-hz = /bits/ 64 <1785600000>;
0083 };
0084 opp-1881600000 {
0085 opp-hz = /bits/ 64 <1881600000>;
0086 };
0087 opp-1996800000 {
0088 opp-hz = /bits/ 64 <1996800000>;
0089 };
0090 opp-2112000000 {
0091 opp-hz = /bits/ 64 <2112000000>;
0092 };
0093 opp-2227200000 {
0094 opp-hz = /bits/ 64 <2227200000>;
0095 };
0096 opp-2342400000 {
0097 opp-hz = /bits/ 64 <2342400000>;
0098 };
0099 opp-2438400000 {
0100 opp-hz = /bits/ 64 <2438400000>;
0101 };
0102 };
0103
0104 cpu4_opp_table: cpu4-opp-table {
0105 compatible = "operating-points-v2";
0106 opp-shared;
0107
0108 opp-825600000 {
0109 opp-hz = /bits/ 64 <825600000>;
0110 };
0111 opp-940800000 {
0112 opp-hz = /bits/ 64 <940800000>;
0113 };
0114 opp-1056000000 {
0115 opp-hz = /bits/ 64 <1056000000>;
0116 };
0117 opp-1171200000 {
0118 opp-hz = /bits/ 64 <1171200000>;
0119 };
0120 opp-1286400000 {
0121 opp-hz = /bits/ 64 <1286400000>;
0122 };
0123 opp-1401600000 {
0124 opp-hz = /bits/ 64 <1401600000>;
0125 };
0126 opp-1516800000 {
0127 opp-hz = /bits/ 64 <1516800000>;
0128 };
0129 opp-1632000000 {
0130 opp-hz = /bits/ 64 <1632000000>;
0131 };
0132 opp-1747200000 {
0133 opp-hz = /bits/ 64 <1747200000>;
0134 };
0135 opp-1862400000 {
0136 opp-hz = /bits/ 64 <1862400000>;
0137 };
0138 opp-1977600000 {
0139 opp-hz = /bits/ 64 <1977600000>;
0140 };
0141 opp-2073600000 {
0142 opp-hz = /bits/ 64 <2073600000>;
0143 };
0144 opp-2169600000 {
0145 opp-hz = /bits/ 64 <2169600000>;
0146 };
0147 opp-2284800000 {
0148 opp-hz = /bits/ 64 <2284800000>;
0149 };
0150 opp-2400000000 {
0151 opp-hz = /bits/ 64 <2400000000>;
0152 };
0153 opp-2496000000 {
0154 opp-hz = /bits/ 64 <2496000000>;
0155 };
0156 opp-2592000000 {
0157 opp-hz = /bits/ 64 <2592000000>;
0158 };
0159 opp-2688000000 {
0160 opp-hz = /bits/ 64 <2688000000>;
0161 };
0162 opp-2803200000 {
0163 opp-hz = /bits/ 64 <2803200000>;
0164 };
0165 opp-2899200000 {
0166 opp-hz = /bits/ 64 <2899200000>;
0167 };
0168 opp-2995200000 {
0169 opp-hz = /bits/ 64 <2995200000>;
0170 };
0171 };
0172
0173 cpus {
0174 #address-cells = <2>;
0175 #size-cells = <0>;
0176
0177 CPU0: cpu@0 {
0178 device_type = "cpu";
0179 compatible = "qcom,kryo";
0180 reg = <0x0 0x0>;
0181 enable-method = "psci";
0182 capacity-dmips-mhz = <602>;
0183 next-level-cache = <&L2_0>;
0184 power-domains = <&CPU_PD0>;
0185 power-domain-names = "psci";
0186 qcom,freq-domain = <&cpufreq_hw 0>;
0187 operating-points-v2 = <&cpu0_opp_table>;
0188 #cooling-cells = <2>;
0189 L2_0: l2-cache {
0190 compatible = "cache";
0191 next-level-cache = <&L3_0>;
0192 L3_0: l3-cache {
0193 compatible = "cache";
0194 };
0195 };
0196 };
0197
0198 CPU1: cpu@100 {
0199 device_type = "cpu";
0200 compatible = "qcom,kryo";
0201 reg = <0x0 0x100>;
0202 enable-method = "psci";
0203 capacity-dmips-mhz = <602>;
0204 next-level-cache = <&L2_100>;
0205 power-domains = <&CPU_PD1>;
0206 power-domain-names = "psci";
0207 qcom,freq-domain = <&cpufreq_hw 0>;
0208 operating-points-v2 = <&cpu0_opp_table>;
0209 #cooling-cells = <2>;
0210 L2_100: l2-cache {
0211 compatible = "cache";
0212 next-level-cache = <&L3_0>;
0213 };
0214 };
0215
0216 CPU2: cpu@200 {
0217 device_type = "cpu";
0218 compatible = "qcom,kryo";
0219 reg = <0x0 0x200>;
0220 enable-method = "psci";
0221 capacity-dmips-mhz = <602>;
0222 next-level-cache = <&L2_200>;
0223 power-domains = <&CPU_PD2>;
0224 power-domain-names = "psci";
0225 qcom,freq-domain = <&cpufreq_hw 0>;
0226 operating-points-v2 = <&cpu0_opp_table>;
0227 #cooling-cells = <2>;
0228 L2_200: l2-cache {
0229 compatible = "cache";
0230 next-level-cache = <&L3_0>;
0231 };
0232 };
0233
0234 CPU3: cpu@300 {
0235 device_type = "cpu";
0236 compatible = "qcom,kryo";
0237 reg = <0x0 0x300>;
0238 enable-method = "psci";
0239 capacity-dmips-mhz = <602>;
0240 next-level-cache = <&L2_300>;
0241 power-domains = <&CPU_PD3>;
0242 power-domain-names = "psci";
0243 qcom,freq-domain = <&cpufreq_hw 0>;
0244 operating-points-v2 = <&cpu0_opp_table>;
0245 #cooling-cells = <2>;
0246 L2_300: l2-cache {
0247 compatible = "cache";
0248 next-level-cache = <&L3_0>;
0249 };
0250 };
0251
0252 CPU4: cpu@400 {
0253 device_type = "cpu";
0254 compatible = "qcom,kryo";
0255 reg = <0x0 0x400>;
0256 enable-method = "psci";
0257 capacity-dmips-mhz = <1024>;
0258 next-level-cache = <&L2_400>;
0259 power-domains = <&CPU_PD4>;
0260 power-domain-names = "psci";
0261 qcom,freq-domain = <&cpufreq_hw 1>;
0262 operating-points-v2 = <&cpu4_opp_table>;
0263 #cooling-cells = <2>;
0264 L2_400: l2-cache {
0265 compatible = "cache";
0266 next-level-cache = <&L3_0>;
0267 };
0268 };
0269
0270 CPU5: cpu@500 {
0271 device_type = "cpu";
0272 compatible = "qcom,kryo";
0273 reg = <0x0 0x500>;
0274 enable-method = "psci";
0275 capacity-dmips-mhz = <1024>;
0276 next-level-cache = <&L2_500>;
0277 power-domains = <&CPU_PD5>;
0278 power-domain-names = "psci";
0279 qcom,freq-domain = <&cpufreq_hw 1>;
0280 operating-points-v2 = <&cpu4_opp_table>;
0281 #cooling-cells = <2>;
0282 L2_500: l2-cache {
0283 compatible = "cache";
0284 next-level-cache = <&L3_0>;
0285 };
0286 };
0287
0288 CPU6: cpu@600 {
0289 device_type = "cpu";
0290 compatible = "qcom,kryo";
0291 reg = <0x0 0x600>;
0292 enable-method = "psci";
0293 capacity-dmips-mhz = <1024>;
0294 next-level-cache = <&L2_600>;
0295 power-domains = <&CPU_PD6>;
0296 power-domain-names = "psci";
0297 qcom,freq-domain = <&cpufreq_hw 1>;
0298 operating-points-v2 = <&cpu4_opp_table>;
0299 #cooling-cells = <2>;
0300 L2_600: l2-cache {
0301 compatible = "cache";
0302 next-level-cache = <&L3_0>;
0303 };
0304 };
0305
0306 CPU7: cpu@700 {
0307 device_type = "cpu";
0308 compatible = "qcom,kryo";
0309 reg = <0x0 0x700>;
0310 enable-method = "psci";
0311 capacity-dmips-mhz = <1024>;
0312 next-level-cache = <&L2_700>;
0313 power-domains = <&CPU_PD7>;
0314 power-domain-names = "psci";
0315 qcom,freq-domain = <&cpufreq_hw 1>;
0316 operating-points-v2 = <&cpu4_opp_table>;
0317 #cooling-cells = <2>;
0318 L2_700: l2-cache {
0319 compatible = "cache";
0320 next-level-cache = <&L3_0>;
0321 };
0322 };
0323
0324 cpu-map {
0325 cluster0 {
0326 core0 {
0327 cpu = <&CPU0>;
0328 };
0329
0330 core1 {
0331 cpu = <&CPU1>;
0332 };
0333
0334 core2 {
0335 cpu = <&CPU2>;
0336 };
0337
0338 core3 {
0339 cpu = <&CPU3>;
0340 };
0341
0342 core4 {
0343 cpu = <&CPU4>;
0344 };
0345
0346 core5 {
0347 cpu = <&CPU5>;
0348 };
0349
0350 core6 {
0351 cpu = <&CPU6>;
0352 };
0353
0354 core7 {
0355 cpu = <&CPU7>;
0356 };
0357 };
0358 };
0359
0360 idle-states {
0361 entry-method = "psci";
0362
0363 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
0364 compatible = "arm,idle-state";
0365 idle-state-name = "little-rail-power-collapse";
0366 arm,psci-suspend-param = <0x40000004>;
0367 entry-latency-us = <355>;
0368 exit-latency-us = <909>;
0369 min-residency-us = <3934>;
0370 local-timer-stop;
0371 };
0372
0373 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
0374 compatible = "arm,idle-state";
0375 idle-state-name = "big-rail-power-collapse";
0376 arm,psci-suspend-param = <0x40000004>;
0377 entry-latency-us = <241>;
0378 exit-latency-us = <1461>;
0379 min-residency-us = <4488>;
0380 local-timer-stop;
0381 };
0382 };
0383
0384 domain-idle-states {
0385 CLUSTER_SLEEP_0: cluster-sleep-0 {
0386 compatible = "domain-idle-state";
0387 idle-state-name = "cluster-power-collapse";
0388 arm,psci-suspend-param = <0x4100c344>;
0389 entry-latency-us = <3263>;
0390 exit-latency-us = <6562>;
0391 min-residency-us = <9987>;
0392 };
0393 };
0394 };
0395
0396 firmware {
0397 scm: scm {
0398 compatible = "qcom,scm-sc8280xp", "qcom,scm";
0399 };
0400 };
0401
0402 aggre1_noc: interconnect-aggre1-noc {
0403 compatible = "qcom,sc8280xp-aggre1-noc";
0404 #interconnect-cells = <2>;
0405 qcom,bcm-voters = <&apps_bcm_voter>;
0406 };
0407
0408 aggre2_noc: interconnect-aggre2-noc {
0409 compatible = "qcom,sc8280xp-aggre2-noc";
0410 #interconnect-cells = <2>;
0411 qcom,bcm-voters = <&apps_bcm_voter>;
0412 };
0413
0414 clk_virt: interconnect-clk-virt {
0415 compatible = "qcom,sc8280xp-clk-virt";
0416 #interconnect-cells = <2>;
0417 qcom,bcm-voters = <&apps_bcm_voter>;
0418 };
0419
0420 config_noc: interconnect-config-noc {
0421 compatible = "qcom,sc8280xp-config-noc";
0422 #interconnect-cells = <2>;
0423 qcom,bcm-voters = <&apps_bcm_voter>;
0424 };
0425
0426 dc_noc: interconnect-dc-noc {
0427 compatible = "qcom,sc8280xp-dc-noc";
0428 #interconnect-cells = <2>;
0429 qcom,bcm-voters = <&apps_bcm_voter>;
0430 };
0431
0432 gem_noc: interconnect-gem-noc {
0433 compatible = "qcom,sc8280xp-gem-noc";
0434 #interconnect-cells = <2>;
0435 qcom,bcm-voters = <&apps_bcm_voter>;
0436 };
0437
0438 lpass_noc: interconnect-lpass-ag-noc {
0439 compatible = "qcom,sc8280xp-lpass-ag-noc";
0440 #interconnect-cells = <2>;
0441 qcom,bcm-voters = <&apps_bcm_voter>;
0442 };
0443
0444 mc_virt: interconnect-mc-virt {
0445 compatible = "qcom,sc8280xp-mc-virt";
0446 #interconnect-cells = <2>;
0447 qcom,bcm-voters = <&apps_bcm_voter>;
0448 };
0449
0450 mmss_noc: interconnect-mmss-noc {
0451 compatible = "qcom,sc8280xp-mmss-noc";
0452 #interconnect-cells = <2>;
0453 qcom,bcm-voters = <&apps_bcm_voter>;
0454 };
0455
0456 nspa_noc: interconnect-nspa-noc {
0457 compatible = "qcom,sc8280xp-nspa-noc";
0458 #interconnect-cells = <2>;
0459 qcom,bcm-voters = <&apps_bcm_voter>;
0460 };
0461
0462 nspb_noc: interconnect-nspb-noc {
0463 compatible = "qcom,sc8280xp-nspb-noc";
0464 #interconnect-cells = <2>;
0465 qcom,bcm-voters = <&apps_bcm_voter>;
0466 };
0467
0468 system_noc: interconnect-system-noc {
0469 compatible = "qcom,sc8280xp-system-noc";
0470 #interconnect-cells = <2>;
0471 qcom,bcm-voters = <&apps_bcm_voter>;
0472 };
0473
0474 memory@80000000 {
0475 device_type = "memory";
0476 /* We expect the bootloader to fill in the size */
0477 reg = <0x0 0x80000000 0x0 0x0>;
0478 };
0479
0480 pmu {
0481 compatible = "arm,armv8-pmuv3";
0482 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0483 };
0484
0485 psci {
0486 compatible = "arm,psci-1.0";
0487 method = "smc";
0488
0489 CPU_PD0: cpu0 {
0490 #power-domain-cells = <0>;
0491 power-domains = <&CLUSTER_PD>;
0492 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0493 };
0494
0495 CPU_PD1: cpu1 {
0496 #power-domain-cells = <0>;
0497 power-domains = <&CLUSTER_PD>;
0498 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0499 };
0500
0501 CPU_PD2: cpu2 {
0502 #power-domain-cells = <0>;
0503 power-domains = <&CLUSTER_PD>;
0504 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0505 };
0506
0507 CPU_PD3: cpu3 {
0508 #power-domain-cells = <0>;
0509 power-domains = <&CLUSTER_PD>;
0510 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
0511 };
0512
0513 CPU_PD4: cpu4 {
0514 #power-domain-cells = <0>;
0515 power-domains = <&CLUSTER_PD>;
0516 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0517 };
0518
0519 CPU_PD5: cpu5 {
0520 #power-domain-cells = <0>;
0521 power-domains = <&CLUSTER_PD>;
0522 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0523 };
0524
0525 CPU_PD6: cpu6 {
0526 #power-domain-cells = <0>;
0527 power-domains = <&CLUSTER_PD>;
0528 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0529 };
0530
0531 CPU_PD7: cpu7 {
0532 #power-domain-cells = <0>;
0533 power-domains = <&CLUSTER_PD>;
0534 domain-idle-states = <&BIG_CPU_SLEEP_0>;
0535 };
0536
0537 CLUSTER_PD: cpu-cluster0 {
0538 #power-domain-cells = <0>;
0539 domain-idle-states = <&CLUSTER_SLEEP_0>;
0540 };
0541 };
0542
0543 qup_opp_table_100mhz: qup-100mhz-opp-table {
0544 compatible = "operating-points-v2";
0545
0546 opp-75000000 {
0547 opp-hz = /bits/ 64 <75000000>;
0548 required-opps = <&rpmhpd_opp_low_svs>;
0549 };
0550
0551 opp-100000000 {
0552 opp-hz = /bits/ 64 <100000000>;
0553 required-opps = <&rpmhpd_opp_svs>;
0554 };
0555 };
0556
0557 reserved-memory {
0558 #address-cells = <2>;
0559 #size-cells = <2>;
0560 ranges;
0561
0562 reserved-region@80000000 {
0563 reg = <0 0x80000000 0 0x860000>;
0564 no-map;
0565 };
0566
0567 cmd_db: cmd-db-region@80860000 {
0568 compatible = "qcom,cmd-db";
0569 reg = <0 0x80860000 0 0x20000>;
0570 no-map;
0571 };
0572
0573 reserved-region@80880000 {
0574 reg = <0 0x80880000 0 0x80000>;
0575 no-map;
0576 };
0577
0578 smem_mem: smem-region@80900000 {
0579 compatible = "qcom,smem";
0580 reg = <0 0x80900000 0 0x200000>;
0581 no-map;
0582 hwlocks = <&tcsr_mutex 3>;
0583 };
0584
0585 reserved-region@80b00000 {
0586 reg = <0 0x80b00000 0 0x100000>;
0587 no-map;
0588 };
0589
0590 reserved-region@83b00000 {
0591 reg = <0 0x83b00000 0 0x1700000>;
0592 no-map;
0593 };
0594
0595 reserved-region@85b00000 {
0596 reg = <0 0x85b00000 0 0xc00000>;
0597 no-map;
0598 };
0599
0600 pil_adsp_mem: adsp-region@86c00000 {
0601 reg = <0 0x86c00000 0 0x2000000>;
0602 no-map;
0603 };
0604
0605 pil_nsp0_mem: cdsp0-region@8a100000 {
0606 reg = <0 0x8a100000 0 0x1e00000>;
0607 no-map;
0608 };
0609
0610 pil_nsp1_mem: cdsp1-region@8c600000 {
0611 reg = <0 0x8c600000 0 0x1e00000>;
0612 no-map;
0613 };
0614
0615 reserved-region@aeb00000 {
0616 reg = <0 0xaeb00000 0 0x16600000>;
0617 no-map;
0618 };
0619 };
0620
0621 smp2p-adsp {
0622 compatible = "qcom,smp2p";
0623 qcom,smem = <443>, <429>;
0624 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
0625 IPCC_MPROC_SIGNAL_SMP2P
0626 IRQ_TYPE_EDGE_RISING>;
0627 mboxes = <&ipcc IPCC_CLIENT_LPASS
0628 IPCC_MPROC_SIGNAL_SMP2P>;
0629
0630 qcom,local-pid = <0>;
0631 qcom,remote-pid = <2>;
0632
0633 smp2p_adsp_out: master-kernel {
0634 qcom,entry-name = "master-kernel";
0635 #qcom,smem-state-cells = <1>;
0636 };
0637
0638 smp2p_adsp_in: slave-kernel {
0639 qcom,entry-name = "slave-kernel";
0640 interrupt-controller;
0641 #interrupt-cells = <2>;
0642 };
0643 };
0644
0645 smp2p-nsp0 {
0646 compatible = "qcom,smp2p";
0647 qcom,smem = <94>, <432>;
0648 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
0649 IPCC_MPROC_SIGNAL_SMP2P
0650 IRQ_TYPE_EDGE_RISING>;
0651 mboxes = <&ipcc IPCC_CLIENT_CDSP
0652 IPCC_MPROC_SIGNAL_SMP2P>;
0653
0654 qcom,local-pid = <0>;
0655 qcom,remote-pid = <5>;
0656
0657 smp2p_nsp0_out: master-kernel {
0658 qcom,entry-name = "master-kernel";
0659 #qcom,smem-state-cells = <1>;
0660 };
0661
0662 smp2p_nsp0_in: slave-kernel {
0663 qcom,entry-name = "slave-kernel";
0664 interrupt-controller;
0665 #interrupt-cells = <2>;
0666 };
0667 };
0668
0669 smp2p-nsp1 {
0670 compatible = "qcom,smp2p";
0671 qcom,smem = <617>, <616>;
0672 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
0673 IPCC_MPROC_SIGNAL_SMP2P
0674 IRQ_TYPE_EDGE_RISING>;
0675 mboxes = <&ipcc IPCC_CLIENT_NSP1
0676 IPCC_MPROC_SIGNAL_SMP2P>;
0677
0678 qcom,local-pid = <0>;
0679 qcom,remote-pid = <12>;
0680
0681 smp2p_nsp1_out: master-kernel {
0682 qcom,entry-name = "master-kernel";
0683 #qcom,smem-state-cells = <1>;
0684 };
0685
0686 smp2p_nsp1_in: slave-kernel {
0687 qcom,entry-name = "slave-kernel";
0688 interrupt-controller;
0689 #interrupt-cells = <2>;
0690 };
0691 };
0692
0693 soc: soc@0 {
0694 compatible = "simple-bus";
0695 #address-cells = <2>;
0696 #size-cells = <2>;
0697 ranges = <0 0 0 0 0x10 0>;
0698 dma-ranges = <0 0 0 0 0x10 0>;
0699
0700 gcc: clock-controller@100000 {
0701 compatible = "qcom,gcc-sc8280xp";
0702 reg = <0x0 0x00100000 0x0 0x1f0000>;
0703 #clock-cells = <1>;
0704 #reset-cells = <1>;
0705 #power-domain-cells = <1>;
0706 clocks = <&rpmhcc RPMH_CXO_CLK>,
0707 <&sleep_clk>,
0708 <0>,
0709 <0>,
0710 <0>,
0711 <0>,
0712 <0>,
0713 <0>,
0714 <&usb_0_ssphy>,
0715 <0>,
0716 <0>,
0717 <0>,
0718 <0>,
0719 <0>,
0720 <0>,
0721 <0>,
0722 <&usb_1_ssphy>,
0723 <0>,
0724 <0>,
0725 <0>,
0726 <0>,
0727 <0>,
0728 <0>,
0729 <0>,
0730 <0>,
0731 <0>,
0732 <0>,
0733 <0>,
0734 <0>,
0735 <0>,
0736 <0>,
0737 <0>,
0738 <0>;
0739 power-domains = <&rpmhpd SC8280XP_CX>;
0740 };
0741
0742 ipcc: mailbox@408000 {
0743 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
0744 reg = <0 0x00408000 0 0x1000>;
0745 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
0746 interrupt-controller;
0747 #interrupt-cells = <3>;
0748 #mbox-cells = <2>;
0749 };
0750
0751 qup2: geniqup@8c0000 {
0752 compatible = "qcom,geni-se-qup";
0753 reg = <0 0x008c0000 0 0x2000>;
0754 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
0755 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
0756 clock-names = "m-ahb", "s-ahb";
0757 iommus = <&apps_smmu 0xa3 0>;
0758
0759 #address-cells = <2>;
0760 #size-cells = <2>;
0761 ranges;
0762
0763 status = "disabled";
0764
0765 qup2_uart17: serial@884000 {
0766 compatible = "qcom,geni-uart";
0767 reg = <0 0x00884000 0 0x4000>;
0768 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
0769 clock-names = "se";
0770 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
0771 operating-points-v2 = <&qup_opp_table_100mhz>;
0772 power-domains = <&rpmhpd SC8280XP_CX>;
0773 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0774 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
0775 interconnect-names = "qup-core", "qup-config";
0776 status = "disabled";
0777 };
0778
0779 qup2_i2c5: i2c@894000 {
0780 compatible = "qcom,geni-i2c";
0781 reg = <0 0x00894000 0 0x4000>;
0782 clock-names = "se";
0783 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
0784 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
0785 #address-cells = <1>;
0786 #size-cells = <0>;
0787 power-domains = <&rpmhpd SC8280XP_CX>;
0788 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
0789 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
0790 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
0791 interconnect-names = "qup-core", "qup-config", "qup-memory";
0792 status = "disabled";
0793 };
0794 };
0795
0796 qup0: geniqup@9c0000 {
0797 compatible = "qcom,geni-se-qup";
0798 reg = <0 0x009c0000 0 0x6000>;
0799 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
0800 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
0801 clock-names = "m-ahb", "s-ahb";
0802 iommus = <&apps_smmu 0x563 0>;
0803
0804 #address-cells = <2>;
0805 #size-cells = <2>;
0806 ranges;
0807
0808 status = "disabled";
0809
0810 qup0_i2c4: i2c@990000 {
0811 compatible = "qcom,geni-i2c";
0812 reg = <0 0x00990000 0 0x4000>;
0813 clock-names = "se";
0814 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
0815 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
0816 #address-cells = <1>;
0817 #size-cells = <0>;
0818 power-domains = <&rpmhpd SC8280XP_CX>;
0819 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
0820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
0821 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
0822 interconnect-names = "qup-core", "qup-config", "qup-memory";
0823 status = "disabled";
0824 };
0825 };
0826
0827 qup1: geniqup@ac0000 {
0828 compatible = "qcom,geni-se-qup";
0829 reg = <0 0x00ac0000 0 0x6000>;
0830 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
0831 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
0832 clock-names = "m-ahb", "s-ahb";
0833 iommus = <&apps_smmu 0x83 0>;
0834
0835 #address-cells = <2>;
0836 #size-cells = <2>;
0837 ranges;
0838
0839 status = "disabled";
0840 };
0841
0842 ufs_mem_hc: ufs@1d84000 {
0843 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
0844 "jedec,ufs-2.0";
0845 reg = <0 0x01d84000 0 0x3000>;
0846 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
0847 phys = <&ufs_mem_phy_lanes>;
0848 phy-names = "ufsphy";
0849 lanes-per-direction = <2>;
0850 #reset-cells = <1>;
0851 resets = <&gcc GCC_UFS_PHY_BCR>;
0852 reset-names = "rst";
0853
0854 power-domains = <&gcc UFS_PHY_GDSC>;
0855 required-opps = <&rpmhpd_opp_nom>;
0856
0857 iommus = <&apps_smmu 0xe0 0x0>;
0858
0859 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
0860 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
0861 <&gcc GCC_UFS_PHY_AHB_CLK>,
0862 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
0863 <&rpmhcc RPMH_CXO_CLK>,
0864 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
0865 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
0866 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
0867 clock-names = "core_clk",
0868 "bus_aggr_clk",
0869 "iface_clk",
0870 "core_clk_unipro",
0871 "ref_clk",
0872 "tx_lane0_sync_clk",
0873 "rx_lane0_sync_clk",
0874 "rx_lane1_sync_clk";
0875 freq-table-hz = <75000000 300000000>,
0876 <0 0>,
0877 <0 0>,
0878 <75000000 300000000>,
0879 <0 0>,
0880 <0 0>,
0881 <0 0>,
0882 <0 0>;
0883 status = "disabled";
0884 };
0885
0886 ufs_mem_phy: phy@1d87000 {
0887 compatible = "qcom,sc8280xp-qmp-ufs-phy";
0888 reg = <0 0x01d87000 0 0xe10>;
0889 #address-cells = <2>;
0890 #size-cells = <2>;
0891 ranges;
0892 clock-names = "ref",
0893 "ref_aux";
0894 clocks = <&rpmhcc RPMH_CXO_CLK>,
0895 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
0896
0897 resets = <&ufs_mem_hc 0>;
0898 reset-names = "ufsphy";
0899 status = "disabled";
0900
0901 ufs_mem_phy_lanes: phy@1d87400 {
0902 reg = <0 0x01d87400 0 0x108>,
0903 <0 0x01d87600 0 0x1e0>,
0904 <0 0x01d87c00 0 0x1dc>,
0905 <0 0x01d87800 0 0x108>,
0906 <0 0x01d87a00 0 0x1e0>;
0907 #phy-cells = <0>;
0908 };
0909 };
0910
0911 ufs_card_hc: ufs@1da4000 {
0912 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
0913 "jedec,ufs-2.0";
0914 reg = <0 0x01da4000 0 0x3000>;
0915 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0916 phys = <&ufs_card_phy_lanes>;
0917 phy-names = "ufsphy";
0918 lanes-per-direction = <2>;
0919 #reset-cells = <1>;
0920 resets = <&gcc GCC_UFS_CARD_BCR>;
0921 reset-names = "rst";
0922
0923 power-domains = <&gcc UFS_CARD_GDSC>;
0924
0925 iommus = <&apps_smmu 0x4a0 0x0>;
0926
0927 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
0928 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
0929 <&gcc GCC_UFS_CARD_AHB_CLK>,
0930 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
0931 <&rpmhcc RPMH_CXO_CLK>,
0932 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
0933 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
0934 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
0935 clock-names = "core_clk",
0936 "bus_aggr_clk",
0937 "iface_clk",
0938 "core_clk_unipro",
0939 "ref_clk",
0940 "tx_lane0_sync_clk",
0941 "rx_lane0_sync_clk",
0942 "rx_lane1_sync_clk";
0943 freq-table-hz = <75000000 300000000>,
0944 <0 0>,
0945 <0 0>,
0946 <75000000 300000000>,
0947 <0 0>,
0948 <0 0>,
0949 <0 0>,
0950 <0 0>;
0951 status = "disabled";
0952 };
0953
0954 ufs_card_phy: phy@1da7000 {
0955 compatible = "qcom,sc8280xp-qmp-ufs-phy";
0956 reg = <0 0x01da7000 0 0xe10>;
0957 #address-cells = <2>;
0958 #size-cells = <2>;
0959 ranges;
0960 clock-names = "ref",
0961 "ref_aux";
0962 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
0963 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
0964
0965 resets = <&ufs_card_hc 0>;
0966 reset-names = "ufsphy";
0967
0968 status = "disabled";
0969
0970 ufs_card_phy_lanes: phy@1da7400 {
0971 reg = <0 0x01da7400 0 0x108>,
0972 <0 0x01da7600 0 0x1e0>,
0973 <0 0x01da7c00 0 0x1dc>,
0974 <0 0x01da7800 0 0x108>,
0975 <0 0x01da7a00 0 0x1e0>;
0976 #phy-cells = <0>;
0977 };
0978 };
0979
0980 tcsr_mutex: hwlock@1f40000 {
0981 compatible = "qcom,tcsr-mutex";
0982 reg = <0x0 0x01f40000 0x0 0x20000>;
0983 #hwlock-cells = <1>;
0984 };
0985
0986 usb_0_hsphy: phy@88e5000 {
0987 compatible = "qcom,sc8280xp-usb-hs-phy",
0988 "qcom,usb-snps-hs-5nm-phy";
0989 reg = <0 0x088e5000 0 0x400>;
0990 clocks = <&rpmhcc RPMH_CXO_CLK>;
0991 clock-names = "ref";
0992 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
0993
0994 #phy-cells = <0>;
0995
0996 status = "disabled";
0997 };
0998
0999 usb_2_hsphy0: phy@88e7000 {
1000 compatible = "qcom,sc8280xp-usb-hs-phy",
1001 "qcom,usb-snps-hs-5nm-phy";
1002 reg = <0 0x088e7000 0 0x400>;
1003 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1004 clock-names = "ref";
1005 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1006
1007 #phy-cells = <0>;
1008
1009 status = "disabled";
1010 };
1011
1012 usb_2_hsphy1: phy@88e8000 {
1013 compatible = "qcom,sc8280xp-usb-hs-phy",
1014 "qcom,usb-snps-hs-5nm-phy";
1015 reg = <0 0x088e8000 0 0x400>;
1016 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1017 clock-names = "ref";
1018 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1019
1020 #phy-cells = <0>;
1021
1022 status = "disabled";
1023 };
1024
1025 usb_2_hsphy2: phy@88e9000 {
1026 compatible = "qcom,sc8280xp-usb-hs-phy",
1027 "qcom,usb-snps-hs-5nm-phy";
1028 reg = <0 0x088e9000 0 0x400>;
1029 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1030 clock-names = "ref";
1031 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1032
1033 #phy-cells = <0>;
1034
1035 status = "disabled";
1036 };
1037
1038 usb_2_hsphy3: phy@88ea000 {
1039 compatible = "qcom,sc8280xp-usb-hs-phy",
1040 "qcom,usb-snps-hs-5nm-phy";
1041 reg = <0 0x088ea000 0 0x400>;
1042 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1043 clock-names = "ref";
1044 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1045
1046 #phy-cells = <0>;
1047
1048 status = "disabled";
1049 };
1050
1051 usb_2_qmpphy0: phy-wrapper@88ef000 {
1052 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1053 reg = <0 0x088ef000 0 0x1c8>;
1054 #address-cells = <2>;
1055 #size-cells = <2>;
1056 ranges;
1057
1058 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1059 <&rpmhcc RPMH_CXO_CLK>,
1060 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1061 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1062 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1063
1064 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1065 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1066 reset-names = "phy", "common";
1067
1068 power-domains = <&gcc USB30_MP_GDSC>;
1069
1070 status = "disabled";
1071
1072 usb_2_ssphy0: phy@88efe00 {
1073 reg = <0 0x088efe00 0 0x160>,
1074 <0 0x088f0000 0 0x1ec>,
1075 <0 0x088ef200 0 0x1f0>;
1076 #phy-cells = <0>;
1077 #clock-cells = <0>;
1078 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1079 clock-names = "pipe0";
1080 clock-output-names = "usb2_phy0_pipe_clk";
1081 };
1082 };
1083
1084 usb_2_qmpphy1: phy-wrapper@88f1000 {
1085 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1086 reg = <0 0x088f1000 0 0x1c8>;
1087 #address-cells = <2>;
1088 #size-cells = <2>;
1089 ranges;
1090
1091 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1092 <&rpmhcc RPMH_CXO_CLK>,
1093 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1094 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1095 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1096
1097 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1098 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1099 reset-names = "phy", "common";
1100
1101 power-domains = <&gcc USB30_MP_GDSC>;
1102
1103 status = "disabled";
1104
1105 usb_2_ssphy1: phy@88f1e00 {
1106 reg = <0 0x088f1e00 0 0x160>,
1107 <0 0x088f2000 0 0x1ec>,
1108 <0 0x088f1200 0 0x1f0>;
1109 #phy-cells = <0>;
1110 #clock-cells = <0>;
1111 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1112 clock-names = "pipe0";
1113 clock-output-names = "usb2_phy1_pipe_clk";
1114 };
1115 };
1116
1117 remoteproc_adsp: remoteproc@3000000 {
1118 compatible = "qcom,sc8280xp-adsp-pas";
1119 reg = <0 0x03000000 0 0x100>;
1120
1121 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1122 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1123 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1124 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1125 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1126 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1127 interrupt-names = "wdog", "fatal", "ready",
1128 "handover", "stop-ack", "shutdown-ack";
1129
1130 clocks = <&rpmhcc RPMH_CXO_CLK>;
1131 clock-names = "xo";
1132
1133 power-domains = <&rpmhpd SC8280XP_LCX>,
1134 <&rpmhpd SC8280XP_LMX>;
1135 power-domain-names = "lcx", "lmx";
1136
1137 memory-region = <&pil_adsp_mem>;
1138
1139 qcom,qmp = <&aoss_qmp>;
1140
1141 qcom,smem-states = <&smp2p_adsp_out 0>;
1142 qcom,smem-state-names = "stop";
1143
1144 status = "disabled";
1145
1146 remoteproc_adsp_glink: glink-edge {
1147 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1148 IPCC_MPROC_SIGNAL_GLINK_QMP
1149 IRQ_TYPE_EDGE_RISING>;
1150 mboxes = <&ipcc IPCC_CLIENT_LPASS
1151 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1152
1153 label = "lpass";
1154 qcom,remote-pid = <2>;
1155 };
1156 };
1157
1158 usb_0_qmpphy: phy-wrapper@88ec000 {
1159 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1160 reg = <0 0x088ec000 0 0x1e4>,
1161 <0 0x088eb000 0 0x40>,
1162 <0 0x088ed000 0 0x1c8>;
1163 #address-cells = <2>;
1164 #size-cells = <2>;
1165 ranges;
1166
1167 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1168 <&rpmhcc RPMH_CXO_CLK>,
1169 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1170 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1171 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1172
1173 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1174 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1175 reset-names = "phy", "common";
1176
1177 power-domains = <&gcc USB30_PRIM_GDSC>;
1178
1179 status = "disabled";
1180
1181 usb_0_ssphy: usb3-phy@88eb400 {
1182 reg = <0 0x088eb400 0 0x100>,
1183 <0 0x088eb600 0 0x3ec>,
1184 <0 0x088ec400 0 0x1f0>,
1185 <0 0x088eba00 0 0x100>,
1186 <0 0x088ebc00 0 0x3ec>,
1187 <0 0x088ec700 0 0x64>;
1188 #phy-cells = <0>;
1189 #clock-cells = <0>;
1190 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1191 clock-names = "pipe0";
1192 clock-output-names = "usb0_phy_pipe_clk_src";
1193 };
1194
1195 usb_0_dpphy: dp-phy@88ed200 {
1196 reg = <0 0x088ed200 0 0x200>,
1197 <0 0x088ed400 0 0x200>,
1198 <0 0x088eda00 0 0x200>,
1199 <0 0x088ea600 0 0x200>,
1200 <0 0x088ea800 0 0x200>;
1201 #clock-cells = <1>;
1202 #phy-cells = <0>;
1203 };
1204 };
1205
1206 usb_1_hsphy: phy@8902000 {
1207 compatible = "qcom,sc8280xp-usb-hs-phy",
1208 "qcom,usb-snps-hs-5nm-phy";
1209 reg = <0 0x08902000 0 0x400>;
1210 #phy-cells = <0>;
1211
1212 clocks = <&rpmhcc RPMH_CXO_CLK>;
1213 clock-names = "ref";
1214
1215 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1216
1217 status = "disabled";
1218 };
1219
1220 usb_1_qmpphy: phy-wrapper@8904000 {
1221 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1222 reg = <0 0x08904000 0 0x1e4>,
1223 <0 0x08903000 0 0x40>,
1224 <0 0x08905000 0 0x1c8>;
1225 #address-cells = <2>;
1226 #size-cells = <2>;
1227 ranges;
1228
1229 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1230 <&rpmhcc RPMH_CXO_CLK>,
1231 <&gcc GCC_USB4_CLKREF_CLK>,
1232 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1233 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1234
1235 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1236 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1237 reset-names = "phy", "common";
1238
1239 power-domains = <&gcc USB30_SEC_GDSC>;
1240
1241 status = "disabled";
1242
1243 usb_1_ssphy: usb3-phy@8903400 {
1244 reg = <0 0x08903400 0 0x100>,
1245 <0 0x08903c00 0 0x3ec>,
1246 <0 0x08904400 0 0x1f0>,
1247 <0 0x08903a00 0 0x100>,
1248 <0 0x08903c00 0 0x3ec>,
1249 <0 0x08904200 0 0x18>;
1250 #phy-cells = <0>;
1251 #clock-cells = <0>;
1252 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1253 clock-names = "pipe0";
1254 clock-output-names = "usb1_phy_pipe_clk_src";
1255 };
1256
1257 usb_1_dpphy: dp-phy@8904200 {
1258 reg = <0 0x08904200 0 0x200>,
1259 <0 0x08904400 0 0x200>,
1260 <0 0x08904a00 0 0x200>,
1261 <0 0x08904600 0 0x200>,
1262 <0 0x08904800 0 0x200>;
1263 #clock-cells = <1>;
1264 #phy-cells = <0>;
1265 };
1266 };
1267
1268 system-cache-controller@9200000 {
1269 compatible = "qcom,sc8280xp-llcc";
1270 reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1271 reg-names = "llcc_base", "llcc_broadcast_base";
1272 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1273 };
1274
1275 usb_0: usb@a6f8800 {
1276 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1277 reg = <0 0x0a6f8800 0 0x400>;
1278 #address-cells = <2>;
1279 #size-cells = <2>;
1280 ranges;
1281
1282 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1283 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1284 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1285 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1286 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1287 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1288 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1289 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1290 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1291 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1292 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1293
1294 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1295 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1296 assigned-clock-rates = <19200000>, <200000000>;
1297
1298 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1299 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1300 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1301 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1302 interrupt-names = "pwr_event",
1303 "dp_hs_phy_irq",
1304 "dm_hs_phy_irq",
1305 "ss_phy_irq";
1306
1307 power-domains = <&gcc USB30_PRIM_GDSC>;
1308
1309 resets = <&gcc GCC_USB30_PRIM_BCR>;
1310
1311 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1313 interconnect-names = "usb-ddr", "apps-usb";
1314
1315 status = "disabled";
1316
1317 usb_0_dwc3: usb@a600000 {
1318 compatible = "snps,dwc3";
1319 reg = <0 0x0a600000 0 0xcd00>;
1320 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1321 iommus = <&apps_smmu 0x820 0x0>;
1322 phys = <&usb_0_hsphy>, <&usb_0_ssphy>;
1323 phy-names = "usb2-phy", "usb3-phy";
1324 };
1325 };
1326
1327 usb_1: usb@a8f8800 {
1328 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1329 reg = <0 0x0a8f8800 0 0x400>;
1330 #address-cells = <2>;
1331 #size-cells = <2>;
1332 ranges;
1333
1334 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1335 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1336 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1337 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1338 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1339 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1340 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1341 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1342 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1343 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1344 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1345
1346 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1347 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1348 assigned-clock-rates = <19200000>, <200000000>;
1349
1350 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1351 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1352 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1353 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1354 interrupt-names = "pwr_event",
1355 "dp_hs_phy_irq",
1356 "dm_hs_phy_irq",
1357 "ss_phy_irq";
1358
1359 power-domains = <&gcc USB30_SEC_GDSC>;
1360
1361 resets = <&gcc GCC_USB30_SEC_BCR>;
1362
1363 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1365 interconnect-names = "usb-ddr", "apps-usb";
1366
1367 status = "disabled";
1368
1369 usb_1_dwc3: usb@a800000 {
1370 compatible = "snps,dwc3";
1371 reg = <0 0x0a800000 0 0xcd00>;
1372 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1373 iommus = <&apps_smmu 0x860 0x0>;
1374 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1375 phy-names = "usb2-phy", "usb3-phy";
1376 };
1377 };
1378
1379 pdc: interrupt-controller@b220000 {
1380 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1381 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1382 qcom,pdc-ranges = <0 480 40>,
1383 <40 140 14>,
1384 <54 263 1>,
1385 <55 306 4>,
1386 <59 312 3>,
1387 <62 374 2>,
1388 <64 434 2>,
1389 <66 438 3>,
1390 <69 86 1>,
1391 <70 520 54>,
1392 <124 609 28>,
1393 <159 638 1>,
1394 <160 720 8>,
1395 <168 801 1>,
1396 <169 728 30>,
1397 <199 416 2>,
1398 <201 449 1>,
1399 <202 89 1>,
1400 <203 451 1>,
1401 <204 462 1>,
1402 <205 264 1>,
1403 <206 579 1>,
1404 <207 653 1>,
1405 <208 656 1>,
1406 <209 659 1>,
1407 <210 122 1>,
1408 <211 699 1>,
1409 <212 705 1>,
1410 <213 450 1>,
1411 <214 643 1>,
1412 <216 646 5>,
1413 <221 390 5>,
1414 <226 700 3>,
1415 <229 240 3>,
1416 <232 269 1>,
1417 <233 377 1>,
1418 <234 372 1>,
1419 <235 138 1>,
1420 <236 857 1>,
1421 <237 860 1>,
1422 <238 137 1>,
1423 <239 668 1>,
1424 <240 366 1>,
1425 <241 949 1>,
1426 <242 815 5>,
1427 <247 769 1>,
1428 <248 768 1>,
1429 <249 663 1>,
1430 <250 799 2>,
1431 <252 798 1>,
1432 <253 765 1>,
1433 <254 763 1>,
1434 <255 454 1>,
1435 <258 139 1>,
1436 <259 786 2>,
1437 <261 370 2>,
1438 <263 158 2>;
1439 #interrupt-cells = <2>;
1440 interrupt-parent = <&intc>;
1441 interrupt-controller;
1442 };
1443
1444 tsens0: thermal-sensor@c263000 {
1445 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1446 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1447 <0 0x0c222000 0 0x8>; /* SROT */
1448 #qcom,sensors = <14>;
1449 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1450 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1451 interrupt-names = "uplow", "critical";
1452 #thermal-sensor-cells = <1>;
1453 };
1454
1455 tsens1: thermal-sensor@c265000 {
1456 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1457 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1458 <0 0x0c223000 0 0x8>; /* SROT */
1459 #qcom,sensors = <16>;
1460 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1461 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1462 interrupt-names = "uplow", "critical";
1463 #thermal-sensor-cells = <1>;
1464 };
1465
1466 aoss_qmp: power-controller@c300000 {
1467 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
1468 reg = <0 0x0c300000 0 0x400>;
1469 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
1470 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1471
1472 #clock-cells = <0>;
1473 };
1474
1475 spmi_bus: spmi@c440000 {
1476 compatible = "qcom,spmi-pmic-arb";
1477 reg = <0 0x0c440000 0 0x1100>,
1478 <0 0x0c600000 0 0x2000000>,
1479 <0 0x0e600000 0 0x100000>,
1480 <0 0x0e700000 0 0xa0000>,
1481 <0 0x0c40a000 0 0x26000>;
1482 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1483 interrupt-names = "periph_irq";
1484 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1485 qcom,ee = <0>;
1486 qcom,channel = <0>;
1487 #address-cells = <1>;
1488 #size-cells = <1>;
1489 interrupt-controller;
1490 #interrupt-cells = <4>;
1491 };
1492
1493 tlmm: pinctrl@f100000 {
1494 compatible = "qcom,sc8280xp-tlmm";
1495 reg = <0 0x0f100000 0 0x300000>;
1496 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1497 gpio-controller;
1498 #gpio-cells = <2>;
1499 interrupt-controller;
1500 #interrupt-cells = <2>;
1501 gpio-ranges = <&tlmm 0 0 230>;
1502 };
1503
1504 apps_smmu: iommu@15000000 {
1505 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
1506 reg = <0 0x15000000 0 0x100000>;
1507 #iommu-cells = <2>;
1508 #global-interrupts = <2>;
1509 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1550 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1552 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1565 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1568 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1573 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1574 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1575 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1576 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1580 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1592 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
1594 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1595 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1596 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1597 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1599 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1601 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1602 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1604 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1606 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
1607 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
1608 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
1609 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
1610 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
1611 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1612 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
1613 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
1614 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
1616 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
1617 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
1620 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
1621 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
1622 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
1623 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
1625 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
1626 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
1627 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
1628 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
1629 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
1631 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
1634 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
1635 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
1639 };
1640
1641 intc: interrupt-controller@17a00000 {
1642 compatible = "arm,gic-v3";
1643 interrupt-controller;
1644 #interrupt-cells = <3>;
1645 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1646 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1647 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1648 #redistributor-regions = <1>;
1649 redistributor-stride = <0 0x20000>;
1650
1651 #address-cells = <2>;
1652 #size-cells = <2>;
1653 ranges;
1654
1655 gic-its@17a40000 {
1656 compatible = "arm,gic-v3-its";
1657 reg = <0 0x17a40000 0 0x20000>;
1658 msi-controller;
1659 #msi-cells = <1>;
1660 };
1661 };
1662
1663 watchdog@17c10000 {
1664 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
1665 reg = <0 0x17c10000 0 0x1000>;
1666 clocks = <&sleep_clk>;
1667 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1668 };
1669
1670 timer@17c20000 {
1671 compatible = "arm,armv7-timer-mem";
1672 reg = <0x0 0x17c20000 0x0 0x1000>;
1673 #address-cells = <1>;
1674 #size-cells = <1>;
1675 ranges = <0x0 0x0 0x0 0x20000000>;
1676
1677 frame@17c21000 {
1678 frame-number = <0>;
1679 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1680 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1681 reg = <0x17c21000 0x1000>,
1682 <0x17c22000 0x1000>;
1683 };
1684
1685 frame@17c23000 {
1686 frame-number = <1>;
1687 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1688 reg = <0x17c23000 0x1000>;
1689 status = "disabled";
1690 };
1691
1692 frame@17c25000 {
1693 frame-number = <2>;
1694 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1695 reg = <0x17c25000 0x1000>;
1696 status = "disabled";
1697 };
1698
1699 frame@17c27000 {
1700 frame-number = <3>;
1701 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1702 reg = <0x17c26000 0x1000>;
1703 status = "disabled";
1704 };
1705
1706 frame@17c29000 {
1707 frame-number = <4>;
1708 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1709 reg = <0x17c29000 0x1000>;
1710 status = "disabled";
1711 };
1712
1713 frame@17c2b000 {
1714 frame-number = <5>;
1715 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1716 reg = <0x17c2b000 0x1000>;
1717 status = "disabled";
1718 };
1719
1720 frame@17c2d000 {
1721 frame-number = <6>;
1722 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1723 reg = <0x17c2d000 0x1000>;
1724 status = "disabled";
1725 };
1726 };
1727
1728 apps_rsc: rsc@18200000 {
1729 compatible = "qcom,rpmh-rsc";
1730 reg = <0x0 0x18200000 0x0 0x10000>,
1731 <0x0 0x18210000 0x0 0x10000>,
1732 <0x0 0x18220000 0x0 0x10000>;
1733 reg-names = "drv-0", "drv-1", "drv-2";
1734 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1737 qcom,tcs-offset = <0xd00>;
1738 qcom,drv-id = <2>;
1739 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1740 <WAKE_TCS 3>, <CONTROL_TCS 1>;
1741 label = "apps_rsc";
1742
1743 apps_bcm_voter: bcm-voter {
1744 compatible = "qcom,bcm-voter";
1745 };
1746
1747 rpmhcc: clock-controller {
1748 compatible = "qcom,sc8280xp-rpmh-clk";
1749 #clock-cells = <1>;
1750 clock-names = "xo";
1751 clocks = <&xo_board_clk>;
1752 };
1753
1754 rpmhpd: power-controller {
1755 compatible = "qcom,sc8280xp-rpmhpd";
1756 #power-domain-cells = <1>;
1757 operating-points-v2 = <&rpmhpd_opp_table>;
1758
1759 rpmhpd_opp_table: opp-table {
1760 compatible = "operating-points-v2";
1761
1762 rpmhpd_opp_ret: opp1 {
1763 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1764 };
1765
1766 rpmhpd_opp_min_svs: opp2 {
1767 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1768 };
1769
1770 rpmhpd_opp_low_svs: opp3 {
1771 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1772 };
1773
1774 rpmhpd_opp_svs: opp4 {
1775 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1776 };
1777
1778 rpmhpd_opp_svs_l1: opp5 {
1779 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1780 };
1781
1782 rpmhpd_opp_nom: opp6 {
1783 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1784 };
1785
1786 rpmhpd_opp_nom_l1: opp7 {
1787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1788 };
1789
1790 rpmhpd_opp_nom_l2: opp8 {
1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1792 };
1793
1794 rpmhpd_opp_turbo: opp9 {
1795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1796 };
1797
1798 rpmhpd_opp_turbo_l1: opp10 {
1799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1800 };
1801 };
1802 };
1803 };
1804
1805 cpufreq_hw: cpufreq@18591000 {
1806 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
1807 reg = <0 0x18591000 0 0x1000>,
1808 <0 0x18592000 0 0x1000>;
1809 reg-names = "freq-domain0", "freq-domain1";
1810
1811 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1812 clock-names = "xo", "alternate";
1813
1814 #freq-domain-cells = <1>;
1815 };
1816
1817 remoteproc_nsp0: remoteproc@1b300000 {
1818 compatible = "qcom,sc8280xp-nsp0-pas";
1819 reg = <0 0x1b300000 0 0x100>;
1820
1821 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1822 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
1823 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
1824 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
1825 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
1826 interrupt-names = "wdog", "fatal", "ready",
1827 "handover", "stop-ack";
1828
1829 clocks = <&rpmhcc RPMH_CXO_CLK>;
1830 clock-names = "xo";
1831
1832 power-domains = <&rpmhpd SC8280XP_NSP>;
1833 power-domain-names = "nsp";
1834
1835 memory-region = <&pil_nsp0_mem>;
1836
1837 qcom,smem-states = <&smp2p_nsp0_out 0>;
1838 qcom,smem-state-names = "stop";
1839
1840 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
1841
1842 status = "disabled";
1843
1844 glink-edge {
1845 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1846 IPCC_MPROC_SIGNAL_GLINK_QMP
1847 IRQ_TYPE_EDGE_RISING>;
1848 mboxes = <&ipcc IPCC_CLIENT_CDSP
1849 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1850
1851 label = "nsp0";
1852 qcom,remote-pid = <5>;
1853
1854 fastrpc {
1855 compatible = "qcom,fastrpc";
1856 qcom,glink-channels = "fastrpcglink-apps-dsp";
1857 label = "cdsp";
1858 #address-cells = <1>;
1859 #size-cells = <0>;
1860
1861 compute-cb@1 {
1862 compatible = "qcom,fastrpc-compute-cb";
1863 reg = <1>;
1864 iommus = <&apps_smmu 0x3181 0x0420>;
1865 };
1866
1867 compute-cb@2 {
1868 compatible = "qcom,fastrpc-compute-cb";
1869 reg = <2>;
1870 iommus = <&apps_smmu 0x3182 0x0420>;
1871 };
1872
1873 compute-cb@3 {
1874 compatible = "qcom,fastrpc-compute-cb";
1875 reg = <3>;
1876 iommus = <&apps_smmu 0x3183 0x0420>;
1877 };
1878
1879 compute-cb@4 {
1880 compatible = "qcom,fastrpc-compute-cb";
1881 reg = <4>;
1882 iommus = <&apps_smmu 0x3184 0x0420>;
1883 };
1884
1885 compute-cb@5 {
1886 compatible = "qcom,fastrpc-compute-cb";
1887 reg = <5>;
1888 iommus = <&apps_smmu 0x3185 0x0420>;
1889 };
1890
1891 compute-cb@6 {
1892 compatible = "qcom,fastrpc-compute-cb";
1893 reg = <6>;
1894 iommus = <&apps_smmu 0x3186 0x0420>;
1895 };
1896
1897 compute-cb@7 {
1898 compatible = "qcom,fastrpc-compute-cb";
1899 reg = <7>;
1900 iommus = <&apps_smmu 0x3187 0x0420>;
1901 };
1902
1903 compute-cb@8 {
1904 compatible = "qcom,fastrpc-compute-cb";
1905 reg = <8>;
1906 iommus = <&apps_smmu 0x3188 0x0420>;
1907 };
1908
1909 compute-cb@9 {
1910 compatible = "qcom,fastrpc-compute-cb";
1911 reg = <9>;
1912 iommus = <&apps_smmu 0x318b 0x0420>;
1913 };
1914
1915 compute-cb@10 {
1916 compatible = "qcom,fastrpc-compute-cb";
1917 reg = <10>;
1918 iommus = <&apps_smmu 0x318b 0x0420>;
1919 };
1920
1921 compute-cb@11 {
1922 compatible = "qcom,fastrpc-compute-cb";
1923 reg = <11>;
1924 iommus = <&apps_smmu 0x318c 0x0420>;
1925 };
1926
1927 compute-cb@12 {
1928 compatible = "qcom,fastrpc-compute-cb";
1929 reg = <12>;
1930 iommus = <&apps_smmu 0x318d 0x0420>;
1931 };
1932
1933 compute-cb@13 {
1934 compatible = "qcom,fastrpc-compute-cb";
1935 reg = <13>;
1936 iommus = <&apps_smmu 0x318e 0x0420>;
1937 };
1938
1939 compute-cb@14 {
1940 compatible = "qcom,fastrpc-compute-cb";
1941 reg = <14>;
1942 iommus = <&apps_smmu 0x318f 0x0420>;
1943 };
1944 };
1945 };
1946 };
1947
1948 remoteproc_nsp1: remoteproc@21300000 {
1949 compatible = "qcom,sc8280xp-nsp1-pas";
1950 reg = <0 0x21300000 0 0x100>;
1951
1952 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
1953 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
1954 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
1955 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
1956 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
1957 interrupt-names = "wdog", "fatal", "ready",
1958 "handover", "stop-ack";
1959
1960 clocks = <&rpmhcc RPMH_CXO_CLK>;
1961 clock-names = "xo";
1962
1963 power-domains = <&rpmhpd SC8280XP_NSP>;
1964 power-domain-names = "nsp";
1965
1966 memory-region = <&pil_nsp1_mem>;
1967
1968 qcom,smem-states = <&smp2p_nsp1_out 0>;
1969 qcom,smem-state-names = "stop";
1970
1971 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
1972
1973 status = "disabled";
1974
1975 glink-edge {
1976 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
1977 IPCC_MPROC_SIGNAL_GLINK_QMP
1978 IRQ_TYPE_EDGE_RISING>;
1979 mboxes = <&ipcc IPCC_CLIENT_NSP1
1980 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1981
1982 label = "nsp1";
1983 qcom,remote-pid = <12>;
1984 };
1985 };
1986 };
1987
1988 thermal-zones {
1989 cpu0-thermal {
1990 polling-delay-passive = <250>;
1991 polling-delay = <1000>;
1992
1993 thermal-sensors = <&tsens0 1>;
1994
1995 trips {
1996 cpu-crit {
1997 temperature = <110000>;
1998 hysteresis = <1000>;
1999 type = "critical";
2000 };
2001 };
2002 };
2003
2004 cpu1-thermal {
2005 polling-delay-passive = <250>;
2006 polling-delay = <1000>;
2007
2008 thermal-sensors = <&tsens0 2>;
2009
2010 trips {
2011 cpu-crit {
2012 temperature = <110000>;
2013 hysteresis = <1000>;
2014 type = "critical";
2015 };
2016 };
2017 };
2018
2019 cpu2-thermal {
2020 polling-delay-passive = <250>;
2021 polling-delay = <1000>;
2022
2023 thermal-sensors = <&tsens0 3>;
2024
2025 trips {
2026 cpu-crit {
2027 temperature = <110000>;
2028 hysteresis = <1000>;
2029 type = "critical";
2030 };
2031 };
2032 };
2033
2034 cpu3-thermal {
2035 polling-delay-passive = <250>;
2036 polling-delay = <1000>;
2037
2038 thermal-sensors = <&tsens0 4>;
2039
2040 trips {
2041 cpu-crit {
2042 temperature = <110000>;
2043 hysteresis = <1000>;
2044 type = "critical";
2045 };
2046 };
2047 };
2048
2049 cpu4-thermal {
2050 polling-delay-passive = <250>;
2051 polling-delay = <1000>;
2052
2053 thermal-sensors = <&tsens0 5>;
2054
2055 trips {
2056 cpu-crit {
2057 temperature = <110000>;
2058 hysteresis = <1000>;
2059 type = "critical";
2060 };
2061 };
2062 };
2063
2064 cpu5-thermal {
2065 polling-delay-passive = <250>;
2066 polling-delay = <1000>;
2067
2068 thermal-sensors = <&tsens0 6>;
2069
2070 trips {
2071 cpu-crit {
2072 temperature = <110000>;
2073 hysteresis = <1000>;
2074 type = "critical";
2075 };
2076 };
2077 };
2078
2079 cpu6-thermal {
2080 polling-delay-passive = <250>;
2081 polling-delay = <1000>;
2082
2083 thermal-sensors = <&tsens0 7>;
2084
2085 trips {
2086 cpu-crit {
2087 temperature = <110000>;
2088 hysteresis = <1000>;
2089 type = "critical";
2090 };
2091 };
2092 };
2093
2094 cpu7-thermal {
2095 polling-delay-passive = <250>;
2096 polling-delay = <1000>;
2097
2098 thermal-sensors = <&tsens0 8>;
2099
2100 trips {
2101 cpu-crit {
2102 temperature = <110000>;
2103 hysteresis = <1000>;
2104 type = "critical";
2105 };
2106 };
2107 };
2108
2109 cluster0-thermal {
2110 polling-delay-passive = <250>;
2111 polling-delay = <1000>;
2112
2113 thermal-sensors = <&tsens0 9>;
2114
2115 trips {
2116 cpu-crit {
2117 temperature = <110000>;
2118 hysteresis = <1000>;
2119 type = "critical";
2120 };
2121 };
2122 };
2123
2124 mem-thermal {
2125 polling-delay-passive = <250>;
2126 polling-delay = <1000>;
2127
2128 thermal-sensors = <&tsens1 15>;
2129
2130 trips {
2131 trip-point0 {
2132 temperature = <90000>;
2133 hysteresis = <2000>;
2134 type = "hot";
2135 };
2136 };
2137 };
2138 };
2139
2140 timer {
2141 compatible = "arm,armv8-timer";
2142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2146 };
2147 };
