0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
0004 */
0005
0006 /dts-v1/;
0007 #include "sparx5_pcb_common.dtsi"
0008
0009 /{
0010 gpio-restart {
0011 compatible = "gpio-restart";
0012 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
0013 priority = <200>;
0014 };
0015
0016 leds {
0017 compatible = "gpio-leds";
0018 led@0 {
0019 label = "eth60:yellow";
0020 gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
0021 default-state = "off";
0022 };
0023 led@1 {
0024 label = "eth60:green";
0025 gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
0026 default-state = "off";
0027 };
0028 led@2 {
0029 label = "eth61:yellow";
0030 gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
0031 default-state = "off";
0032 };
0033 led@3 {
0034 label = "eth61:green";
0035 gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
0036 default-state = "off";
0037 };
0038 led@4 {
0039 label = "eth62:yellow";
0040 gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
0041 default-state = "off";
0042 };
0043 led@5 {
0044 label = "eth62:green";
0045 gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
0046 default-state = "off";
0047 };
0048 led@6 {
0049 label = "eth63:yellow";
0050 gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
0051 default-state = "off";
0052 };
0053 led@7 {
0054 label = "eth63:green";
0055 gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
0056 default-state = "off";
0057 };
0058 };
0059 };
0060
0061 &gpio {
0062 i2cmux_pins_i: i2cmux-pins-i {
0063 pins = "GPIO_35", "GPIO_36",
0064 "GPIO_50", "GPIO_51";
0065 function = "twi_scl_m";
0066 output-low;
0067 };
0068 i2cmux_s29: i2cmux-0 {
0069 pins = "GPIO_35";
0070 function = "twi_scl_m";
0071 output-high;
0072 };
0073 i2cmux_s30: i2cmux-1 {
0074 pins = "GPIO_36";
0075 function = "twi_scl_m";
0076 output-high;
0077 };
0078 i2cmux_s31: i2cmux-2 {
0079 pins = "GPIO_50";
0080 function = "twi_scl_m";
0081 output-high;
0082 };
0083 i2cmux_s32: i2cmux-3 {
0084 pins = "GPIO_51";
0085 function = "twi_scl_m";
0086 output-high;
0087 };
0088 };
0089
0090 &spi0 {
0091 status = "okay";
0092 flash@0 {
0093 compatible = "jedec,spi-nor";
0094 spi-max-frequency = <8000000>;
0095 reg = <0>;
0096 };
0097 };
0098
0099 &spi0 {
0100 status = "okay";
0101 spi@0 {
0102 compatible = "spi-mux";
0103 mux-controls = <&mux>;
0104 #address-cells = <1>;
0105 #size-cells = <0>;
0106 reg = <0>; /* CS0 */
0107 flash@9 {
0108 compatible = "jedec,spi-nor";
0109 spi-max-frequency = <8000000>;
0110 reg = <0x9>; /* SPI */
0111 };
0112 };
0113 };
0114
0115 &sgpio1 {
0116 status = "okay";
0117 microchip,sgpio-port-ranges = <24 31>;
0118 gpio@0 {
0119 ngpios = <64>;
0120 };
0121 gpio@1 {
0122 ngpios = <64>;
0123 };
0124 };
0125
0126 &sgpio2 {
0127 status = "okay";
0128 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
0129 };
0130
0131 &axi {
0132 i2c0_imux: i2c0-imux@0 {
0133 compatible = "i2c-mux-pinctrl";
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 i2c-parent = <&i2c0>;
0137 };
0138 };
0139
0140 &i2c0_imux {
0141 pinctrl-names =
0142 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
0143 "idle";
0144 pinctrl-0 = <&i2cmux_s29>;
0145 pinctrl-1 = <&i2cmux_s30>;
0146 pinctrl-2 = <&i2cmux_s31>;
0147 pinctrl-3 = <&i2cmux_s32>;
0148 pinctrl-4 = <&i2cmux_pins_i>;
0149 i2c_sfp1: i2c_sfp1 {
0150 reg = <0x0>;
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 };
0154 i2c_sfp2: i2c_sfp2 {
0155 reg = <0x1>;
0156 #address-cells = <1>;
0157 #size-cells = <0>;
0158 };
0159 i2c_sfp3: i2c_sfp3 {
0160 reg = <0x2>;
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163 };
0164 i2c_sfp4: i2c_sfp4 {
0165 reg = <0x3>;
0166 #address-cells = <1>;
0167 #size-cells = <0>;
0168 };
0169 };
0170
0171 &axi {
0172 sfp_eth60: sfp-eth60 {
0173 compatible = "sff,sfp";
0174 i2c-bus = <&i2c_sfp1>;
0175 tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
0176 rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
0177 los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
0178 mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
0179 tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
0180 };
0181 sfp_eth61: sfp-eth61 {
0182 compatible = "sff,sfp";
0183 i2c-bus = <&i2c_sfp2>;
0184 tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
0185 rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
0186 los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
0187 mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
0188 tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
0189 };
0190 sfp_eth62: sfp-eth62 {
0191 compatible = "sff,sfp";
0192 i2c-bus = <&i2c_sfp3>;
0193 tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
0194 rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
0195 los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
0196 mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
0197 tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
0198 };
0199 sfp_eth63: sfp-eth63 {
0200 compatible = "sff,sfp";
0201 i2c-bus = <&i2c_sfp4>;
0202 tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
0203 rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
0204 los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
0205 mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
0206 tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
0207 };
0208 };
0209
0210 &mdio0 {
0211 status = "ok";
0212 phy0: ethernet-phy@0 {
0213 reg = <0>;
0214 };
0215 phy1: ethernet-phy@1 {
0216 reg = <1>;
0217 };
0218 phy2: ethernet-phy@2 {
0219 reg = <2>;
0220 };
0221 phy3: ethernet-phy@3 {
0222 reg = <3>;
0223 };
0224 phy4: ethernet-phy@4 {
0225 reg = <4>;
0226 };
0227 phy5: ethernet-phy@5 {
0228 reg = <5>;
0229 };
0230 phy6: ethernet-phy@6 {
0231 reg = <6>;
0232 };
0233 phy7: ethernet-phy@7 {
0234 reg = <7>;
0235 };
0236 phy8: ethernet-phy@8 {
0237 reg = <8>;
0238 };
0239 phy9: ethernet-phy@9 {
0240 reg = <9>;
0241 };
0242 phy10: ethernet-phy@10 {
0243 reg = <10>;
0244 };
0245 phy11: ethernet-phy@11 {
0246 reg = <11>;
0247 };
0248 phy12: ethernet-phy@12 {
0249 reg = <12>;
0250 };
0251 phy13: ethernet-phy@13 {
0252 reg = <13>;
0253 };
0254 phy14: ethernet-phy@14 {
0255 reg = <14>;
0256 };
0257 phy15: ethernet-phy@15 {
0258 reg = <15>;
0259 };
0260 phy16: ethernet-phy@16 {
0261 reg = <16>;
0262 };
0263 phy17: ethernet-phy@17 {
0264 reg = <17>;
0265 };
0266 phy18: ethernet-phy@18 {
0267 reg = <18>;
0268 };
0269 phy19: ethernet-phy@19 {
0270 reg = <19>;
0271 };
0272 phy20: ethernet-phy@20 {
0273 reg = <20>;
0274 };
0275 phy21: ethernet-phy@21 {
0276 reg = <21>;
0277 };
0278 phy22: ethernet-phy@22 {
0279 reg = <22>;
0280 };
0281 phy23: ethernet-phy@23 {
0282 reg = <23>;
0283 };
0284 };
0285
0286 &mdio1 {
0287 status = "ok";
0288 phy24: ethernet-phy@24 {
0289 reg = <0>;
0290 };
0291 phy25: ethernet-phy@25 {
0292 reg = <1>;
0293 };
0294 phy26: ethernet-phy@26 {
0295 reg = <2>;
0296 };
0297 phy27: ethernet-phy@27 {
0298 reg = <3>;
0299 };
0300 phy28: ethernet-phy@28 {
0301 reg = <4>;
0302 };
0303 phy29: ethernet-phy@29 {
0304 reg = <5>;
0305 };
0306 phy30: ethernet-phy@30 {
0307 reg = <6>;
0308 };
0309 phy31: ethernet-phy@31 {
0310 reg = <7>;
0311 };
0312 phy32: ethernet-phy@32 {
0313 reg = <8>;
0314 };
0315 phy33: ethernet-phy@33 {
0316 reg = <9>;
0317 };
0318 phy34: ethernet-phy@34 {
0319 reg = <10>;
0320 };
0321 phy35: ethernet-phy@35 {
0322 reg = <11>;
0323 };
0324 phy36: ethernet-phy@36 {
0325 reg = <12>;
0326 };
0327 phy37: ethernet-phy@37 {
0328 reg = <13>;
0329 };
0330 phy38: ethernet-phy@38 {
0331 reg = <14>;
0332 };
0333 phy39: ethernet-phy@39 {
0334 reg = <15>;
0335 };
0336 phy40: ethernet-phy@40 {
0337 reg = <16>;
0338 };
0339 phy41: ethernet-phy@41 {
0340 reg = <17>;
0341 };
0342 phy42: ethernet-phy@42 {
0343 reg = <18>;
0344 };
0345 phy43: ethernet-phy@43 {
0346 reg = <19>;
0347 };
0348 phy44: ethernet-phy@44 {
0349 reg = <20>;
0350 };
0351 phy45: ethernet-phy@45 {
0352 reg = <21>;
0353 };
0354 phy46: ethernet-phy@46 {
0355 reg = <22>;
0356 };
0357 phy47: ethernet-phy@47 {
0358 reg = <23>;
0359 };
0360 };
0361
0362 &mdio3 {
0363 status = "ok";
0364 phy64: ethernet-phy@64 {
0365 reg = <28>;
0366 };
0367 };
0368
0369 &switch {
0370 ethernet-ports {
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373
0374 port0: port@0 {
0375 reg = <0>;
0376 microchip,bandwidth = <1000>;
0377 phys = <&serdes 13>;
0378 phy-handle = <&phy0>;
0379 phy-mode = "qsgmii";
0380 };
0381 port1: port@1 {
0382 reg = <1>;
0383 microchip,bandwidth = <1000>;
0384 phys = <&serdes 13>;
0385 phy-handle = <&phy1>;
0386 phy-mode = "qsgmii";
0387 };
0388 port2: port@2 {
0389 reg = <2>;
0390 microchip,bandwidth = <1000>;
0391 phys = <&serdes 13>;
0392 phy-handle = <&phy2>;
0393 phy-mode = "qsgmii";
0394 };
0395 port3: port@3 {
0396 reg = <3>;
0397 microchip,bandwidth = <1000>;
0398 phys = <&serdes 13>;
0399 phy-handle = <&phy3>;
0400 phy-mode = "qsgmii";
0401 };
0402 port4: port@4 {
0403 reg = <4>;
0404 microchip,bandwidth = <1000>;
0405 phys = <&serdes 14>;
0406 phy-handle = <&phy4>;
0407 phy-mode = "qsgmii";
0408 };
0409 port5: port@5 {
0410 reg = <5>;
0411 microchip,bandwidth = <1000>;
0412 phys = <&serdes 14>;
0413 phy-handle = <&phy5>;
0414 phy-mode = "qsgmii";
0415 };
0416 port6: port@6 {
0417 reg = <6>;
0418 microchip,bandwidth = <1000>;
0419 phys = <&serdes 14>;
0420 phy-handle = <&phy6>;
0421 phy-mode = "qsgmii";
0422 };
0423 port7: port@7 {
0424 reg = <7>;
0425 microchip,bandwidth = <1000>;
0426 phys = <&serdes 14>;
0427 phy-handle = <&phy7>;
0428 phy-mode = "qsgmii";
0429 };
0430 port8: port@8 {
0431 reg = <8>;
0432 microchip,bandwidth = <1000>;
0433 phys = <&serdes 15>;
0434 phy-handle = <&phy8>;
0435 phy-mode = "qsgmii";
0436 };
0437 port9: port@9 {
0438 reg = <9>;
0439 microchip,bandwidth = <1000>;
0440 phys = <&serdes 15>;
0441 phy-handle = <&phy9>;
0442 phy-mode = "qsgmii";
0443 };
0444 port10: port@10 {
0445 reg = <10>;
0446 microchip,bandwidth = <1000>;
0447 phys = <&serdes 15>;
0448 phy-handle = <&phy10>;
0449 phy-mode = "qsgmii";
0450 };
0451 port11: port@11 {
0452 reg = <11>;
0453 microchip,bandwidth = <1000>;
0454 phys = <&serdes 15>;
0455 phy-handle = <&phy11>;
0456 phy-mode = "qsgmii";
0457 };
0458 port12: port@12 {
0459 reg = <12>;
0460 microchip,bandwidth = <1000>;
0461 phys = <&serdes 16>;
0462 phy-handle = <&phy12>;
0463 phy-mode = "qsgmii";
0464 };
0465 port13: port@13 {
0466 reg = <13>;
0467 microchip,bandwidth = <1000>;
0468 phys = <&serdes 16>;
0469 phy-handle = <&phy13>;
0470 phy-mode = "qsgmii";
0471 };
0472 port14: port@14 {
0473 reg = <14>;
0474 microchip,bandwidth = <1000>;
0475 phys = <&serdes 16>;
0476 phy-handle = <&phy14>;
0477 phy-mode = "qsgmii";
0478 };
0479 port15: port@15 {
0480 reg = <15>;
0481 microchip,bandwidth = <1000>;
0482 phys = <&serdes 16>;
0483 phy-handle = <&phy15>;
0484 phy-mode = "qsgmii";
0485 };
0486 port16: port@16 {
0487 reg = <16>;
0488 microchip,bandwidth = <1000>;
0489 phys = <&serdes 17>;
0490 phy-handle = <&phy16>;
0491 phy-mode = "qsgmii";
0492 };
0493 port17: port@17 {
0494 reg = <17>;
0495 microchip,bandwidth = <1000>;
0496 phys = <&serdes 17>;
0497 phy-handle = <&phy17>;
0498 phy-mode = "qsgmii";
0499 };
0500 port18: port@18 {
0501 reg = <18>;
0502 microchip,bandwidth = <1000>;
0503 phys = <&serdes 17>;
0504 phy-handle = <&phy18>;
0505 phy-mode = "qsgmii";
0506 };
0507 port19: port@19 {
0508 reg = <19>;
0509 microchip,bandwidth = <1000>;
0510 phys = <&serdes 17>;
0511 phy-handle = <&phy19>;
0512 phy-mode = "qsgmii";
0513 };
0514 port20: port@20 {
0515 reg = <20>;
0516 microchip,bandwidth = <1000>;
0517 phys = <&serdes 18>;
0518 phy-handle = <&phy20>;
0519 phy-mode = "qsgmii";
0520 };
0521 port21: port@21 {
0522 reg = <21>;
0523 microchip,bandwidth = <1000>;
0524 phys = <&serdes 18>;
0525 phy-handle = <&phy21>;
0526 phy-mode = "qsgmii";
0527 };
0528 port22: port@22 {
0529 reg = <22>;
0530 microchip,bandwidth = <1000>;
0531 phys = <&serdes 18>;
0532 phy-handle = <&phy22>;
0533 phy-mode = "qsgmii";
0534 };
0535 port23: port@23 {
0536 reg = <23>;
0537 microchip,bandwidth = <1000>;
0538 phys = <&serdes 18>;
0539 phy-handle = <&phy23>;
0540 phy-mode = "qsgmii";
0541 };
0542 port24: port@24 {
0543 reg = <24>;
0544 microchip,bandwidth = <1000>;
0545 phys = <&serdes 19>;
0546 phy-handle = <&phy24>;
0547 phy-mode = "qsgmii";
0548 };
0549 port25: port@25 {
0550 reg = <25>;
0551 microchip,bandwidth = <1000>;
0552 phys = <&serdes 19>;
0553 phy-handle = <&phy25>;
0554 phy-mode = "qsgmii";
0555 };
0556 port26: port@26 {
0557 reg = <26>;
0558 microchip,bandwidth = <1000>;
0559 phys = <&serdes 19>;
0560 phy-handle = <&phy26>;
0561 phy-mode = "qsgmii";
0562 };
0563 port27: port@27 {
0564 reg = <27>;
0565 microchip,bandwidth = <1000>;
0566 phys = <&serdes 19>;
0567 phy-handle = <&phy27>;
0568 phy-mode = "qsgmii";
0569 };
0570 port28: port@28 {
0571 reg = <28>;
0572 microchip,bandwidth = <1000>;
0573 phys = <&serdes 20>;
0574 phy-handle = <&phy28>;
0575 phy-mode = "qsgmii";
0576 };
0577 port29: port@29 {
0578 reg = <29>;
0579 microchip,bandwidth = <1000>;
0580 phys = <&serdes 20>;
0581 phy-handle = <&phy29>;
0582 phy-mode = "qsgmii";
0583 };
0584 port30: port@30 {
0585 reg = <30>;
0586 microchip,bandwidth = <1000>;
0587 phys = <&serdes 20>;
0588 phy-handle = <&phy30>;
0589 phy-mode = "qsgmii";
0590 };
0591 port31: port@31 {
0592 reg = <31>;
0593 microchip,bandwidth = <1000>;
0594 phys = <&serdes 20>;
0595 phy-handle = <&phy31>;
0596 phy-mode = "qsgmii";
0597 };
0598 port32: port@32 {
0599 reg = <32>;
0600 microchip,bandwidth = <1000>;
0601 phys = <&serdes 21>;
0602 phy-handle = <&phy32>;
0603 phy-mode = "qsgmii";
0604 };
0605 port33: port@33 {
0606 reg = <33>;
0607 microchip,bandwidth = <1000>;
0608 phys = <&serdes 21>;
0609 phy-handle = <&phy33>;
0610 phy-mode = "qsgmii";
0611 };
0612 port34: port@34 {
0613 reg = <34>;
0614 microchip,bandwidth = <1000>;
0615 phys = <&serdes 21>;
0616 phy-handle = <&phy34>;
0617 phy-mode = "qsgmii";
0618 };
0619 port35: port@35 {
0620 reg = <35>;
0621 microchip,bandwidth = <1000>;
0622 phys = <&serdes 21>;
0623 phy-handle = <&phy35>;
0624 phy-mode = "qsgmii";
0625 };
0626 port36: port@36 {
0627 reg = <36>;
0628 microchip,bandwidth = <1000>;
0629 phys = <&serdes 22>;
0630 phy-handle = <&phy36>;
0631 phy-mode = "qsgmii";
0632 };
0633 port37: port@37 {
0634 reg = <37>;
0635 microchip,bandwidth = <1000>;
0636 phys = <&serdes 22>;
0637 phy-handle = <&phy37>;
0638 phy-mode = "qsgmii";
0639 };
0640 port38: port@38 {
0641 reg = <38>;
0642 microchip,bandwidth = <1000>;
0643 phys = <&serdes 22>;
0644 phy-handle = <&phy38>;
0645 phy-mode = "qsgmii";
0646 };
0647 port39: port@39 {
0648 reg = <39>;
0649 microchip,bandwidth = <1000>;
0650 phys = <&serdes 22>;
0651 phy-handle = <&phy39>;
0652 phy-mode = "qsgmii";
0653 };
0654 port40: port@40 {
0655 reg = <40>;
0656 microchip,bandwidth = <1000>;
0657 phys = <&serdes 23>;
0658 phy-handle = <&phy40>;
0659 phy-mode = "qsgmii";
0660 };
0661 port41: port@41 {
0662 reg = <41>;
0663 microchip,bandwidth = <1000>;
0664 phys = <&serdes 23>;
0665 phy-handle = <&phy41>;
0666 phy-mode = "qsgmii";
0667 };
0668 port42: port@42 {
0669 reg = <42>;
0670 microchip,bandwidth = <1000>;
0671 phys = <&serdes 23>;
0672 phy-handle = <&phy42>;
0673 phy-mode = "qsgmii";
0674 };
0675 port43: port@43 {
0676 reg = <43>;
0677 microchip,bandwidth = <1000>;
0678 phys = <&serdes 23>;
0679 phy-handle = <&phy43>;
0680 phy-mode = "qsgmii";
0681 };
0682 port44: port@44 {
0683 reg = <44>;
0684 microchip,bandwidth = <1000>;
0685 phys = <&serdes 24>;
0686 phy-handle = <&phy44>;
0687 phy-mode = "qsgmii";
0688 };
0689 port45: port@45 {
0690 reg = <45>;
0691 microchip,bandwidth = <1000>;
0692 phys = <&serdes 24>;
0693 phy-handle = <&phy45>;
0694 phy-mode = "qsgmii";
0695 };
0696 port46: port@46 {
0697 reg = <46>;
0698 microchip,bandwidth = <1000>;
0699 phys = <&serdes 24>;
0700 phy-handle = <&phy46>;
0701 phy-mode = "qsgmii";
0702 };
0703 port47: port@47 {
0704 reg = <47>;
0705 microchip,bandwidth = <1000>;
0706 phys = <&serdes 24>;
0707 phy-handle = <&phy47>;
0708 phy-mode = "qsgmii";
0709 };
0710 /* Then the 25G interfaces */
0711 port60: port@60 {
0712 reg = <60>;
0713 microchip,bandwidth = <25000>;
0714 phys = <&serdes 29>;
0715 phy-mode = "10gbase-r";
0716 sfp = <&sfp_eth60>;
0717 managed = "in-band-status";
0718 };
0719 port61: port@61 {
0720 reg = <61>;
0721 microchip,bandwidth = <25000>;
0722 phys = <&serdes 30>;
0723 phy-mode = "10gbase-r";
0724 sfp = <&sfp_eth61>;
0725 managed = "in-band-status";
0726 };
0727 port62: port@62 {
0728 reg = <62>;
0729 microchip,bandwidth = <25000>;
0730 phys = <&serdes 31>;
0731 phy-mode = "10gbase-r";
0732 sfp = <&sfp_eth62>;
0733 managed = "in-band-status";
0734 };
0735 port63: port@63 {
0736 reg = <63>;
0737 microchip,bandwidth = <25000>;
0738 phys = <&serdes 32>;
0739 phy-mode = "10gbase-r";
0740 sfp = <&sfp_eth63>;
0741 managed = "in-band-status";
0742 };
0743 /* Finally the Management interface */
0744 port64: port@64 {
0745 reg = <64>;
0746 microchip,bandwidth = <1000>;
0747 phys = <&serdes 0>;
0748 phy-handle = <&phy64>;
0749 phy-mode = "sgmii";
0750 };
0751 };
0752 };
