0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (c) 2019 MediaTek Inc.
0004 * Copyright (c) 2019 BayLibre, SAS.
0005 * Author: Fabien Parent <fparent@baylibre.com>
0006 */
0007
0008 #include <dt-bindings/clock/mt8516-clk.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/phy/phy.h>
0012
0013 #include "mt8516-pinfunc.h"
0014
0015 / {
0016 compatible = "mediatek,mt8516";
0017 interrupt-parent = <&sysirq>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 cluster0_opp: opp-table-0 {
0022 compatible = "operating-points-v2";
0023 opp-shared;
0024 opp-598000000 {
0025 opp-hz = /bits/ 64 <598000000>;
0026 opp-microvolt = <1150000>;
0027 };
0028 opp-747500000 {
0029 opp-hz = /bits/ 64 <747500000>;
0030 opp-microvolt = <1150000>;
0031 };
0032 opp-1040000000 {
0033 opp-hz = /bits/ 64 <1040000000>;
0034 opp-microvolt = <1200000>;
0035 };
0036 opp-1196000000 {
0037 opp-hz = /bits/ 64 <1196000000>;
0038 opp-microvolt = <1250000>;
0039 };
0040 opp-1300000000 {
0041 opp-hz = /bits/ 64 <1300000000>;
0042 opp-microvolt = <1300000>;
0043 };
0044 };
0045
0046 cpus {
0047 #address-cells = <1>;
0048 #size-cells = <0>;
0049
0050 cpu0: cpu@0 {
0051 device_type = "cpu";
0052 compatible = "arm,cortex-a35";
0053 reg = <0x0>;
0054 enable-method = "psci";
0055 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
0056 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
0057 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
0058 <&topckgen CLK_TOP_MAINPLL_D2>;
0059 clock-names = "cpu", "intermediate";
0060 operating-points-v2 = <&cluster0_opp>;
0061 };
0062
0063 cpu1: cpu@1 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a35";
0066 reg = <0x1>;
0067 enable-method = "psci";
0068 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
0069 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
0070 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
0071 <&topckgen CLK_TOP_MAINPLL_D2>;
0072 clock-names = "cpu", "intermediate";
0073 operating-points-v2 = <&cluster0_opp>;
0074 };
0075
0076 cpu2: cpu@2 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a35";
0079 reg = <0x2>;
0080 enable-method = "psci";
0081 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
0082 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
0083 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
0084 <&topckgen CLK_TOP_MAINPLL_D2>;
0085 clock-names = "cpu", "intermediate";
0086 operating-points-v2 = <&cluster0_opp>;
0087 };
0088
0089 cpu3: cpu@3 {
0090 device_type = "cpu";
0091 compatible = "arm,cortex-a35";
0092 reg = <0x3>;
0093 enable-method = "psci";
0094 cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
0095 <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
0096 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
0097 <&topckgen CLK_TOP_MAINPLL_D2>;
0098 clock-names = "cpu", "intermediate", "armpll";
0099 operating-points-v2 = <&cluster0_opp>;
0100 };
0101
0102 idle-states {
0103 entry-method = "psci";
0104
0105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
0106 compatible = "arm,idle-state";
0107 entry-latency-us = <600>;
0108 exit-latency-us = <600>;
0109 min-residency-us = <1200>;
0110 arm,psci-suspend-param = <0x0010000>;
0111 };
0112
0113 CLUSTER_SLEEP_0: cluster-sleep-0 {
0114 compatible = "arm,idle-state";
0115 entry-latency-us = <800>;
0116 exit-latency-us = <1000>;
0117 min-residency-us = <2000>;
0118 arm,psci-suspend-param = <0x2010000>;
0119 };
0120 };
0121 };
0122
0123 psci {
0124 compatible = "arm,psci-1.0";
0125 method = "smc";
0126 };
0127
0128 clk26m: clk26m {
0129 compatible = "fixed-clock";
0130 #clock-cells = <0>;
0131 clock-frequency = <26000000>;
0132 clock-output-names = "clk26m";
0133 };
0134
0135 clk32k: clk32k {
0136 compatible = "fixed-clock";
0137 #clock-cells = <0>;
0138 clock-frequency = <32000>;
0139 clock-output-names = "clk32k";
0140 };
0141
0142 reserved-memory {
0143 #address-cells = <2>;
0144 #size-cells = <2>;
0145 ranges;
0146
0147 /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
0148 bl31_secmon_reserved: secmon@43000000 {
0149 no-map;
0150 reg = <0 0x43000000 0 0x20000>;
0151 };
0152 };
0153
0154 timer {
0155 compatible = "arm,armv8-timer";
0156 interrupt-parent = <&gic>;
0157 interrupts = <GIC_PPI 13
0158 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0159 <GIC_PPI 14
0160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0161 <GIC_PPI 11
0162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0163 <GIC_PPI 10
0164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0165 };
0166
0167 pmu {
0168 compatible = "arm,armv8-pmuv3";
0169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
0170 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
0171 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
0172 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
0173 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0174 };
0175
0176 soc {
0177 #address-cells = <2>;
0178 #size-cells = <2>;
0179 compatible = "simple-bus";
0180 ranges;
0181
0182 topckgen: topckgen@10000000 {
0183 compatible = "mediatek,mt8516-topckgen", "syscon";
0184 reg = <0 0x10000000 0 0x1000>;
0185 #clock-cells = <1>;
0186 };
0187
0188 infracfg: infracfg@10001000 {
0189 compatible = "mediatek,mt8516-infracfg", "syscon";
0190 reg = <0 0x10001000 0 0x1000>;
0191 #clock-cells = <1>;
0192 };
0193
0194 pericfg: pericfg@10003050 {
0195 compatible = "mediatek,mt8516-pericfg", "syscon";
0196 reg = <0 0x10003050 0 0x1000>;
0197 };
0198
0199 apmixedsys: apmixedsys@10018000 {
0200 compatible = "mediatek,mt8516-apmixedsys", "syscon";
0201 reg = <0 0x10018000 0 0x710>;
0202 #clock-cells = <1>;
0203 };
0204
0205 toprgu: toprgu@10007000 {
0206 compatible = "mediatek,mt8516-wdt",
0207 "mediatek,mt6589-wdt";
0208 reg = <0 0x10007000 0 0x1000>;
0209 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
0210 #reset-cells = <1>;
0211 };
0212
0213 timer: timer@10008000 {
0214 compatible = "mediatek,mt8516-timer",
0215 "mediatek,mt6577-timer";
0216 reg = <0 0x10008000 0 0x1000>;
0217 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
0218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
0219 <&topckgen CLK_TOP_APXGPT>;
0220 clock-names = "clk13m", "bus";
0221 };
0222
0223 syscfg_pctl: syscfg-pctl@10005000 {
0224 compatible = "syscon";
0225 reg = <0 0x10005000 0 0x1000>;
0226 };
0227
0228 pio: pinctrl@1000b000 {
0229 compatible = "mediatek,mt8516-pinctrl";
0230 reg = <0 0x1000b000 0 0x1000>;
0231 mediatek,pctl-regmap = <&syscfg_pctl>;
0232 pins-are-numbered;
0233 gpio-controller;
0234 #gpio-cells = <2>;
0235 interrupt-controller;
0236 #interrupt-cells = <2>;
0237 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0238 };
0239
0240 efuse: efuse@10009000 {
0241 compatible = "mediatek,mt8516-efuse", "mediatek,efuse";
0242 reg = <0 0x10009000 0 0x1000>;
0243 #address-cells = <1>;
0244 #size-cells = <1>;
0245 };
0246
0247 pwrap: pwrap@1000f000 {
0248 compatible = "mediatek,mt8516-pwrap";
0249 reg = <0 0x1000f000 0 0x1000>;
0250 reg-names = "pwrap";
0251 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
0252 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
0253 <&topckgen CLK_TOP_PMICWRAP_AP>;
0254 clock-names = "spi", "wrap";
0255 };
0256
0257 sysirq: interrupt-controller@10200620 {
0258 compatible = "mediatek,mt8516-sysirq",
0259 "mediatek,mt6577-sysirq";
0260 interrupt-controller;
0261 #interrupt-cells = <3>;
0262 interrupt-parent = <&gic>;
0263 reg = <0 0x10200620 0 0x20>;
0264 };
0265
0266 gic: interrupt-controller@10310000 {
0267 compatible = "arm,gic-400";
0268 #interrupt-cells = <3>;
0269 interrupt-parent = <&gic>;
0270 interrupt-controller;
0271 reg = <0 0x10310000 0 0x1000>,
0272 <0 0x10320000 0 0x1000>,
0273 <0 0x10340000 0 0x2000>,
0274 <0 0x10360000 0 0x2000>;
0275 interrupts = <GIC_PPI 9
0276 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0277 };
0278
0279 apdma: dma-controller@11000480 {
0280 compatible = "mediatek,mt8516-uart-dma",
0281 "mediatek,mt6577-uart-dma";
0282 reg = <0 0x11000480 0 0x80>,
0283 <0 0x11000500 0 0x80>,
0284 <0 0x11000580 0 0x80>,
0285 <0 0x11000600 0 0x80>,
0286 <0 0x11000980 0 0x80>,
0287 <0 0x11000a00 0 0x80>;
0288 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
0289 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
0290 <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
0291 <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
0292 <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
0293 <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
0294 dma-requests = <6>;
0295 clocks = <&topckgen CLK_TOP_APDMA>;
0296 clock-names = "apdma";
0297 #dma-cells = <1>;
0298 };
0299
0300 uart0: serial@11005000 {
0301 compatible = "mediatek,mt8516-uart",
0302 "mediatek,mt6577-uart";
0303 reg = <0 0x11005000 0 0x1000>;
0304 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0305 clocks = <&topckgen CLK_TOP_UART0_SEL>,
0306 <&topckgen CLK_TOP_UART0>;
0307 clock-names = "baud", "bus";
0308 dmas = <&apdma 0
0309 &apdma 1>;
0310 dma-names = "tx", "rx";
0311 status = "disabled";
0312 };
0313
0314 uart1: serial@11006000 {
0315 compatible = "mediatek,mt8516-uart",
0316 "mediatek,mt6577-uart";
0317 reg = <0 0x11006000 0 0x1000>;
0318 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
0319 clocks = <&topckgen CLK_TOP_UART1_SEL>,
0320 <&topckgen CLK_TOP_UART1>;
0321 clock-names = "baud", "bus";
0322 dmas = <&apdma 2
0323 &apdma 3>;
0324 dma-names = "tx", "rx";
0325 status = "disabled";
0326 };
0327
0328 uart2: serial@11007000 {
0329 compatible = "mediatek,mt8516-uart",
0330 "mediatek,mt6577-uart";
0331 reg = <0 0x11007000 0 0x1000>;
0332 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
0333 clocks = <&topckgen CLK_TOP_UART2_SEL>,
0334 <&topckgen CLK_TOP_UART2>;
0335 clock-names = "baud", "bus";
0336 dmas = <&apdma 4
0337 &apdma 5>;
0338 dma-names = "tx", "rx";
0339 status = "disabled";
0340 };
0341
0342 i2c0: i2c@11009000 {
0343 compatible = "mediatek,mt8516-i2c",
0344 "mediatek,mt2712-i2c";
0345 reg = <0 0x11009000 0 0x90>,
0346 <0 0x11000180 0 0x80>;
0347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
0348 clocks = <&topckgen CLK_TOP_I2C0>,
0349 <&topckgen CLK_TOP_APDMA>;
0350 clock-names = "main", "dma";
0351 #address-cells = <1>;
0352 #size-cells = <0>;
0353 status = "disabled";
0354 };
0355
0356 i2c1: i2c@1100a000 {
0357 compatible = "mediatek,mt8516-i2c",
0358 "mediatek,mt2712-i2c";
0359 reg = <0 0x1100a000 0 0x90>,
0360 <0 0x11000200 0 0x80>;
0361 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
0362 clocks = <&topckgen CLK_TOP_I2C1>,
0363 <&topckgen CLK_TOP_APDMA>;
0364 clock-names = "main", "dma";
0365 #address-cells = <1>;
0366 #size-cells = <0>;
0367 status = "disabled";
0368 };
0369
0370 i2c2: i2c@1100b000 {
0371 compatible = "mediatek,mt8516-i2c",
0372 "mediatek,mt2712-i2c";
0373 reg = <0 0x1100b000 0 0x90>,
0374 <0 0x11000280 0 0x80>;
0375 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
0376 clocks = <&topckgen CLK_TOP_I2C2>,
0377 <&topckgen CLK_TOP_APDMA>;
0378 clock-names = "main", "dma";
0379 #address-cells = <1>;
0380 #size-cells = <0>;
0381 status = "disabled";
0382 };
0383
0384 spi: spi@1100c000 {
0385 compatible = "mediatek,mt8516-spi",
0386 "mediatek,mt2712-spi";
0387 #address-cells = <1>;
0388 #size-cells = <0>;
0389 reg = <0 0x1100c000 0 0x1000>;
0390 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
0391 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
0392 <&topckgen CLK_TOP_SPI_SEL>,
0393 <&topckgen CLK_TOP_SPI>;
0394 clock-names = "parent-clk", "sel-clk", "spi-clk";
0395 status = "disabled";
0396 };
0397
0398 mmc0: mmc@11120000 {
0399 compatible = "mediatek,mt8516-mmc";
0400 reg = <0 0x11120000 0 0x1000>;
0401 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
0402 clocks = <&topckgen CLK_TOP_MSDC0>,
0403 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
0404 <&topckgen CLK_TOP_MSDC0_INFRA>;
0405 clock-names = "source", "hclk", "source_cg";
0406 status = "disabled";
0407 };
0408
0409 mmc1: mmc@11130000 {
0410 compatible = "mediatek,mt8516-mmc";
0411 reg = <0 0x11130000 0 0x1000>;
0412 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0413 clocks = <&topckgen CLK_TOP_MSDC1>,
0414 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
0415 <&topckgen CLK_TOP_MSDC1_INFRA>;
0416 clock-names = "source", "hclk", "source_cg";
0417 status = "disabled";
0418 };
0419
0420 mmc2: mmc@11170000 {
0421 compatible = "mediatek,mt8516-mmc";
0422 reg = <0 0x11170000 0 0x1000>;
0423 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
0424 clocks = <&topckgen CLK_TOP_MSDC2>,
0425 <&topckgen CLK_TOP_RG_MSDC2>,
0426 <&topckgen CLK_TOP_MSDC2_INFRA>;
0427 clock-names = "source", "hclk", "source_cg";
0428 status = "disabled";
0429 };
0430
0431 ethernet: ethernet@11180000 {
0432 compatible = "mediatek,mt8516-eth";
0433 reg = <0 0x11180000 0 0x1000>;
0434 mediatek,pericfg = <&pericfg>;
0435 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
0436 clocks = <&topckgen CLK_TOP_RG_ETH>,
0437 <&topckgen CLK_TOP_66M_ETH>,
0438 <&topckgen CLK_TOP_133M_ETH>;
0439 clock-names = "core", "reg", "trans";
0440 status = "disabled";
0441 };
0442
0443 rng: rng@1020c000 {
0444 compatible = "mediatek,mt8516-rng",
0445 "mediatek,mt7623-rng";
0446 reg = <0 0x1020c000 0 0x100>;
0447 clocks = <&topckgen CLK_TOP_TRNG>;
0448 clock-names = "rng";
0449 };
0450
0451 pwm: pwm@11008000 {
0452 compatible = "mediatek,mt8516-pwm";
0453 reg = <0 0x11008000 0 0x1000>;
0454 #pwm-cells = <2>;
0455 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
0456 clocks = <&topckgen CLK_TOP_PWM>,
0457 <&topckgen CLK_TOP_PWM_B>,
0458 <&topckgen CLK_TOP_PWM1_FB>,
0459 <&topckgen CLK_TOP_PWM2_FB>,
0460 <&topckgen CLK_TOP_PWM3_FB>,
0461 <&topckgen CLK_TOP_PWM4_FB>,
0462 <&topckgen CLK_TOP_PWM5_FB>;
0463 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
0464 "pwm4", "pwm5";
0465 };
0466
0467 usb0: usb@11100000 {
0468 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
0469 reg = <0 0x11100000 0 0x1000>;
0470 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
0471 interrupt-names = "mc";
0472 phys = <&usb0_port PHY_TYPE_USB2>;
0473 clocks = <&topckgen CLK_TOP_USB>,
0474 <&topckgen CLK_TOP_USBIF>,
0475 <&topckgen CLK_TOP_USB_1P>;
0476 clock-names = "main","mcu","univpll";
0477 status = "disabled";
0478 };
0479
0480 usb1: usb@11190000 {
0481 compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb";
0482 reg = <0 0x11190000 0 0x1000>;
0483 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
0484 interrupt-names = "mc";
0485 phys = <&usb1_port PHY_TYPE_USB2>;
0486 clocks = <&topckgen CLK_TOP_USB>,
0487 <&topckgen CLK_TOP_USBIF>,
0488 <&topckgen CLK_TOP_USB_1P>;
0489 clock-names = "main","mcu","univpll";
0490 dr_mode = "host";
0491 status = "disabled";
0492 };
0493
0494 usb_phy: t-phy@11110000 {
0495 compatible = "mediatek,mt8516-tphy",
0496 "mediatek,generic-tphy-v1";
0497 reg = <0 0x11110000 0 0x800>;
0498 #address-cells = <2>;
0499 #size-cells = <2>;
0500 ranges;
0501 status = "disabled";
0502
0503 usb0_port: usb-phy@11110800 {
0504 reg = <0 0x11110800 0 0x100>;
0505 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0506 clock-names = "ref";
0507 #phy-cells = <1>;
0508 };
0509
0510 usb1_port: usb-phy@11110900 {
0511 reg = <0 0x11110900 0 0x100>;
0512 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
0513 clock-names = "ref";
0514 #phy-cells = <1>;
0515 };
0516 };
0517
0518 auxadc: adc@11003000 {
0519 compatible = "mediatek,mt8516-auxadc",
0520 "mediatek,mt8173-auxadc";
0521 reg = <0 0x11003000 0 0x1000>;
0522 clocks = <&topckgen CLK_TOP_AUX_ADC>;
0523 clock-names = "main";
0524 #io-channel-cells = <1>;
0525 status = "disabled";
0526 };
0527 };
0528 };
