0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2020 Marvell International Ltd.
0004 *
0005 * Device tree for the CN9131-DB board.
0006 */
0007
0008 #include "cn9130-db.dtsi"
0009
0010 / {
0011 compatible = "marvell,cn9131", "marvell,cn9130",
0012 "marvell,armada-ap807-quad", "marvell,armada-ap807";
0013
0014 aliases {
0015 gpio3 = &cp1_gpio1;
0016 gpio4 = &cp1_gpio2;
0017 ethernet3 = &cp1_eth0;
0018 ethernet4 = &cp1_eth1;
0019 };
0020
0021 cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
0022 compatible = "regulator-fixed";
0023 pinctrl-names = "default";
0024 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
0025 regulator-name = "cp1-xhci0-vbus";
0026 regulator-min-microvolt = <5000000>;
0027 regulator-max-microvolt = <5000000>;
0028 enable-active-high;
0029 gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
0030 };
0031
0032 cp1_usb3_0_phy0: cp1_usb3_phy0 {
0033 compatible = "usb-nop-xceiv";
0034 vcc-supply = <&cp1_reg_usb3_vbus0>;
0035 };
0036
0037 cp1_sfp_eth1: sfp-eth1 {
0038 compatible = "sff,sfp";
0039 i2c-bus = <&cp1_i2c0>;
0040 los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
0041 mod-def0-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
0042 tx-disable-gpios = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
0043 tx-fault-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&cp1_sfp_pins>;
0046 /*
0047 * SFP cages are unconnected on early PCBs because of an the I2C
0048 * lanes not being connected. Prevent the port for being
0049 * unusable by disabling the SFP node.
0050 */
0051 status = "disabled";
0052 };
0053 };
0054
0055 /*
0056 * Instantiate the first slave CP115
0057 */
0058
0059 #define CP11X_NAME cp1
0060 #define CP11X_BASE f4000000
0061 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
0062 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
0063 #define CP11X_PCIE0_BASE f4600000
0064 #define CP11X_PCIE1_BASE f4620000
0065 #define CP11X_PCIE2_BASE f4640000
0066
0067 #include "armada-cp115.dtsi"
0068
0069 #undef CP11X_NAME
0070 #undef CP11X_BASE
0071 #undef CP11X_PCIEx_MEM_BASE
0072 #undef CP11X_PCIEx_MEM_SIZE
0073 #undef CP11X_PCIE0_BASE
0074 #undef CP11X_PCIE1_BASE
0075 #undef CP11X_PCIE2_BASE
0076
0077 &cp1_crypto {
0078 status = "disabled";
0079 };
0080
0081 &cp1_ethernet {
0082 status = "okay";
0083 };
0084
0085 /* CON50 */
0086 &cp1_eth0 {
0087 status = "okay";
0088 phy-mode = "10gbase-r";
0089 /* Generic PHY, providing serdes lanes */
0090 phys = <&cp1_comphy4 0>;
0091 managed = "in-band-status";
0092 sfp = <&cp1_sfp_eth1>;
0093 };
0094
0095 &cp1_gpio1 {
0096 status = "okay";
0097 };
0098
0099 &cp1_gpio2 {
0100 status = "okay";
0101 };
0102
0103 &cp1_i2c0 {
0104 status = "okay";
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&cp1_i2c0_pins>;
0107 clock-frequency = <100000>;
0108 };
0109
0110 /* CON40 */
0111 &cp1_pcie0 {
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&cp1_pcie_reset_pins>;
0114 num-lanes = <2>;
0115 num-viewport = <8>;
0116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
0117 status = "okay";
0118 /* Generic PHY, providing serdes lanes */
0119 phys = <&cp1_comphy0 0
0120 &cp1_comphy1 0>;
0121 };
0122
0123 &cp1_sata0 {
0124 status = "okay";
0125
0126 /* CON32 */
0127 sata-port@1 {
0128 /* Generic PHY, providing serdes lanes */
0129 phys = <&cp1_comphy5 1>;
0130 };
0131 };
0132
0133 /* U24 */
0134 &cp1_spi1 {
0135 status = "okay";
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&cp1_spi0_pins>;
0138 reg = <0x700680 0x50>;
0139
0140 flash@0 {
0141 #address-cells = <0x1>;
0142 #size-cells = <0x1>;
0143 compatible = "jedec,spi-nor";
0144 reg = <0x0>;
0145 /* On-board MUX does not allow higher frequencies */
0146 spi-max-frequency = <40000000>;
0147
0148 partitions {
0149 compatible = "fixed-partitions";
0150 #address-cells = <1>;
0151 #size-cells = <1>;
0152
0153 partition@0 {
0154 label = "U-Boot-1";
0155 reg = <0x0 0x200000>;
0156 };
0157
0158 partition@400000 {
0159 label = "Filesystem-1";
0160 reg = <0x200000 0xe00000>;
0161 };
0162 };
0163 };
0164
0165 };
0166
0167 &cp1_syscon0 {
0168 cp1_pinctrl: pinctrl {
0169 compatible = "marvell,cp115-standalone-pinctrl";
0170
0171 cp1_i2c0_pins: cp1-i2c-pins-0 {
0172 marvell,pins = "mpp37", "mpp38";
0173 marvell,function = "i2c0";
0174 };
0175 cp1_spi0_pins: cp1-spi-pins-0 {
0176 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
0177 marvell,function = "spi1";
0178 };
0179 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
0180 marvell,pins = "mpp3";
0181 marvell,function = "gpio";
0182 };
0183 cp1_sfp_pins: sfp-pins {
0184 marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
0185 marvell,function = "gpio";
0186 };
0187 cp1_pcie_reset_pins: cp1-pcie-reset-pins {
0188 marvell,pins = "mpp0";
0189 marvell,function = "gpio";
0190 };
0191 };
0192 };
0193
0194 /* CON58 */
0195 &cp1_utmi {
0196 status = "okay";
0197 };
0198
0199 &cp1_usb3_1 {
0200 status = "okay";
0201 usb-phy = <&cp1_usb3_0_phy0>;
0202 /* Generic PHY, providing serdes lanes */
0203 phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
0204 phy-names = "usb", "utmi";
0205 dr_mode = "host";
0206 };
