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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2019 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for Marvell Armada AP80x.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/thermal/thermal.h>
0010
0011 /dts-v1/;
0012
0013 / {
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 aliases {
0018 serial0 = &uart0;
0019 serial1 = &uart1;
0020 gpio0 = &ap_gpio;
0021 spi0 = &spi0;
0022 };
0023
0024 psci {
0025 compatible = "arm,psci-0.2";
0026 method = "smc";
0027 };
0028
0029 reserved-memory {
0030 #address-cells = <2>;
0031 #size-cells = <2>;
0032 ranges;
0033
0034 /*
0035 * This area matches the mapping done with a
0036 * mainline U-Boot, and should be updated by the
0037 * bootloader.
0038 */
0039
0040 psci-area@4000000 {
0041 reg = <0x0 0x4000000 0x0 0x200000>;
0042 no-map;
0043 };
0044 };
0045
0046 AP_NAME {
0047 #address-cells = <2>;
0048 #size-cells = <2>;
0049 compatible = "simple-bus";
0050 interrupt-parent = <&gic>;
0051 ranges;
0052
0053 config-space@f0000000 {
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 compatible = "simple-bus";
0057 ranges = <0x0 0x0 0xf0000000 0x1000000>;
0058
0059 smmu: iommu@5000000 {
0060 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
0061 reg = <0x100000 0x100000>;
0062 dma-coherent;
0063 #iommu-cells = <1>;
0064 #global-interrupts = <1>;
0065 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0066 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0070 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0072 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0073 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0074 status = "disabled";
0075 };
0076
0077 gic: interrupt-controller@210000 {
0078 compatible = "arm,gic-400";
0079 #interrupt-cells = <3>;
0080 #address-cells = <1>;
0081 #size-cells = <1>;
0082 ranges;
0083 interrupt-controller;
0084 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0085 reg = <0x210000 0x10000>,
0086 <0x220000 0x20000>,
0087 <0x240000 0x20000>,
0088 <0x260000 0x20000>;
0089
0090 gic_v2m0: v2m@280000 {
0091 compatible = "arm,gic-v2m-frame";
0092 msi-controller;
0093 reg = <0x280000 0x1000>;
0094 arm,msi-base-spi = <160>;
0095 arm,msi-num-spis = <32>;
0096 };
0097 gic_v2m1: v2m@290000 {
0098 compatible = "arm,gic-v2m-frame";
0099 msi-controller;
0100 reg = <0x290000 0x1000>;
0101 arm,msi-base-spi = <192>;
0102 arm,msi-num-spis = <32>;
0103 };
0104 gic_v2m2: v2m@2a0000 {
0105 compatible = "arm,gic-v2m-frame";
0106 msi-controller;
0107 reg = <0x2a0000 0x1000>;
0108 arm,msi-base-spi = <224>;
0109 arm,msi-num-spis = <32>;
0110 };
0111 gic_v2m3: v2m@2b0000 {
0112 compatible = "arm,gic-v2m-frame";
0113 msi-controller;
0114 reg = <0x2b0000 0x1000>;
0115 arm,msi-base-spi = <256>;
0116 arm,msi-num-spis = <32>;
0117 };
0118 };
0119
0120 timer {
0121 compatible = "arm,armv8-timer";
0122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0126 };
0127
0128 pmu {
0129 compatible = "arm,cortex-a72-pmu";
0130 interrupt-parent = <&pic>;
0131 interrupts = <17>;
0132 };
0133
0134 odmi: odmi@300000 {
0135 compatible = "marvell,odmi-controller";
0136 interrupt-controller;
0137 msi-controller;
0138 marvell,odmi-frames = <4>;
0139 reg = <0x300000 0x4000>,
0140 <0x304000 0x4000>,
0141 <0x308000 0x4000>,
0142 <0x30C000 0x4000>;
0143 marvell,spi-base = <128>, <136>, <144>, <152>;
0144 };
0145
0146 gicp: gicp@3f0040 {
0147 compatible = "marvell,ap806-gicp";
0148 reg = <0x3f0040 0x10>;
0149 marvell,spi-ranges = <64 64>, <288 64>;
0150 msi-controller;
0151 };
0152
0153 pic: interrupt-controller@3f0100 {
0154 compatible = "marvell,armada-8k-pic";
0155 reg = <0x3f0100 0x10>;
0156 #interrupt-cells = <1>;
0157 interrupt-controller;
0158 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0159 };
0160
0161 sei: interrupt-controller@3f0200 {
0162 compatible = "marvell,ap806-sei";
0163 reg = <0x3f0200 0x40>;
0164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0165 #interrupt-cells = <1>;
0166 interrupt-controller;
0167 msi-controller;
0168 };
0169
0170 xor@400000 {
0171 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0172 reg = <0x400000 0x1000>,
0173 <0x410000 0x1000>;
0174 msi-parent = <&gic_v2m0>;
0175 clocks = <&ap_clk 3>;
0176 dma-coherent;
0177 };
0178
0179 xor@420000 {
0180 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0181 reg = <0x420000 0x1000>,
0182 <0x430000 0x1000>;
0183 msi-parent = <&gic_v2m0>;
0184 clocks = <&ap_clk 3>;
0185 dma-coherent;
0186 };
0187
0188 xor@440000 {
0189 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0190 reg = <0x440000 0x1000>,
0191 <0x450000 0x1000>;
0192 msi-parent = <&gic_v2m0>;
0193 clocks = <&ap_clk 3>;
0194 dma-coherent;
0195 };
0196
0197 xor@460000 {
0198 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0199 reg = <0x460000 0x1000>,
0200 <0x470000 0x1000>;
0201 msi-parent = <&gic_v2m0>;
0202 clocks = <&ap_clk 3>;
0203 dma-coherent;
0204 };
0205
0206 spi0: spi@510600 {
0207 compatible = "marvell,armada-380-spi";
0208 reg = <0x510600 0x50>;
0209 #address-cells = <1>;
0210 #size-cells = <0>;
0211 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0212 clocks = <&ap_clk 3>;
0213 status = "disabled";
0214 };
0215
0216 i2c0: i2c@511000 {
0217 compatible = "marvell,mv78230-i2c";
0218 reg = <0x511000 0x20>;
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0222 clocks = <&ap_clk 3>;
0223 status = "disabled";
0224 };
0225
0226 uart0: serial@512000 {
0227 compatible = "snps,dw-apb-uart";
0228 reg = <0x512000 0x100>;
0229 reg-shift = <2>;
0230 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0231 reg-io-width = <1>;
0232 clocks = <&ap_clk 3>;
0233 status = "disabled";
0234 };
0235
0236 uart1: serial@512100 {
0237 compatible = "snps,dw-apb-uart";
0238 reg = <0x512100 0x100>;
0239 reg-shift = <2>;
0240 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0241 reg-io-width = <1>;
0242 clocks = <&ap_clk 3>;
0243 status = "disabled";
0244
0245 };
0246
0247 watchdog: watchdog@610000 {
0248 compatible = "arm,sbsa-gwdt";
0249 reg = <0x610000 0x1000>, <0x600000 0x1000>;
0250 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0251 };
0252
0253 ap_sdhci0: mmc@6e0000 {
0254 compatible = "marvell,armada-ap806-sdhci";
0255 reg = <0x6e0000 0x300>;
0256 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0257 clock-names = "core";
0258 clocks = <&ap_clk 4>;
0259 dma-coherent;
0260 marvell,xenon-phy-slow-mode;
0261 status = "disabled";
0262 };
0263
0264 ap_syscon0: system-controller@6f4000 {
0265 compatible = "syscon", "simple-mfd";
0266 reg = <0x6f4000 0x2000>;
0267
0268 ap_pinctrl: pinctrl {
0269 compatible = "marvell,ap806-pinctrl";
0270
0271 uart0_pins: uart0-pins {
0272 marvell,pins = "mpp11", "mpp19";
0273 marvell,function = "uart0";
0274 };
0275 };
0276
0277 ap_gpio: gpio@1040 {
0278 compatible = "marvell,armada-8k-gpio";
0279 offset = <0x1040>;
0280 ngpios = <20>;
0281 gpio-controller;
0282 #gpio-cells = <2>;
0283 gpio-ranges = <&ap_pinctrl 0 0 20>;
0284 marvell,pwm-offset = <0x10c0>;
0285 #pwm-cells = <2>;
0286 clocks = <&ap_clk 3>;
0287 };
0288 };
0289
0290 ap_syscon1: system-controller@6f8000 {
0291 compatible = "syscon", "simple-mfd";
0292 reg = <0x6f8000 0x1000>;
0293 #address-cells = <1>;
0294 #size-cells = <1>;
0295
0296 ap_thermal: thermal-sensor@80 {
0297 compatible = "marvell,armada-ap806-thermal";
0298 reg = <0x80 0x10>;
0299 interrupt-parent = <&sei>;
0300 interrupts = <18>;
0301 #thermal-sensor-cells = <1>;
0302 };
0303 };
0304 };
0305 };
0306
0307 /*
0308 * The thermal IP features one internal sensor plus, if applicable, one
0309 * remote channel wired to one sensor per CPU.
0310 *
0311 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
0312 * first one that will have a critical trip point will be chosen.
0313 */
0314 thermal-zones {
0315 ap_thermal_ic: ap-thermal-ic {
0316 polling-delay-passive = <0>; /* Interrupt driven */
0317 polling-delay = <0>; /* Interrupt driven */
0318
0319 thermal-sensors = <&ap_thermal 0>;
0320
0321 trips {
0322 ap_crit: ap-crit {
0323 temperature = <100000>; /* mC degrees */
0324 hysteresis = <2000>; /* mC degrees */
0325 type = "critical";
0326 };
0327 };
0328
0329 cooling-maps { };
0330 };
0331
0332 ap_thermal_cpu0: ap-thermal-cpu0 {
0333 polling-delay-passive = <1000>;
0334 polling-delay = <1000>;
0335
0336 thermal-sensors = <&ap_thermal 1>;
0337
0338 trips {
0339 cpu0_hot: cpu0-hot {
0340 temperature = <85000>;
0341 hysteresis = <2000>;
0342 type = "passive";
0343 };
0344 cpu0_emerg: cpu0-emerg {
0345 temperature = <95000>;
0346 hysteresis = <2000>;
0347 type = "passive";
0348 };
0349 };
0350
0351 cooling-maps {
0352 map0_hot: map0-hot {
0353 trip = <&cpu0_hot>;
0354 cooling-device = <&cpu0 1 2>,
0355 <&cpu1 1 2>;
0356 };
0357 map0_emerg: map0-ermerg {
0358 trip = <&cpu0_emerg>;
0359 cooling-device = <&cpu0 3 3>,
0360 <&cpu1 3 3>;
0361 };
0362 };
0363 };
0364
0365 ap_thermal_cpu1: ap-thermal-cpu1 {
0366 polling-delay-passive = <1000>;
0367 polling-delay = <1000>;
0368
0369 thermal-sensors = <&ap_thermal 2>;
0370
0371 trips {
0372 cpu1_hot: cpu1-hot {
0373 temperature = <85000>;
0374 hysteresis = <2000>;
0375 type = "passive";
0376 };
0377 cpu1_emerg: cpu1-emerg {
0378 temperature = <95000>;
0379 hysteresis = <2000>;
0380 type = "passive";
0381 };
0382 };
0383
0384 cooling-maps {
0385 map1_hot: map1-hot {
0386 trip = <&cpu1_hot>;
0387 cooling-device = <&cpu0 1 2>,
0388 <&cpu1 1 2>;
0389 };
0390 map1_emerg: map1-emerg {
0391 trip = <&cpu1_emerg>;
0392 cooling-device = <&cpu0 3 3>,
0393 <&cpu1 3 3>;
0394 };
0395 };
0396 };
0397
0398 ap_thermal_cpu2: ap-thermal-cpu2 {
0399 polling-delay-passive = <1000>;
0400 polling-delay = <1000>;
0401
0402 thermal-sensors = <&ap_thermal 3>;
0403
0404 trips {
0405 cpu2_hot: cpu2-hot {
0406 temperature = <85000>;
0407 hysteresis = <2000>;
0408 type = "passive";
0409 };
0410 cpu2_emerg: cpu2-emerg {
0411 temperature = <95000>;
0412 hysteresis = <2000>;
0413 type = "passive";
0414 };
0415 };
0416
0417 cooling-maps {
0418 map2_hot: map2-hot {
0419 trip = <&cpu2_hot>;
0420 cooling-device = <&cpu2 1 2>,
0421 <&cpu3 1 2>;
0422 };
0423 map2_emerg: map2-emerg {
0424 trip = <&cpu2_emerg>;
0425 cooling-device = <&cpu2 3 3>,
0426 <&cpu3 3 3>;
0427 };
0428 };
0429 };
0430
0431 ap_thermal_cpu3: ap-thermal-cpu3 {
0432 polling-delay-passive = <1000>;
0433 polling-delay = <1000>;
0434
0435 thermal-sensors = <&ap_thermal 4>;
0436
0437 trips {
0438 cpu3_hot: cpu3-hot {
0439 temperature = <85000>;
0440 hysteresis = <2000>;
0441 type = "passive";
0442 };
0443 cpu3_emerg: cpu3-emerg {
0444 temperature = <95000>;
0445 hysteresis = <2000>;
0446 type = "passive";
0447 };
0448 };
0449
0450 cooling-maps {
0451 map3_hot: map3-bhot {
0452 trip = <&cpu3_hot>;
0453 cooling-device = <&cpu2 1 2>,
0454 <&cpu3 1 2>;
0455 };
0456 map3_emerg: map3-emerg {
0457 trip = <&cpu3_emerg>;
0458 cooling-device = <&cpu2 3 3>,
0459 <&cpu3 3 3>;
0460 };
0461 };
0462 };
0463 };
0464 };
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