0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for Marvell Armada AP806.
0006 */
0007
0008 #include "armada-ap806.dtsi"
0009
0010 / {
0011 model = "Marvell Armada AP806 Dual";
0012 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu0: cpu@0 {
0019 device_type = "cpu";
0020 compatible = "arm,cortex-a72";
0021 reg = <0x000>;
0022 enable-method = "psci";
0023 #cooling-cells = <2>;
0024 clocks = <&cpu_clk 0>;
0025 i-cache-size = <0xc000>;
0026 i-cache-line-size = <64>;
0027 i-cache-sets = <256>;
0028 d-cache-size = <0x8000>;
0029 d-cache-line-size = <64>;
0030 d-cache-sets = <256>;
0031 next-level-cache = <&l2>;
0032 };
0033 cpu1: cpu@1 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a72";
0036 reg = <0x001>;
0037 enable-method = "psci";
0038 #cooling-cells = <2>;
0039 clocks = <&cpu_clk 0>;
0040 i-cache-size = <0xc000>;
0041 i-cache-line-size = <64>;
0042 i-cache-sets = <256>;
0043 d-cache-size = <0x8000>;
0044 d-cache-line-size = <64>;
0045 d-cache-sets = <256>;
0046 next-level-cache = <&l2>;
0047 };
0048
0049 l2: l2-cache {
0050 compatible = "cache";
0051 cache-size = <0x80000>;
0052 cache-line-size = <64>;
0053 cache-sets = <512>;
0054 };
0055 };
0056
0057 thermal-zones {
0058 /delete-node/ ap-thermal-cpu2;
0059 /delete-node/ ap-thermal-cpu3;
0060 };
0061 };
