0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2019, Intel Corporation
0004 */
0005
0006 /dts-v1/;
0007 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/clock/agilex-clock.h>
0011
0012 / {
0013 compatible = "intel,socfpga-agilex";
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 reserved-memory {
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020 ranges;
0021
0022 service_reserved: svcbuffer@0 {
0023 compatible = "shared-dma-pool";
0024 reg = <0x0 0x0 0x0 0x2000000>;
0025 alignment = <0x1000>;
0026 no-map;
0027 };
0028 };
0029
0030 cpus {
0031 #address-cells = <1>;
0032 #size-cells = <0>;
0033
0034 cpu0: cpu@0 {
0035 compatible = "arm,cortex-a53";
0036 device_type = "cpu";
0037 enable-method = "psci";
0038 reg = <0x0>;
0039 };
0040
0041 cpu1: cpu@1 {
0042 compatible = "arm,cortex-a53";
0043 device_type = "cpu";
0044 enable-method = "psci";
0045 reg = <0x1>;
0046 };
0047
0048 cpu2: cpu@2 {
0049 compatible = "arm,cortex-a53";
0050 device_type = "cpu";
0051 enable-method = "psci";
0052 reg = <0x2>;
0053 };
0054
0055 cpu3: cpu@3 {
0056 compatible = "arm,cortex-a53";
0057 device_type = "cpu";
0058 enable-method = "psci";
0059 reg = <0x3>;
0060 };
0061 };
0062
0063 pmu {
0064 compatible = "arm,armv8-pmuv3";
0065 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0066 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0069 interrupt-affinity = <&cpu0>,
0070 <&cpu1>,
0071 <&cpu2>,
0072 <&cpu3>;
0073 interrupt-parent = <&intc>;
0074 };
0075
0076 psci {
0077 compatible = "arm,psci-0.2";
0078 method = "smc";
0079 };
0080
0081 intc: interrupt-controller@fffc1000 {
0082 compatible = "arm,gic-400", "arm,cortex-a15-gic";
0083 #interrupt-cells = <3>;
0084 interrupt-controller;
0085 reg = <0x0 0xfffc1000 0x0 0x1000>,
0086 <0x0 0xfffc2000 0x0 0x2000>,
0087 <0x0 0xfffc4000 0x0 0x2000>,
0088 <0x0 0xfffc6000 0x0 0x2000>;
0089 };
0090
0091 clocks {
0092 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
0093 #clock-cells = <0>;
0094 compatible = "fixed-clock";
0095 };
0096
0097 cb_intosc_ls_clk: cb-intosc-ls-clk {
0098 #clock-cells = <0>;
0099 compatible = "fixed-clock";
0100 };
0101
0102 f2s_free_clk: f2s-free-clk {
0103 #clock-cells = <0>;
0104 compatible = "fixed-clock";
0105 };
0106
0107 osc1: osc1 {
0108 #clock-cells = <0>;
0109 compatible = "fixed-clock";
0110 };
0111
0112 qspi_clk: qspi-clk {
0113 #clock-cells = <0>;
0114 compatible = "fixed-clock";
0115 clock-frequency = <200000000>;
0116 };
0117 };
0118
0119 timer {
0120 compatible = "arm,armv8-timer";
0121 interrupt-parent = <&intc>;
0122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0126 };
0127
0128 usbphy0: usbphy {
0129 #phy-cells = <0>;
0130 compatible = "usb-nop-xceiv";
0131 };
0132
0133 soc {
0134 #address-cells = <1>;
0135 #size-cells = <1>;
0136 compatible = "simple-bus";
0137 device_type = "soc";
0138 interrupt-parent = <&intc>;
0139 ranges = <0 0 0 0xffffffff>;
0140
0141 base_fpga_region {
0142 #address-cells = <0x1>;
0143 #size-cells = <0x1>;
0144 compatible = "fpga-region";
0145 fpga-mgr = <&fpga_mgr>;
0146 };
0147
0148 clkmgr: clock-controller@ffd10000 {
0149 compatible = "intel,agilex-clkmgr";
0150 reg = <0xffd10000 0x1000>;
0151 #clock-cells = <1>;
0152 };
0153
0154 gmac0: ethernet@ff800000 {
0155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0156 reg = <0xff800000 0x2000>;
0157 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0158 interrupt-names = "macirq";
0159 mac-address = [00 00 00 00 00 00];
0160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
0161 reset-names = "stmmaceth", "stmmaceth-ocp";
0162 tx-fifo-depth = <16384>;
0163 rx-fifo-depth = <16384>;
0164 snps,multicast-filter-bins = <256>;
0165 iommus = <&smmu 1>;
0166 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
0167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
0168 clock-names = "stmmaceth", "ptp_ref";
0169 status = "disabled";
0170 };
0171
0172 gmac1: ethernet@ff802000 {
0173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0174 reg = <0xff802000 0x2000>;
0175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0176 interrupt-names = "macirq";
0177 mac-address = [00 00 00 00 00 00];
0178 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
0179 reset-names = "stmmaceth", "stmmaceth-ocp";
0180 tx-fifo-depth = <16384>;
0181 rx-fifo-depth = <16384>;
0182 snps,multicast-filter-bins = <256>;
0183 iommus = <&smmu 2>;
0184 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
0185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
0186 clock-names = "stmmaceth", "ptp_ref";
0187 status = "disabled";
0188 };
0189
0190 gmac2: ethernet@ff804000 {
0191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
0192 reg = <0xff804000 0x2000>;
0193 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0194 interrupt-names = "macirq";
0195 mac-address = [00 00 00 00 00 00];
0196 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
0197 reset-names = "stmmaceth", "stmmaceth-ocp";
0198 tx-fifo-depth = <16384>;
0199 rx-fifo-depth = <16384>;
0200 snps,multicast-filter-bins = <256>;
0201 iommus = <&smmu 3>;
0202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
0203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
0204 clock-names = "stmmaceth", "ptp_ref";
0205 status = "disabled";
0206 };
0207
0208 gpio0: gpio@ffc03200 {
0209 #address-cells = <1>;
0210 #size-cells = <0>;
0211 compatible = "snps,dw-apb-gpio";
0212 reg = <0xffc03200 0x100>;
0213 resets = <&rst GPIO0_RESET>;
0214 status = "disabled";
0215
0216 porta: gpio-controller@0 {
0217 compatible = "snps,dw-apb-gpio-port";
0218 gpio-controller;
0219 #gpio-cells = <2>;
0220 snps,nr-gpios = <24>;
0221 reg = <0>;
0222 interrupt-controller;
0223 #interrupt-cells = <2>;
0224 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0225 };
0226 };
0227
0228 gpio1: gpio@ffc03300 {
0229 #address-cells = <1>;
0230 #size-cells = <0>;
0231 compatible = "snps,dw-apb-gpio";
0232 reg = <0xffc03300 0x100>;
0233 resets = <&rst GPIO1_RESET>;
0234 status = "disabled";
0235
0236 portb: gpio-controller@0 {
0237 compatible = "snps,dw-apb-gpio-port";
0238 gpio-controller;
0239 #gpio-cells = <2>;
0240 snps,nr-gpios = <24>;
0241 reg = <0>;
0242 interrupt-controller;
0243 #interrupt-cells = <2>;
0244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0245 };
0246 };
0247
0248 i2c0: i2c@ffc02800 {
0249 #address-cells = <1>;
0250 #size-cells = <0>;
0251 compatible = "snps,designware-i2c";
0252 reg = <0xffc02800 0x100>;
0253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0254 resets = <&rst I2C0_RESET>;
0255 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0256 status = "disabled";
0257 };
0258
0259 i2c1: i2c@ffc02900 {
0260 #address-cells = <1>;
0261 #size-cells = <0>;
0262 compatible = "snps,designware-i2c";
0263 reg = <0xffc02900 0x100>;
0264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0265 resets = <&rst I2C1_RESET>;
0266 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0267 status = "disabled";
0268 };
0269
0270 i2c2: i2c@ffc02a00 {
0271 #address-cells = <1>;
0272 #size-cells = <0>;
0273 compatible = "snps,designware-i2c";
0274 reg = <0xffc02a00 0x100>;
0275 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0276 resets = <&rst I2C2_RESET>;
0277 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0278 status = "disabled";
0279 };
0280
0281 i2c3: i2c@ffc02b00 {
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 compatible = "snps,designware-i2c";
0285 reg = <0xffc02b00 0x100>;
0286 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0287 resets = <&rst I2C3_RESET>;
0288 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0289 status = "disabled";
0290 };
0291
0292 i2c4: i2c@ffc02c00 {
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295 compatible = "snps,designware-i2c";
0296 reg = <0xffc02c00 0x100>;
0297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0298 resets = <&rst I2C4_RESET>;
0299 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0300 status = "disabled";
0301 };
0302
0303 mmc: mmc@ff808000 {
0304 #address-cells = <1>;
0305 #size-cells = <0>;
0306 compatible = "altr,socfpga-dw-mshc";
0307 reg = <0xff808000 0x1000>;
0308 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0309 fifo-depth = <0x400>;
0310 resets = <&rst SDMMC_RESET>;
0311 reset-names = "reset";
0312 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
0313 <&clkmgr AGILEX_SDMMC_CLK>;
0314 clock-names = "biu", "ciu";
0315 iommus = <&smmu 5>;
0316 status = "disabled";
0317 };
0318
0319 nand: nand-controller@ffb90000 {
0320 #address-cells = <1>;
0321 #size-cells = <0>;
0322 compatible = "altr,socfpga-denali-nand";
0323 reg = <0xffb90000 0x10000>,
0324 <0xffb80000 0x1000>;
0325 reg-names = "nand_data", "denali_reg";
0326 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0327 clocks = <&clkmgr AGILEX_NAND_CLK>,
0328 <&clkmgr AGILEX_NAND_X_CLK>,
0329 <&clkmgr AGILEX_NAND_ECC_CLK>;
0330 clock-names = "nand", "nand_x", "ecc";
0331 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
0332 status = "disabled";
0333 };
0334
0335 ocram: sram@ffe00000 {
0336 compatible = "mmio-sram";
0337 reg = <0xffe00000 0x40000>;
0338 };
0339
0340 pdma: dma-controller@ffda0000 {
0341 compatible = "arm,pl330", "arm,primecell";
0342 reg = <0xffda0000 0x1000>;
0343 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0344 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0348 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0349 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0350 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0351 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0352 #dma-cells = <1>;
0353 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
0354 reset-names = "dma", "dma-ocp";
0355 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
0356 clock-names = "apb_pclk";
0357 };
0358
0359 rst: rstmgr@ffd11000 {
0360 #reset-cells = <1>;
0361 compatible = "altr,stratix10-rst-mgr";
0362 reg = <0xffd11000 0x100>;
0363 };
0364
0365 smmu: iommu@fa000000 {
0366 compatible = "arm,mmu-500", "arm,smmu-v2";
0367 reg = <0xfa000000 0x40000>;
0368 #global-interrupts = <2>;
0369 #iommu-cells = <1>;
0370 interrupt-parent = <&intc>;
0371 /* Global Secure Fault */
0372 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0373 /* Global Non-secure Fault */
0374 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0375 /* Non-secure Context Interrupts (32) */
0376 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0377 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0378 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0379 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0380 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0381 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
0382 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
0383 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
0384 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
0385 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
0386 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
0387 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0388 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0389 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0390 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0391 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0392 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
0393 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
0394 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
0395 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0396 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
0397 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
0398 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0399 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0400 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0401 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0402 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
0403 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0404 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
0405 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0406 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0407 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0408 stream-match-mask = <0x7ff0>;
0409 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
0410 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
0411 <&clkmgr AGILEX_L4_MAIN_CLK>;
0412 status = "disabled";
0413 };
0414
0415 spi0: spi@ffda4000 {
0416 compatible = "snps,dw-apb-ssi";
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419 reg = <0xffda4000 0x1000>;
0420 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0421 resets = <&rst SPIM0_RESET>;
0422 reset-names = "spi";
0423 reg-io-width = <4>;
0424 num-cs = <4>;
0425 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
0426 status = "disabled";
0427 };
0428
0429 spi1: spi@ffda5000 {
0430 compatible = "snps,dw-apb-ssi";
0431 #address-cells = <1>;
0432 #size-cells = <0>;
0433 reg = <0xffda5000 0x1000>;
0434 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0435 resets = <&rst SPIM1_RESET>;
0436 reset-names = "spi";
0437 reg-io-width = <4>;
0438 num-cs = <4>;
0439 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
0440 status = "disabled";
0441 };
0442
0443 sysmgr: sysmgr@ffd12000 {
0444 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
0445 reg = <0xffd12000 0x500>;
0446 };
0447
0448 timer0: timer0@ffc03000 {
0449 compatible = "snps,dw-apb-timer";
0450 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0451 reg = <0xffc03000 0x100>;
0452 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0453 clock-names = "timer";
0454 };
0455
0456 timer1: timer1@ffc03100 {
0457 compatible = "snps,dw-apb-timer";
0458 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0459 reg = <0xffc03100 0x100>;
0460 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0461 clock-names = "timer";
0462 };
0463
0464 timer2: timer2@ffd00000 {
0465 compatible = "snps,dw-apb-timer";
0466 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0467 reg = <0xffd00000 0x100>;
0468 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0469 clock-names = "timer";
0470 };
0471
0472 timer3: timer3@ffd00100 {
0473 compatible = "snps,dw-apb-timer";
0474 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0475 reg = <0xffd00100 0x100>;
0476 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0477 clock-names = "timer";
0478 };
0479
0480 uart0: serial@ffc02000 {
0481 compatible = "snps,dw-apb-uart";
0482 reg = <0xffc02000 0x100>;
0483 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0484 reg-shift = <2>;
0485 reg-io-width = <4>;
0486 resets = <&rst UART0_RESET>;
0487 status = "disabled";
0488 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0489 };
0490
0491 uart1: serial@ffc02100 {
0492 compatible = "snps,dw-apb-uart";
0493 reg = <0xffc02100 0x100>;
0494 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0495 reg-shift = <2>;
0496 reg-io-width = <4>;
0497 resets = <&rst UART1_RESET>;
0498 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
0499 status = "disabled";
0500 };
0501
0502 usb0: usb@ffb00000 {
0503 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
0504 reg = <0xffb00000 0x40000>;
0505 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0506 phys = <&usbphy0>;
0507 phy-names = "usb2-phy";
0508 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
0509 reset-names = "dwc2", "dwc2-ecc";
0510 clocks = <&clkmgr AGILEX_USB_CLK>;
0511 clock-names = "otg";
0512 iommus = <&smmu 6>;
0513 status = "disabled";
0514 };
0515
0516 usb1: usb@ffb40000 {
0517 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
0518 reg = <0xffb40000 0x40000>;
0519 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0520 phys = <&usbphy0>;
0521 phy-names = "usb2-phy";
0522 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
0523 reset-names = "dwc2", "dwc2-ecc";
0524 iommus = <&smmu 7>;
0525 clocks = <&clkmgr AGILEX_USB_CLK>;
0526 status = "disabled";
0527 };
0528
0529 watchdog0: watchdog@ffd00200 {
0530 compatible = "snps,dw-wdt";
0531 reg = <0xffd00200 0x100>;
0532 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0533 resets = <&rst WATCHDOG0_RESET>;
0534 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
0535 status = "disabled";
0536 };
0537
0538 watchdog1: watchdog@ffd00300 {
0539 compatible = "snps,dw-wdt";
0540 reg = <0xffd00300 0x100>;
0541 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0542 resets = <&rst WATCHDOG1_RESET>;
0543 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
0544 status = "disabled";
0545 };
0546
0547 watchdog2: watchdog@ffd00400 {
0548 compatible = "snps,dw-wdt";
0549 reg = <0xffd00400 0x100>;
0550 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0551 resets = <&rst WATCHDOG2_RESET>;
0552 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
0553 status = "disabled";
0554 };
0555
0556 watchdog3: watchdog@ffd00500 {
0557 compatible = "snps,dw-wdt";
0558 reg = <0xffd00500 0x100>;
0559 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0560 resets = <&rst WATCHDOG3_RESET>;
0561 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
0562 status = "disabled";
0563 };
0564
0565 sdr: sdr@f8011100 {
0566 compatible = "altr,sdr-ctl", "syscon";
0567 reg = <0xf8011100 0xc0>;
0568 };
0569
0570 eccmgr {
0571 compatible = "altr,socfpga-s10-ecc-manager",
0572 "altr,socfpga-a10-ecc-manager";
0573 altr,sysmgr-syscon = <&sysmgr>;
0574 #address-cells = <1>;
0575 #size-cells = <1>;
0576 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0577 interrupt-controller;
0578 #interrupt-cells = <2>;
0579 ranges;
0580
0581 sdramedac {
0582 compatible = "altr,sdram-edac-s10";
0583 altr,sdr-syscon = <&sdr>;
0584 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
0585 };
0586
0587 ocram-ecc@ff8cc000 {
0588 compatible = "altr,socfpga-s10-ocram-ecc",
0589 "altr,socfpga-a10-ocram-ecc";
0590 reg = <0xff8cc000 0x100>;
0591 altr,ecc-parent = <&ocram>;
0592 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0593 };
0594
0595 usb0-ecc@ff8c4000 {
0596 compatible = "altr,socfpga-s10-usb-ecc",
0597 "altr,socfpga-usb-ecc";
0598 reg = <0xff8c4000 0x100>;
0599 altr,ecc-parent = <&usb0>;
0600 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0601 };
0602
0603 emac0-rx-ecc@ff8c0000 {
0604 compatible = "altr,socfpga-s10-eth-mac-ecc",
0605 "altr,socfpga-eth-mac-ecc";
0606 reg = <0xff8c0000 0x100>;
0607 altr,ecc-parent = <&gmac0>;
0608 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0609 };
0610
0611 emac0-tx-ecc@ff8c0400 {
0612 compatible = "altr,socfpga-s10-eth-mac-ecc",
0613 "altr,socfpga-eth-mac-ecc";
0614 reg = <0xff8c0400 0x100>;
0615 altr,ecc-parent = <&gmac0>;
0616 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
0617 };
0618
0619 sdmmca-ecc@ff8c8c00 {
0620 compatible = "altr,socfpga-s10-sdmmc-ecc",
0621 "altr,socfpga-sdmmc-ecc";
0622 reg = <0xff8c8c00 0x100>;
0623 altr,ecc-parent = <&mmc>;
0624 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
0625 <15 IRQ_TYPE_LEVEL_HIGH>;
0626 };
0627 };
0628
0629 qspi: spi@ff8d2000 {
0630 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633 reg = <0xff8d2000 0x100>,
0634 <0xff900000 0x100000>;
0635 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0636 cdns,fifo-depth = <128>;
0637 cdns,fifo-width = <4>;
0638 cdns,trigger-address = <0x00000000>;
0639 clocks = <&qspi_clk>;
0640
0641 status = "disabled";
0642 };
0643
0644 firmware {
0645 svc {
0646 compatible = "intel,agilex-svc";
0647 method = "smc";
0648 memory-region = <&service_reserved>;
0649
0650 fpga_mgr: fpga-mgr {
0651 compatible = "intel,agilex-soc-fpga-mgr";
0652 };
0653 };
0654 };
0655 };
0656 };
