0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * NXP S32G2 SoC family
0004 *
0005 * Copyright (c) 2021 SUSE LLC
0006 * Copyright (c) 2017-2021 NXP
0007 */
0008
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 compatible = "nxp,s32g2";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a53";
0024 reg = <0x0>;
0025 enable-method = "psci";
0026 next-level-cache = <&cluster0_l2>;
0027 };
0028
0029 cpu1: cpu@1 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a53";
0032 reg = <0x1>;
0033 enable-method = "psci";
0034 next-level-cache = <&cluster0_l2>;
0035 };
0036
0037 cpu2: cpu@100 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a53";
0040 reg = <0x100>;
0041 enable-method = "psci";
0042 next-level-cache = <&cluster1_l2>;
0043 };
0044
0045 cpu3: cpu@101 {
0046 device_type = "cpu";
0047 compatible = "arm,cortex-a53";
0048 reg = <0x101>;
0049 enable-method = "psci";
0050 next-level-cache = <&cluster1_l2>;
0051 };
0052
0053 cluster0_l2: l2-cache0 {
0054 compatible = "cache";
0055 };
0056
0057 cluster1_l2: l2-cache1 {
0058 compatible = "cache";
0059 };
0060 };
0061
0062 pmu {
0063 compatible = "arm,cortex-a53-pmu";
0064 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0065 };
0066
0067 timer {
0068 compatible = "arm,armv8-timer";
0069 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
0070 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
0071 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
0072 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
0073 };
0074
0075 firmware {
0076 psci {
0077 compatible = "arm,psci-1.0";
0078 method = "smc";
0079 };
0080 };
0081
0082 soc@0 {
0083 compatible = "simple-bus";
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 ranges = <0 0 0 0x80000000>;
0087
0088 uart0: serial@401c8000 {
0089 compatible = "nxp,s32g2-linflexuart",
0090 "fsl,s32v234-linflexuart";
0091 reg = <0x401c8000 0x3000>;
0092 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
0093 status = "disabled";
0094 };
0095
0096 uart1: serial@401cc000 {
0097 compatible = "nxp,s32g2-linflexuart",
0098 "fsl,s32v234-linflexuart";
0099 reg = <0x401cc000 0x3000>;
0100 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
0101 status = "disabled";
0102 };
0103
0104 uart2: serial@402bc000 {
0105 compatible = "nxp,s32g2-linflexuart",
0106 "fsl,s32v234-linflexuart";
0107 reg = <0x402bc000 0x3000>;
0108 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
0109 status = "disabled";
0110 };
0111
0112 gic: interrupt-controller@50800000 {
0113 compatible = "arm,gic-v3";
0114 reg = <0x50800000 0x10000>,
0115 <0x50880000 0x80000>,
0116 <0x50400000 0x2000>,
0117 <0x50410000 0x2000>,
0118 <0x50420000 0x2000>;
0119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0120 interrupt-controller;
0121 #interrupt-cells = <3>;
0122 };
0123 };
0124 };
