0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2019 Zodiac Inflight Innovations
0004 */
0005
0006 #include "imx8mq.dtsi"
0007
0008 / {
0009 aliases {
0010 mdio-gpio0 = &mdio0;
0011 rtc0 = &ds1341;
0012 };
0013
0014 chosen {
0015 stdout-path = &uart1;
0016 };
0017
0018 mdio0: bitbang-mdio {
0019 compatible = "virtual,mdio-gpio";
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
0022 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
0023 <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
0024 #address-cells = <1>;
0025 #size-cells = <0>;
0026
0027 phy0: ethernet-phy@0 {
0028 reg = <0>;
0029 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
0030 };
0031 };
0032
0033 pcie0_refclk: clock-pcie0-refclk {
0034 compatible = "fixed-clock";
0035 #clock-cells = <0>;
0036 clock-frequency = <100000000>;
0037 };
0038
0039 pcie1_refclk: clock-pcie1-refclk {
0040 compatible = "fixed-clock";
0041 #clock-cells = <0>;
0042 clock-frequency = <100000000>;
0043 };
0044
0045 reg_12p0_main: regulator-12p0-main {
0046 compatible = "regulator-fixed";
0047 regulator-name = "12V_MAIN";
0048 regulator-min-microvolt = <12000000>;
0049 regulator-max-microvolt = <12000000>;
0050 regulator-always-on;
0051 };
0052
0053 reg_5p0_main: regulator-5p0-main {
0054 compatible = "regulator-fixed";
0055 vin-supply = <®_12p0_main>;
0056 regulator-name = "5V_MAIN";
0057 regulator-min-microvolt = <5000000>;
0058 regulator-max-microvolt = <5000000>;
0059 regulator-always-on;
0060 };
0061
0062 reg_3p3_main: regulator-3p3-main {
0063 compatible = "regulator-fixed";
0064 vin-supply = <®_12p0_main>;
0065 regulator-name = "3V3_MAIN";
0066 regulator-min-microvolt = <3300000>;
0067 regulator-max-microvolt = <3300000>;
0068 regulator-always-on;
0069 };
0070
0071 reg_gen_3p3: regulator-gen-3p3 {
0072 compatible = "regulator-fixed";
0073 vin-supply = <®_3p3_main>;
0074 regulator-name = "GEN_3V3";
0075 regulator-min-microvolt = <3300000>;
0076 regulator-max-microvolt = <3300000>;
0077 regulator-always-on;
0078 };
0079
0080 reg_usdhc2_vmmc: regulator-vsd-3v3 {
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_reg_usdhc2>;
0083 compatible = "regulator-fixed";
0084 vin-supply = <®_gen_3p3>;
0085 regulator-name = "3V3_SD";
0086 regulator-min-microvolt = <3300000>;
0087 regulator-max-microvolt = <3300000>;
0088 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0089 enable-active-high;
0090 };
0091
0092 reg_arm: regulator-arm {
0093 pinctrl-names = "default";
0094 pinctrl-0 = <&pinctrl_reg_arm>;
0095 compatible = "regulator-gpio";
0096 vin-supply = <®_12p0_main>;
0097 regulator-name = "0V9_ARM";
0098 regulator-min-microvolt = <900000>;
0099 regulator-max-microvolt = <1000000>;
0100 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
0101 states = <1000000 0x1
0102 900000 0x0>;
0103 regulator-always-on;
0104 };
0105
0106 cs2000_ref: cs2000-ref {
0107 compatible = "fixed-clock";
0108 #clock-cells = <0>;
0109 clock-frequency = <24576000>;
0110 };
0111
0112 cs2000_in_dummy: cs2000-in-dummy {
0113 compatible = "fixed-clock";
0114 #clock-cells = <0>;
0115 clock-frequency = <0>;
0116 };
0117 };
0118
0119 &A53_0 {
0120 cpu-supply = <®_arm>;
0121 };
0122
0123 &A53_1 {
0124 cpu-supply = <®_arm>;
0125 };
0126
0127 &A53_2 {
0128 cpu-supply = <®_arm>;
0129 };
0130
0131 &A53_3 {
0132 cpu-supply = <®_arm>;
0133 };
0134
0135 &fec1 {
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&pinctrl_fec1>;
0138
0139 phy-handle = <&phy0>;
0140 phy-mode = "rmii";
0141 status = "okay";
0142
0143 mdio {
0144 #address-cells = <1>;
0145 #size-cells = <0>;
0146 clock-frequency = <12500000>;
0147 suppress-preamble;
0148 status = "okay";
0149
0150 switch: switch@0 {
0151 compatible = "marvell,mv88e6085";
0152 pinctrl-0 = <&pinctrl_switch_irq>;
0153 pinctrl-names = "default";
0154 reg = <0>;
0155 dsa,member = <0 0>;
0156 eeprom-length = <512>;
0157 interrupt-parent = <&gpio1>;
0158 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
0159 interrupt-controller;
0160 #interrupt-cells = <2>;
0161
0162 ports {
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165
0166 port@0 {
0167 reg = <0>;
0168 label = "gigabit_proc";
0169 phy-handle = <&switchphy0>;
0170 };
0171
0172 port@1 {
0173 reg = <1>;
0174 label = "netaux";
0175 phy-handle = <&switchphy1>;
0176 };
0177
0178 port@2 {
0179 reg = <2>;
0180 label = "cpu";
0181 ethernet = <&fec1>;
0182
0183 fixed-link {
0184 speed = <100>;
0185 full-duplex;
0186 };
0187 };
0188
0189 port@3 {
0190 reg = <3>;
0191 label = "netright";
0192 phy-handle = <&switchphy3>;
0193 };
0194
0195 port@4 {
0196 reg = <4>;
0197 label = "netleft";
0198 phy-handle = <&switchphy4>;
0199 };
0200 };
0201
0202 mdio {
0203 #address-cells = <1>;
0204 #size-cells = <0>;
0205
0206 switchphy0: switchphy@0 {
0207 reg = <0>;
0208 interrupt-parent = <&switch>;
0209 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
0210 };
0211
0212 switchphy1: switchphy@1 {
0213 reg = <1>;
0214 interrupt-parent = <&switch>;
0215 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0216 };
0217
0218 switchphy2: switchphy@2 {
0219 reg = <2>;
0220 interrupt-parent = <&switch>;
0221 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0222 };
0223
0224 switchphy3: switchphy@3 {
0225 reg = <3>;
0226 interrupt-parent = <&switch>;
0227 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
0228 };
0229
0230 switchphy4: switchphy@4 {
0231 reg = <4>;
0232 interrupt-parent = <&switch>;
0233 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0234 };
0235 };
0236 };
0237 };
0238 };
0239
0240 &gpio3 {
0241 pinctrl-names = "default";
0242 pinctrl-0 = <&pinctrl_gpio3_hog>;
0243
0244 usb-emulation-hog {
0245 gpio-hog;
0246 gpios = <10 GPIO_ACTIVE_HIGH>;
0247 output-low;
0248 line-name = "usb-emulation";
0249 };
0250
0251 usb-mode1-hog {
0252 gpio-hog;
0253 gpios = <11 GPIO_ACTIVE_HIGH>;
0254 output-high;
0255 line-name = "usb-mode1";
0256 };
0257
0258 usb-pwr-hog {
0259 gpio-hog;
0260 gpios = <12 GPIO_ACTIVE_LOW>;
0261 output-high;
0262 line-name = "usb-pwr-ctrl-en-n";
0263 };
0264
0265 usb-mode2-hog {
0266 gpio-hog;
0267 gpios = <13 GPIO_ACTIVE_HIGH>;
0268 output-high;
0269 line-name = "usb-mode2";
0270 };
0271 };
0272
0273 &i2c1 {
0274 clock-frequency = <400000>;
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_i2c1>;
0277 status = "okay";
0278
0279 accelerometer@1c {
0280 compatible = "fsl,mma8451";
0281 pinctrl-names = "default";
0282 pinctrl-0 = <&pinctrl_accel>;
0283 reg = <0x1c>;
0284 interrupt-parent = <&gpio3>;
0285 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
0286 interrupt-names = "INT2";
0287 vdd-supply = <®_gen_3p3>;
0288 vddio-supply = <®_gen_3p3>;
0289 };
0290
0291 ucs1002: charger@32 {
0292 compatible = "microchip,ucs1002";
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&pinctrl_ucs1002>;
0295 reg = <0x32>;
0296 interrupt-parent = <&gpio3>;
0297 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
0298 <18 IRQ_TYPE_EDGE_FALLING>;
0299 interrupt-names = "a_det", "alert";
0300 };
0301
0302 hpa2: amp@60 {
0303 compatible = "ti,tpa6130a2";
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&pinctrl_tpa2>;
0306 reg = <0x60>;
0307 power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0308 Vdd-supply = <®_5p0_main>;
0309 sound-name-prefix = "HPA2";
0310 };
0311 };
0312
0313 &i2c2 {
0314 clock-frequency = <400000>;
0315 pinctrl-names = "default";
0316 pinctrl-0 = <&pinctrl_i2c2>;
0317 status = "okay";
0318
0319 pmic@8 {
0320 compatible = "fsl,pfuze100";
0321 reg = <0x8>;
0322
0323 regulators {
0324 sw1a_reg: sw1ab {
0325 regulator-min-microvolt = <825000>;
0326 regulator-max-microvolt = <1100000>;
0327 };
0328
0329 sw1c_reg: sw1c {
0330 regulator-min-microvolt = <825000>;
0331 regulator-max-microvolt = <1100000>;
0332 };
0333
0334 sw2_reg: sw2 {
0335 regulator-min-microvolt = <1100000>;
0336 regulator-max-microvolt = <1100000>;
0337 regulator-always-on;
0338 };
0339
0340 sw3a_reg: sw3ab {
0341 regulator-min-microvolt = <825000>;
0342 regulator-max-microvolt = <1100000>;
0343 regulator-always-on;
0344 };
0345
0346 sw4_reg: sw4 {
0347 regulator-min-microvolt = <1800000>;
0348 regulator-max-microvolt = <1800000>;
0349 regulator-always-on;
0350 };
0351
0352 swbst_reg: swbst {
0353 regulator-min-microvolt = <5000000>;
0354 regulator-max-microvolt = <5150000>;
0355 };
0356
0357 snvs_reg: vsnvs {
0358 regulator-min-microvolt = <1000000>;
0359 regulator-max-microvolt = <3000000>;
0360 regulator-always-on;
0361 };
0362
0363 vref_reg: vrefddr {
0364 regulator-always-on;
0365 };
0366
0367 vgen1_reg: vgen1 {
0368 regulator-min-microvolt = <800000>;
0369 regulator-max-microvolt = <1550000>;
0370 };
0371
0372 vgen2_reg: vgen2 {
0373 regulator-min-microvolt = <850000>;
0374 regulator-max-microvolt = <975000>;
0375 regulator-always-on;
0376 };
0377
0378 vgen3_reg: vgen3 {
0379 regulator-min-microvolt = <1675000>;
0380 regulator-max-microvolt = <1975000>;
0381 regulator-always-on;
0382 };
0383
0384 vgen4_reg: vgen4 {
0385 regulator-min-microvolt = <1625000>;
0386 regulator-max-microvolt = <1875000>;
0387 regulator-always-on;
0388 };
0389
0390 vgen5_reg: vgen5 {
0391 regulator-min-microvolt = <3075000>;
0392 regulator-max-microvolt = <3625000>;
0393 regulator-always-on;
0394 };
0395
0396 vgen6_reg: vgen6 {
0397 regulator-min-microvolt = <1800000>;
0398 regulator-max-microvolt = <3300000>;
0399 };
0400 };
0401 };
0402
0403 codec1: codec@18 {
0404 compatible = "ti,tlv320dac3100";
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_codec1>;
0407 reg = <0x18>;
0408 #sound-dai-cells = <0>;
0409 HPVDD-supply = <®_gen_3p3>;
0410 SPRVDD-supply = <®_gen_3p3>;
0411 SPLVDD-supply = <®_gen_3p3>;
0412 AVDD-supply = <®_gen_3p3>;
0413 IOVDD-supply = <®_gen_3p3>;
0414 DVDD-supply = <&vgen4_reg>;
0415 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
0416 };
0417
0418 eeprom@54 {
0419 compatible = "atmel,24c128";
0420 reg = <0x54>;
0421 };
0422
0423 hpa1: amp@60 {
0424 compatible = "ti,tpa6130a2";
0425 pinctrl-names = "default";
0426 pinctrl-0 = <&pinctrl_tpa1>;
0427 reg = <0x60>;
0428 power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
0429 Vdd-supply = <®_5p0_main>;
0430 sound-name-prefix = "HPA1";
0431 };
0432
0433 ds1341: rtc@68 {
0434 compatible = "dallas,ds1341";
0435 reg = <0x68>;
0436 };
0437 };
0438
0439 &i2c3 {
0440 clock-frequency = <100000>;
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&pinctrl_i2c3>;
0443 status = "okay";
0444
0445 usbhub: usbhub@2c {
0446 compatible = "microchip,usb2513b";
0447 pinctrl-names = "default";
0448 pinctrl-0 = <&pinctrl_usbhub>;
0449 reg = <0x2c>;
0450 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
0451 };
0452
0453 watchdog@38 {
0454 compatible = "zii,rave-wdt";
0455 reg = <0x38>;
0456 };
0457
0458 cs2000: clkgen@4e {
0459 compatible = "cirrus,cs2000-cp";
0460 reg = <0x4e>;
0461 #clock-cells = <0>;
0462 clock-names = "clk_in", "ref_clk";
0463 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
0464 assigned-clocks = <&cs2000>;
0465 assigned-clock-rates = <24000000>;
0466 };
0467 };
0468
0469 &i2c4 {
0470 clock-frequency = <400000>;
0471 pinctrl-names = "default";
0472 pinctrl-0 = <&pinctrl_i2c4>;
0473 status = "okay";
0474 };
0475
0476 &sai2 {
0477 pinctrl-names = "default";
0478 pinctrl-0 = <&pinctrl_sai2>;
0479 status = "okay";
0480 };
0481
0482 &uart1 {
0483 pinctrl-names = "default";
0484 pinctrl-0 = <&pinctrl_uart1>;
0485 status = "okay";
0486 };
0487
0488 &uart2 {
0489 pinctrl-names = "default";
0490 pinctrl-0 = <&pinctrl_uart2>;
0491 status = "okay";
0492
0493 rave-sp {
0494 compatible = "zii,rave-sp-rdu2";
0495 current-speed = <1000000>;
0496 #address-cells = <1>;
0497 #size-cells = <1>;
0498
0499 watchdog {
0500 compatible = "zii,rave-sp-watchdog";
0501 };
0502
0503 backlight {
0504 compatible = "zii,rave-sp-backlight";
0505 };
0506
0507 pwrbutton {
0508 compatible = "zii,rave-sp-pwrbutton";
0509 };
0510
0511 eeprom@a3 {
0512 compatible = "zii,rave-sp-eeprom";
0513 reg = <0xa3 0x4000>;
0514 zii,eeprom-name = "dds-eeprom";
0515 };
0516
0517 eeprom@a4 {
0518 compatible = "zii,rave-sp-eeprom";
0519 reg = <0xa4 0x4000>;
0520 #address-cells = <1>;
0521 #size-cells = <1>;
0522 zii,eeprom-name = "main-eeprom";
0523 };
0524 };
0525 };
0526
0527 &usb3_phy0 {
0528 vbus-supply = <&ucs1002>;
0529 status = "okay";
0530 };
0531
0532 &usb_dwc3_0 {
0533 dr_mode = "host";
0534 maximum-speed = "high-speed";
0535 status = "okay";
0536 };
0537
0538 &usb3_phy1 {
0539 vbus-supply = <®_5p0_main>;
0540 status = "okay";
0541 };
0542
0543 &usb_dwc3_1 {
0544 dr_mode = "host";
0545 maximum-speed = "high-speed";
0546 status = "okay";
0547 };
0548
0549 &pcie0 {
0550 pinctrl-names = "default";
0551 pinctrl-0 = <&pinctrl_pcie0>;
0552 reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
0553 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
0554 <&clk IMX8MQ_CLK_PCIE1_AUX>,
0555 <&clk IMX8MQ_CLK_PCIE1_PHY>,
0556 <&pcie0_refclk>;
0557 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0558 vph-supply = <&vgen5_reg>;
0559 status = "okay";
0560 };
0561
0562 &pcie1 {
0563 pinctrl-names = "default";
0564 pinctrl-0 = <&pinctrl_pcie1>;
0565 reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
0566 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
0567 <&clk IMX8MQ_CLK_PCIE2_AUX>,
0568 <&clk IMX8MQ_CLK_PCIE2_PHY>,
0569 <&pcie1_refclk>;
0570 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0571 vph-supply = <&vgen5_reg>;
0572 status = "okay";
0573 };
0574
0575 &pgc_gpu {
0576 power-supply = <&sw1a_reg>;
0577 };
0578
0579 &pgc_vpu {
0580 power-supply = <&sw1c_reg>;
0581 };
0582
0583 &usdhc1 {
0584 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0585 assigned-clock-rates = <400000000>;
0586 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0587 pinctrl-0 = <&pinctrl_usdhc1>;
0588 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0589 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0590 vqmmc-supply = <&sw4_reg>;
0591 bus-width = <8>;
0592 non-removable;
0593 no-sd;
0594 no-sdio;
0595 status = "okay";
0596 };
0597
0598 &usdhc2 {
0599 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
0600 assigned-clock-rates = <200000000>;
0601 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0602 pinctrl-0 = <&pinctrl_usdhc2>;
0603 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0604 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0605 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0606 vmmc-supply = <®_usdhc2_vmmc>;
0607 status = "okay";
0608 };
0609
0610 &snvs_rtc {
0611 status = "disabled";
0612 };
0613
0614 &iomuxc {
0615 pinctrl_accel: accelgrp {
0616 fsl,pins = <
0617 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
0618 >;
0619 };
0620
0621 pinctrl_codec1: dac1grp {
0622 fsl,pins = <
0623 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41
0624 >;
0625 };
0626
0627 pinctrl_fec1: fec1grp {
0628 fsl,pins = <
0629 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0630 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0631 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0632 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0633 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0634 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0635 MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
0636 MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
0637 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0638 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0639 >;
0640 };
0641
0642 pinctrl_fec1_phy_reset: fec1phyresetgrp {
0643 fsl,pins = <
0644 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
0645 >;
0646 };
0647
0648 pinctrl_gpio3_hog: gpio3hoggrp {
0649 fsl,pins = <
0650 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
0651 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
0652 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
0653 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
0654 >;
0655 };
0656
0657 pinctrl_i2c1: i2c1grp {
0658 fsl,pins = <
0659 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
0660 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000a2
0661 >;
0662 };
0663
0664 pinctrl_i2c2: i2c2grp {
0665 fsl,pins = <
0666 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000022
0667 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000a2
0668 >;
0669 };
0670
0671 pinctrl_i2c3: i2c3grp {
0672 fsl,pins = <
0673 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
0674 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000a2
0675 >;
0676 };
0677
0678 pinctrl_i2c4: i2c4grp {
0679 fsl,pins = <
0680 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
0681 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000a2
0682 >;
0683 };
0684
0685 pinctrl_mdio_bitbang: bitbangmdiogrp {
0686 fsl,pins = <
0687 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
0688 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
0689 >;
0690 };
0691
0692 pinctrl_pcie0: pcie0grp {
0693 fsl,pins = <
0694 MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
0695 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
0696 >;
0697 };
0698
0699 pinctrl_pcie1: pcie1grp {
0700 fsl,pins = <
0701 MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
0702 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
0703 >;
0704 };
0705
0706 pinctrl_reg_arm: regarmgrp {
0707 fsl,pins = <
0708 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
0709 >;
0710 };
0711
0712 pinctrl_reg_usdhc2: regusdhc2grp {
0713 fsl,pins = <
0714 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0715 >;
0716 };
0717
0718 pinctrl_sai2: sai2grp {
0719 fsl,pins = <
0720 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
0721 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
0722 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
0723 >;
0724 };
0725
0726 pinctrl_switch_irq: switchgrp {
0727 fsl,pins = <
0728 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
0729 >;
0730 };
0731
0732 pinctrl_tpa1: tpa6130-1grp {
0733 fsl,pins = <
0734 MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x41
0735 >;
0736 };
0737
0738 pinctrl_tpa2: tpa6130-2grp {
0739 fsl,pins = <
0740 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
0741 >;
0742 };
0743
0744 pinctrl_ts: tsgrp {
0745 fsl,pins = <
0746 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
0747 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
0748 >;
0749 };
0750
0751 pinctrl_uart1: uart1grp {
0752 fsl,pins = <
0753 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0754 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0755 >;
0756 };
0757
0758 pinctrl_uart2: uart2grp {
0759 fsl,pins = <
0760 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
0761 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
0762 >;
0763 };
0764
0765 pinctrl_ucs1002: ucs1002grp {
0766 fsl,pins = <
0767 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41
0768 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41
0769 >;
0770 };
0771
0772 pinctrl_usbhub: usbhubgrp {
0773 fsl,pins = <
0774 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
0775 >;
0776 };
0777
0778 pinctrl_usdhc1: usdhc1grp {
0779 fsl,pins = <
0780 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0781 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0782 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0783 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0784 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0785 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0786 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0787 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0788 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0789 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0790 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
0791 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0792 >;
0793 };
0794
0795 pinctrl_usdhc1_100mhz: usdhc1-100grp {
0796 fsl,pins = <
0797 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0798 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0799 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0800 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0801 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0802 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0803 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0804 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0805 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0806 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0807 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
0808 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0809 >;
0810 };
0811
0812 pinctrl_usdhc1_200mhz: usdhc1-200grp {
0813 fsl,pins = <
0814 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0815 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0816 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0817 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0818 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0819 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0820 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0821 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0822 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0823 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0824 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
0825 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0826 >;
0827 };
0828
0829 pinctrl_usdhc2: usdhc2grp {
0830 fsl,pins = <
0831 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
0832 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
0833 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
0834 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
0835 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
0836 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
0837 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0838 >;
0839 };
0840
0841 pinctrl_usdhc2_100mhz: usdhc2-100grp {
0842 fsl,pins = <
0843 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
0844 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
0845 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
0846 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
0847 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
0848 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
0849 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0850 >;
0851 };
0852
0853 pinctrl_usdhc2_200mhz: usdhc2-200grp {
0854 fsl,pins = <
0855 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
0856 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
0857 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
0858 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
0859 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
0860 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
0861 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0862 >;
0863 };
0864 };
