0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mp.dtsi"
0009
0010 / {
0011 model = "NXP i.MX8MPlus EVK board";
0012 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
0013
0014 chosen {
0015 stdout-path = &uart2;
0016 };
0017
0018 gpio-leds {
0019 compatible = "gpio-leds";
0020 pinctrl-names = "default";
0021 pinctrl-0 = <&pinctrl_gpio_led>;
0022
0023 status {
0024 label = "yellow:status";
0025 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
0026 default-state = "on";
0027 };
0028 };
0029
0030 memory@40000000 {
0031 device_type = "memory";
0032 reg = <0x0 0x40000000 0 0xc0000000>,
0033 <0x1 0x00000000 0 0xc0000000>;
0034 };
0035
0036 reg_can1_stby: regulator-can1-stby {
0037 compatible = "regulator-fixed";
0038 regulator-name = "can1-stby";
0039 pinctrl-names = "default";
0040 pinctrl-0 = <&pinctrl_flexcan1_reg>;
0041 regulator-min-microvolt = <3300000>;
0042 regulator-max-microvolt = <3300000>;
0043 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0044 enable-active-high;
0045 };
0046
0047 reg_can2_stby: regulator-can2-stby {
0048 compatible = "regulator-fixed";
0049 regulator-name = "can2-stby";
0050 pinctrl-names = "default";
0051 pinctrl-0 = <&pinctrl_flexcan2_reg>;
0052 regulator-min-microvolt = <3300000>;
0053 regulator-max-microvolt = <3300000>;
0054 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
0055 enable-active-high;
0056 };
0057
0058 reg_usdhc2_vmmc: regulator-usdhc2 {
0059 compatible = "regulator-fixed";
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0062 regulator-name = "VSD_3V3";
0063 regulator-min-microvolt = <3300000>;
0064 regulator-max-microvolt = <3300000>;
0065 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0066 enable-active-high;
0067 };
0068 };
0069
0070 &A53_0 {
0071 cpu-supply = <®_arm>;
0072 };
0073
0074 &A53_1 {
0075 cpu-supply = <®_arm>;
0076 };
0077
0078 &A53_2 {
0079 cpu-supply = <®_arm>;
0080 };
0081
0082 &A53_3 {
0083 cpu-supply = <®_arm>;
0084 };
0085
0086 &eqos {
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&pinctrl_eqos>;
0089 phy-mode = "rgmii-id";
0090 phy-handle = <ðphy0>;
0091 snps,force_thresh_dma_mode;
0092 snps,mtl-tx-config = <&mtl_tx_setup>;
0093 snps,mtl-rx-config = <&mtl_rx_setup>;
0094 status = "okay";
0095
0096 mdio {
0097 compatible = "snps,dwmac-mdio";
0098 #address-cells = <1>;
0099 #size-cells = <0>;
0100
0101 ethphy0: ethernet-phy@1 {
0102 compatible = "ethernet-phy-ieee802.3-c22";
0103 reg = <1>;
0104 eee-broken-1000t;
0105 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0106 reset-assert-us = <10000>;
0107 reset-deassert-us = <80000>;
0108 realtek,clkout-disable;
0109 };
0110 };
0111
0112 mtl_tx_setup: tx-queues-config {
0113 snps,tx-queues-to-use = <5>;
0114 snps,tx-sched-sp;
0115
0116 queue0 {
0117 snps,dcb-algorithm;
0118 snps,priority = <0x1>;
0119 };
0120
0121 queue1 {
0122 snps,dcb-algorithm;
0123 snps,priority = <0x2>;
0124 };
0125
0126 queue2 {
0127 snps,dcb-algorithm;
0128 snps,priority = <0x4>;
0129 };
0130
0131 queue3 {
0132 snps,dcb-algorithm;
0133 snps,priority = <0x8>;
0134 };
0135
0136 queue4 {
0137 snps,dcb-algorithm;
0138 snps,priority = <0xf0>;
0139 };
0140 };
0141
0142 mtl_rx_setup: rx-queues-config {
0143 snps,rx-queues-to-use = <5>;
0144 snps,rx-sched-sp;
0145
0146 queue0 {
0147 snps,dcb-algorithm;
0148 snps,priority = <0x1>;
0149 snps,map-to-dma-channel = <0>;
0150 };
0151
0152 queue1 {
0153 snps,dcb-algorithm;
0154 snps,priority = <0x2>;
0155 snps,map-to-dma-channel = <1>;
0156 };
0157
0158 queue2 {
0159 snps,dcb-algorithm;
0160 snps,priority = <0x4>;
0161 snps,map-to-dma-channel = <2>;
0162 };
0163
0164 queue3 {
0165 snps,dcb-algorithm;
0166 snps,priority = <0x8>;
0167 snps,map-to-dma-channel = <3>;
0168 };
0169
0170 queue4 {
0171 snps,dcb-algorithm;
0172 snps,priority = <0xf0>;
0173 snps,map-to-dma-channel = <4>;
0174 };
0175 };
0176 };
0177
0178 &fec {
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_fec>;
0181 phy-mode = "rgmii-id";
0182 phy-handle = <ðphy1>;
0183 fsl,magic-packet;
0184 status = "okay";
0185
0186 mdio {
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189
0190 ethphy1: ethernet-phy@1 {
0191 compatible = "ethernet-phy-ieee802.3-c22";
0192 reg = <1>;
0193 eee-broken-1000t;
0194 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
0195 reset-assert-us = <10000>;
0196 reset-deassert-us = <80000>;
0197 realtek,clkout-disable;
0198 };
0199 };
0200 };
0201
0202 &flexcan1 {
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_flexcan1>;
0205 xceiver-supply = <®_can1_stby>;
0206 status = "okay";
0207 };
0208
0209 &flexcan2 {
0210 pinctrl-names = "default";
0211 pinctrl-0 = <&pinctrl_flexcan2>;
0212 xceiver-supply = <®_can2_stby>;
0213 status = "disabled";/* can2 pin conflict with pdm */
0214 };
0215
0216 &i2c1 {
0217 clock-frequency = <400000>;
0218 pinctrl-names = "default";
0219 pinctrl-0 = <&pinctrl_i2c1>;
0220 status = "okay";
0221
0222 pmic@25 {
0223 compatible = "nxp,pca9450c";
0224 reg = <0x25>;
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_pmic>;
0227 interrupt-parent = <&gpio1>;
0228 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0229
0230 regulators {
0231 BUCK1 {
0232 regulator-name = "BUCK1";
0233 regulator-min-microvolt = <720000>;
0234 regulator-max-microvolt = <1000000>;
0235 regulator-boot-on;
0236 regulator-always-on;
0237 regulator-ramp-delay = <3125>;
0238 };
0239
0240 reg_arm: BUCK2 {
0241 regulator-name = "BUCK2";
0242 regulator-min-microvolt = <720000>;
0243 regulator-max-microvolt = <1025000>;
0244 regulator-boot-on;
0245 regulator-always-on;
0246 regulator-ramp-delay = <3125>;
0247 nxp,dvs-run-voltage = <950000>;
0248 nxp,dvs-standby-voltage = <850000>;
0249 };
0250
0251 BUCK4 {
0252 regulator-name = "BUCK4";
0253 regulator-min-microvolt = <3000000>;
0254 regulator-max-microvolt = <3600000>;
0255 regulator-boot-on;
0256 regulator-always-on;
0257 };
0258
0259 BUCK5 {
0260 regulator-name = "BUCK5";
0261 regulator-min-microvolt = <1650000>;
0262 regulator-max-microvolt = <1950000>;
0263 regulator-boot-on;
0264 regulator-always-on;
0265 };
0266
0267 BUCK6 {
0268 regulator-name = "BUCK6";
0269 regulator-min-microvolt = <1045000>;
0270 regulator-max-microvolt = <1155000>;
0271 regulator-boot-on;
0272 regulator-always-on;
0273 };
0274
0275 LDO1 {
0276 regulator-name = "LDO1";
0277 regulator-min-microvolt = <1650000>;
0278 regulator-max-microvolt = <1950000>;
0279 regulator-boot-on;
0280 regulator-always-on;
0281 };
0282
0283 LDO3 {
0284 regulator-name = "LDO3";
0285 regulator-min-microvolt = <1710000>;
0286 regulator-max-microvolt = <1890000>;
0287 regulator-boot-on;
0288 regulator-always-on;
0289 };
0290
0291 LDO5 {
0292 regulator-name = "LDO5";
0293 regulator-min-microvolt = <1800000>;
0294 regulator-max-microvolt = <3300000>;
0295 regulator-boot-on;
0296 regulator-always-on;
0297 };
0298 };
0299 };
0300 };
0301
0302 &i2c3 {
0303 clock-frequency = <400000>;
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&pinctrl_i2c3>;
0306 status = "okay";
0307
0308 pca6416: gpio@20 {
0309 compatible = "ti,tca6416";
0310 reg = <0x20>;
0311 gpio-controller;
0312 #gpio-cells = <2>;
0313 interrupt-controller;
0314 #interrupt-cells = <2>;
0315 pinctrl-names = "default";
0316 pinctrl-0 = <&pinctrl_pca6416_int>;
0317 interrupt-parent = <&gpio1>;
0318 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0319 gpio-line-names = "EXT_PWREN1",
0320 "EXT_PWREN2",
0321 "CAN1/I2C5_SEL",
0322 "PDM/CAN2_SEL",
0323 "FAN_EN",
0324 "PWR_MEAS_IO1",
0325 "PWR_MEAS_IO2",
0326 "EXP_P0_7",
0327 "EXP_P1_0",
0328 "EXP_P1_1",
0329 "EXP_P1_2",
0330 "EXP_P1_3",
0331 "EXP_P1_4",
0332 "EXP_P1_5",
0333 "EXP_P1_6",
0334 "EXP_P1_7";
0335 };
0336 };
0337
0338 /* I2C on expansion connector J22. */
0339 &i2c5 {
0340 clock-frequency = <100000>; /* Lower clock speed for external bus. */
0341 pinctrl-names = "default";
0342 pinctrl-0 = <&pinctrl_i2c5>;
0343 status = "disabled"; /* can1 pins conflict with i2c5 */
0344
0345 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
0346 * LOW: CAN1 (default, pull-down)
0347 * HIGH: I2C5
0348 * You need to set it to high to enable I2C5 (for example, add gpio-hog
0349 * in pca6416 node).
0350 */
0351 };
0352
0353 &snvs_pwrkey {
0354 status = "okay";
0355 };
0356
0357 &uart2 {
0358 /* console */
0359 pinctrl-names = "default";
0360 pinctrl-0 = <&pinctrl_uart2>;
0361 status = "okay";
0362 };
0363
0364 &usb3_phy1 {
0365 status = "okay";
0366 };
0367
0368 &usb3_1 {
0369 status = "okay";
0370 };
0371
0372 &usb_dwc3_1 {
0373 pinctrl-names = "default";
0374 pinctrl-0 = <&pinctrl_usb1_vbus>;
0375 dr_mode = "host";
0376 status = "okay";
0377 };
0378
0379 &usdhc2 {
0380 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
0381 assigned-clock-rates = <400000000>;
0382 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0383 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0384 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0385 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0386 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0387 vmmc-supply = <®_usdhc2_vmmc>;
0388 bus-width = <4>;
0389 status = "okay";
0390 };
0391
0392 &usdhc3 {
0393 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
0394 assigned-clock-rates = <400000000>;
0395 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0396 pinctrl-0 = <&pinctrl_usdhc3>;
0397 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0398 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0399 bus-width = <8>;
0400 non-removable;
0401 status = "okay";
0402 };
0403
0404 &wdog1 {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_wdog>;
0407 fsl,ext-reset-output;
0408 status = "okay";
0409 };
0410
0411 &iomuxc {
0412 pinctrl_eqos: eqosgrp {
0413 fsl,pins = <
0414 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
0415 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
0416 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
0417 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
0418 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
0419 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
0420 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
0421 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
0422 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
0423 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
0424 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
0425 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
0426 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
0427 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
0428 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
0429 >;
0430 };
0431
0432 pinctrl_fec: fecgrp {
0433 fsl,pins = <
0434 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
0435 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
0436 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
0437 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
0438 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
0439 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
0440 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
0441 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
0442 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
0443 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
0444 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
0445 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
0446 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
0447 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
0448 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
0449 >;
0450 };
0451
0452 pinctrl_flexcan1: flexcan1grp {
0453 fsl,pins = <
0454 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
0455 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
0456 >;
0457 };
0458
0459 pinctrl_flexcan2: flexcan2grp {
0460 fsl,pins = <
0461 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
0462 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
0463 >;
0464 };
0465
0466 pinctrl_flexcan1_reg: flexcan1reggrp {
0467 fsl,pins = <
0468 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
0469 >;
0470 };
0471
0472 pinctrl_flexcan2_reg: flexcan2reggrp {
0473 fsl,pins = <
0474 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
0475 >;
0476 };
0477
0478 pinctrl_gpio_led: gpioledgrp {
0479 fsl,pins = <
0480 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
0481 >;
0482 };
0483
0484 pinctrl_i2c1: i2c1grp {
0485 fsl,pins = <
0486 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
0487 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
0488 >;
0489 };
0490
0491 pinctrl_i2c3: i2c3grp {
0492 fsl,pins = <
0493 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
0494 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
0495 >;
0496 };
0497
0498 pinctrl_i2c5: i2c5grp {
0499 fsl,pins = <
0500 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
0501 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
0502 >;
0503 };
0504
0505 pinctrl_pmic: pmicgrp {
0506 fsl,pins = <
0507 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
0508 >;
0509 };
0510
0511 pinctrl_pca6416_int: pca6416_int_grp {
0512 fsl,pins = <
0513 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
0514 >;
0515 };
0516
0517 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0518 fsl,pins = <
0519 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
0520 >;
0521 };
0522
0523 pinctrl_uart2: uart2grp {
0524 fsl,pins = <
0525 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
0526 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
0527 >;
0528 };
0529
0530 pinctrl_usb1_vbus: usb1grp {
0531 fsl,pins = <
0532 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
0533 >;
0534 };
0535
0536 pinctrl_usdhc2: usdhc2grp {
0537 fsl,pins = <
0538 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
0539 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
0540 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
0541 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
0542 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
0543 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
0544 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0545 >;
0546 };
0547
0548 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0549 fsl,pins = <
0550 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
0551 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
0552 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
0553 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
0554 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
0555 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
0556 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0557 >;
0558 };
0559
0560 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0561 fsl,pins = <
0562 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
0563 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
0564 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
0565 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
0566 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
0567 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
0568 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0569 >;
0570 };
0571
0572 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0573 fsl,pins = <
0574 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
0575 >;
0576 };
0577
0578 pinctrl_usdhc3: usdhc3grp {
0579 fsl,pins = <
0580 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
0581 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
0582 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
0583 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
0584 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
0585 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
0586 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
0587 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
0588 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
0589 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
0590 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
0591 >;
0592 };
0593
0594 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0595 fsl,pins = <
0596 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
0597 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
0598 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
0599 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
0600 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
0601 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
0602 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
0603 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
0604 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
0605 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
0606 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
0607 >;
0608 };
0609
0610 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0611 fsl,pins = <
0612 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
0613 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
0614 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
0615 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
0616 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
0617 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
0618 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
0619 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
0620 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
0621 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
0622 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
0623 >;
0624 };
0625
0626 pinctrl_wdog: wdoggrp {
0627 fsl,pins = <
0628 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
0629 >;
0630 };
0631 };
