0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2021 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/linux-event-codes.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/net/ti-dp83867.h>
0012
0013 #include "imx8mn.dtsi"
0014
0015 / {
0016 model = "Gateworks Venice GW7902 i.MX8MN board";
0017 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
0018
0019 aliases {
0020 usb0 = &usbotg1;
0021 };
0022
0023 chosen {
0024 stdout-path = &uart2;
0025 };
0026
0027 memory@40000000 {
0028 device_type = "memory";
0029 reg = <0x0 0x40000000 0 0x80000000>;
0030 };
0031
0032 can20m: can20m {
0033 compatible = "fixed-clock";
0034 #clock-cells = <0>;
0035 clock-frequency = <20000000>;
0036 clock-output-names = "can20m";
0037 };
0038
0039 gpio-keys {
0040 compatible = "gpio-keys";
0041
0042 key-user-pb {
0043 label = "user_pb";
0044 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0045 linux,code = <BTN_0>;
0046 };
0047
0048 key-user-pb1x {
0049 label = "user_pb1x";
0050 linux,code = <BTN_1>;
0051 interrupt-parent = <&gsc>;
0052 interrupts = <0>;
0053 };
0054
0055 key-erased {
0056 label = "key_erased";
0057 linux,code = <BTN_2>;
0058 interrupt-parent = <&gsc>;
0059 interrupts = <1>;
0060 };
0061
0062 key-eeprom-wp {
0063 label = "eeprom_wp";
0064 linux,code = <BTN_3>;
0065 interrupt-parent = <&gsc>;
0066 interrupts = <2>;
0067 };
0068
0069 key-tamper {
0070 label = "tamper";
0071 linux,code = <BTN_4>;
0072 interrupt-parent = <&gsc>;
0073 interrupts = <5>;
0074 };
0075
0076 switch-hold {
0077 label = "switch_hold";
0078 linux,code = <BTN_5>;
0079 interrupt-parent = <&gsc>;
0080 interrupts = <7>;
0081 };
0082 };
0083
0084 led-controller {
0085 compatible = "gpio-leds";
0086 pinctrl-names = "default";
0087 pinctrl-0 = <&pinctrl_gpio_leds>;
0088
0089 led-0 {
0090 function = LED_FUNCTION_STATUS;
0091 color = <LED_COLOR_ID_GREEN>;
0092 label = "panel1";
0093 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
0094 default-state = "off";
0095 };
0096
0097 led-1 {
0098 function = LED_FUNCTION_STATUS;
0099 color = <LED_COLOR_ID_GREEN>;
0100 label = "panel2";
0101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
0102 default-state = "off";
0103 };
0104
0105 led-2 {
0106 function = LED_FUNCTION_STATUS;
0107 color = <LED_COLOR_ID_GREEN>;
0108 label = "panel3";
0109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
0110 default-state = "off";
0111 };
0112
0113 led-3 {
0114 function = LED_FUNCTION_STATUS;
0115 color = <LED_COLOR_ID_GREEN>;
0116 label = "panel4";
0117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
0118 default-state = "off";
0119 };
0120
0121 led-4 {
0122 function = LED_FUNCTION_STATUS;
0123 color = <LED_COLOR_ID_GREEN>;
0124 label = "panel5";
0125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
0126 default-state = "off";
0127 };
0128 };
0129
0130 pps {
0131 compatible = "pps-gpio";
0132 pinctrl-names = "default";
0133 pinctrl-0 = <&pinctrl_pps>;
0134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
0135 status = "okay";
0136 };
0137
0138 reg_3p3v: regulator-3p3v {
0139 compatible = "regulator-fixed";
0140 regulator-name = "3P3V";
0141 regulator-min-microvolt = <3300000>;
0142 regulator-max-microvolt = <3300000>;
0143 regulator-always-on;
0144 };
0145
0146 reg_usb1_vbus: regulator-usb1 {
0147 compatible = "regulator-fixed";
0148 pinctrl-names = "default";
0149 pinctrl-0 = <&pinctrl_reg_usb1>;
0150 regulator-name = "usb_usb1_vbus";
0151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
0152 enable-active-high;
0153 regulator-min-microvolt = <5000000>;
0154 regulator-max-microvolt = <5000000>;
0155 };
0156
0157 reg_wifi: regulator-wifi {
0158 compatible = "regulator-fixed";
0159 pinctrl-names = "default";
0160 pinctrl-0 = <&pinctrl_reg_wl>;
0161 regulator-name = "wifi";
0162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0163 enable-active-high;
0164 startup-delay-us = <100>;
0165 regulator-min-microvolt = <3300000>;
0166 regulator-max-microvolt = <3300000>;
0167 };
0168 };
0169
0170 &A53_0 {
0171 cpu-supply = <&buck2>;
0172 };
0173
0174 &A53_1 {
0175 cpu-supply = <&buck2>;
0176 };
0177
0178 &A53_2 {
0179 cpu-supply = <&buck2>;
0180 };
0181
0182 &A53_3 {
0183 cpu-supply = <&buck2>;
0184 };
0185
0186 &ddrc {
0187 operating-points-v2 = <&ddrc_opp_table>;
0188
0189 ddrc_opp_table: opp-table {
0190 compatible = "operating-points-v2";
0191
0192 opp-25M {
0193 opp-hz = /bits/ 64 <25000000>;
0194 };
0195
0196 opp-100M {
0197 opp-hz = /bits/ 64 <100000000>;
0198 };
0199
0200 opp-750M {
0201 opp-hz = /bits/ 64 <750000000>;
0202 };
0203 };
0204 };
0205
0206 &ecspi1 {
0207 pinctrl-names = "default";
0208 pinctrl-0 = <&pinctrl_spi1>;
0209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0210 status = "okay";
0211
0212 can@0 {
0213 compatible = "microchip,mcp2515";
0214 reg = <0>;
0215 clocks = <&can20m>;
0216 oscillator-frequency = <20000000>;
0217 interrupt-parent = <&gpio2>;
0218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0219 spi-max-frequency = <10000000>;
0220 };
0221 };
0222
0223 &disp_blk_ctrl {
0224 status = "disabled";
0225 };
0226
0227 /* off-board header */
0228 &ecspi2 {
0229 pinctrl-names = "default";
0230 pinctrl-0 = <&pinctrl_spi2>;
0231 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0232 status = "okay";
0233 };
0234
0235 &fec1 {
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_fec1>;
0238 phy-mode = "rgmii-id";
0239 phy-handle = <ðphy0>;
0240 local-mac-address = [00 00 00 00 00 00];
0241 status = "okay";
0242
0243 mdio {
0244 #address-cells = <1>;
0245 #size-cells = <0>;
0246
0247 ethphy0: ethernet-phy@0 {
0248 compatible = "ethernet-phy-ieee802.3-c22";
0249 reg = <0>;
0250 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0251 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0252 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0253 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0254 };
0255 };
0256 };
0257
0258 &gpio1 {
0259 gpio-line-names = "", "", "", "", "", "", "", "",
0260 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
0261 "", "", "", "", "", "", "", "",
0262 "", "", "", "", "", "", "", "";
0263 };
0264
0265 &gpio2 {
0266 gpio-line-names = "", "", "", "", "", "", "", "",
0267 "uart2_en#", "", "", "", "", "", "", "",
0268 "", "", "", "", "", "", "", "",
0269 "", "", "", "", "", "", "", "";
0270 };
0271
0272 &gpio3 {
0273 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
0274 "", "", "", "", "", "", "", "",
0275 "", "", "", "", "", "", "", "",
0276 "", "", "", "", "", "", "", "";
0277 };
0278
0279 &gpio4 {
0280 gpio-line-names = "", "", "", "", "", "", "", "",
0281 "", "", "", "", "", "", "", "",
0282 "", "", "", "", "", "app_gpio1", "", "uart1_rs485",
0283 "", "uart1_term", "uart1_half", "app_gpio2",
0284 "mipi_gpio1", "", "", "";
0285 };
0286
0287 &gpio5 {
0288 gpio-line-names = "", "", "", "mipi_gpio4",
0289 "mipi_gpio3", "mipi_gpio2", "", "",
0290 "", "", "", "", "", "", "", "",
0291 "", "", "", "", "", "", "", "",
0292 "", "", "", "", "", "", "", "";
0293 };
0294
0295 &gpu {
0296 status = "disabled";
0297 };
0298
0299 &i2c1 {
0300 clock-frequency = <100000>;
0301 pinctrl-names = "default";
0302 pinctrl-0 = <&pinctrl_i2c1>;
0303 status = "okay";
0304
0305 gsc: gsc@20 {
0306 compatible = "gw,gsc";
0307 reg = <0x20>;
0308 pinctrl-0 = <&pinctrl_gsc>;
0309 interrupt-parent = <&gpio2>;
0310 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
0311 interrupt-controller;
0312 #interrupt-cells = <1>;
0313
0314 adc {
0315 compatible = "gw,gsc-adc";
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318
0319 channel@6 {
0320 gw,mode = <0>;
0321 reg = <0x06>;
0322 label = "temp";
0323 };
0324
0325 channel@8 {
0326 gw,mode = <1>;
0327 reg = <0x08>;
0328 label = "vdd_bat";
0329 };
0330
0331 channel@82 {
0332 gw,mode = <2>;
0333 reg = <0x82>;
0334 label = "vin";
0335 gw,voltage-divider-ohms = <22100 1000>;
0336 gw,voltage-offset-microvolt = <700000>;
0337 };
0338
0339 channel@84 {
0340 gw,mode = <2>;
0341 reg = <0x84>;
0342 label = "vin_4p0";
0343 gw,voltage-divider-ohms = <10000 10000>;
0344 };
0345
0346 channel@86 {
0347 gw,mode = <2>;
0348 reg = <0x86>;
0349 label = "vdd_3p3";
0350 gw,voltage-divider-ohms = <10000 10000>;
0351 };
0352
0353 channel@88 {
0354 gw,mode = <2>;
0355 reg = <0x88>;
0356 label = "vdd_0p9";
0357 };
0358
0359 channel@8c {
0360 gw,mode = <2>;
0361 reg = <0x8c>;
0362 label = "vdd_soc";
0363 };
0364
0365 channel@8e {
0366 gw,mode = <2>;
0367 reg = <0x8e>;
0368 label = "vdd_arm";
0369 };
0370
0371 channel@90 {
0372 gw,mode = <2>;
0373 reg = <0x90>;
0374 label = "vdd_1p8";
0375 };
0376
0377 channel@92 {
0378 gw,mode = <2>;
0379 reg = <0x92>;
0380 label = "vdd_dram";
0381 };
0382
0383 channel@98 {
0384 gw,mode = <2>;
0385 reg = <0x98>;
0386 label = "vdd_1p0";
0387 };
0388
0389 channel@9a {
0390 gw,mode = <2>;
0391 reg = <0x9a>;
0392 label = "vdd_2p5";
0393 gw,voltage-divider-ohms = <10000 10000>;
0394 };
0395
0396 channel@9c {
0397 gw,mode = <2>;
0398 reg = <0x9c>;
0399 label = "vdd_5p0";
0400 gw,voltage-divider-ohms = <10000 10000>;
0401 };
0402
0403 channel@a2 {
0404 gw,mode = <2>;
0405 reg = <0xa2>;
0406 label = "vdd_gsc";
0407 gw,voltage-divider-ohms = <10000 10000>;
0408 };
0409 };
0410 };
0411
0412 gpio: gpio@23 {
0413 compatible = "nxp,pca9555";
0414 reg = <0x23>;
0415 gpio-controller;
0416 #gpio-cells = <2>;
0417 interrupt-parent = <&gsc>;
0418 interrupts = <4>;
0419 };
0420
0421 pmic@4b {
0422 compatible = "rohm,bd71847";
0423 reg = <0x4b>;
0424 pinctrl-names = "default";
0425 pinctrl-0 = <&pinctrl_pmic>;
0426 interrupt-parent = <&gpio3>;
0427 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0428 rohm,reset-snvs-powered;
0429 #clock-cells = <0>;
0430 clocks = <&osc_32k 0>;
0431 clock-output-names = "clk-32k-out";
0432
0433 regulators {
0434 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
0435 BUCK1 {
0436 regulator-name = "buck1";
0437 regulator-min-microvolt = <700000>;
0438 regulator-max-microvolt = <1300000>;
0439 regulator-boot-on;
0440 regulator-always-on;
0441 regulator-ramp-delay = <1250>;
0442 };
0443
0444 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
0445 buck2: BUCK2 {
0446 regulator-name = "buck2";
0447 regulator-min-microvolt = <700000>;
0448 regulator-max-microvolt = <1300000>;
0449 regulator-boot-on;
0450 regulator-always-on;
0451 regulator-ramp-delay = <1250>;
0452 rohm,dvs-run-voltage = <1000000>;
0453 rohm,dvs-idle-voltage = <900000>;
0454 };
0455
0456 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
0457 BUCK3 {
0458 regulator-name = "buck3";
0459 regulator-min-microvolt = <700000>;
0460 regulator-max-microvolt = <1350000>;
0461 regulator-boot-on;
0462 regulator-always-on;
0463 };
0464
0465 /* vdd_3p3 */
0466 BUCK4 {
0467 regulator-name = "buck4";
0468 regulator-min-microvolt = <3000000>;
0469 regulator-max-microvolt = <3300000>;
0470 regulator-boot-on;
0471 regulator-always-on;
0472 };
0473
0474 /* vdd_1p8 */
0475 BUCK5 {
0476 regulator-name = "buck5";
0477 regulator-min-microvolt = <1605000>;
0478 regulator-max-microvolt = <1995000>;
0479 regulator-boot-on;
0480 regulator-always-on;
0481 };
0482
0483 /* vdd_dram */
0484 BUCK6 {
0485 regulator-name = "buck6";
0486 regulator-min-microvolt = <800000>;
0487 regulator-max-microvolt = <1400000>;
0488 regulator-boot-on;
0489 regulator-always-on;
0490 };
0491
0492 /* nvcc_snvs_1p8 */
0493 LDO1 {
0494 regulator-name = "ldo1";
0495 regulator-min-microvolt = <1600000>;
0496 regulator-max-microvolt = <1900000>;
0497 regulator-boot-on;
0498 regulator-always-on;
0499 };
0500
0501 /* vdd_snvs_0p8 */
0502 LDO2 {
0503 regulator-name = "ldo2";
0504 regulator-min-microvolt = <800000>;
0505 regulator-max-microvolt = <900000>;
0506 regulator-boot-on;
0507 regulator-always-on;
0508 };
0509
0510 /* vdda_1p8 */
0511 LDO3 {
0512 regulator-name = "ldo3";
0513 regulator-min-microvolt = <1800000>;
0514 regulator-max-microvolt = <3300000>;
0515 regulator-boot-on;
0516 regulator-always-on;
0517 };
0518
0519 LDO4 {
0520 regulator-name = "ldo4";
0521 regulator-min-microvolt = <900000>;
0522 regulator-max-microvolt = <1800000>;
0523 regulator-boot-on;
0524 regulator-always-on;
0525 };
0526
0527 LDO6 {
0528 regulator-name = "ldo6";
0529 regulator-min-microvolt = <900000>;
0530 regulator-max-microvolt = <1800000>;
0531 regulator-boot-on;
0532 regulator-always-on;
0533 };
0534 };
0535 };
0536
0537 eeprom@50 {
0538 compatible = "atmel,24c02";
0539 reg = <0x50>;
0540 pagesize = <16>;
0541 };
0542
0543 eeprom@51 {
0544 compatible = "atmel,24c02";
0545 reg = <0x51>;
0546 pagesize = <16>;
0547 };
0548
0549 eeprom@52 {
0550 compatible = "atmel,24c02";
0551 reg = <0x52>;
0552 pagesize = <16>;
0553 };
0554
0555 eeprom@53 {
0556 compatible = "atmel,24c02";
0557 reg = <0x53>;
0558 pagesize = <16>;
0559 };
0560
0561 rtc@68 {
0562 compatible = "dallas,ds1672";
0563 reg = <0x68>;
0564 };
0565 };
0566
0567 &i2c2 {
0568 clock-frequency = <400000>;
0569 pinctrl-names = "default";
0570 pinctrl-0 = <&pinctrl_i2c2>;
0571 status = "okay";
0572
0573 accelerometer@19 {
0574 compatible = "st,lis2de12";
0575 pinctrl-names = "default";
0576 pinctrl-0 = <&pinctrl_accel>;
0577 reg = <0x19>;
0578 st,drdy-int-pin = <1>;
0579 interrupt-parent = <&gpio1>;
0580 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
0581 interrupt-names = "INT1";
0582 };
0583 };
0584
0585 /* off-board header */
0586 &i2c3 {
0587 clock-frequency = <400000>;
0588 pinctrl-names = "default";
0589 pinctrl-0 = <&pinctrl_i2c3>;
0590 status = "okay";
0591 };
0592
0593 /* off-board header */
0594 &i2c4 {
0595 clock-frequency = <400000>;
0596 pinctrl-names = "default";
0597 pinctrl-0 = <&pinctrl_i2c4>;
0598 status = "okay";
0599 };
0600
0601 &pgc_gpumix {
0602 status = "disabled";
0603 };
0604
0605 /* off-board header */
0606 &sai3 {
0607 pinctrl-names = "default";
0608 pinctrl-0 = <&pinctrl_sai3>;
0609 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
0610 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
0611 assigned-clock-rates = <24576000>;
0612 status = "okay";
0613 };
0614
0615 /* RS232/RS485/RS422 selectable */
0616 &uart1 {
0617 pinctrl-names = "default";
0618 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
0619 status = "okay";
0620 };
0621
0622 /* RS232 console */
0623 &uart2 {
0624 pinctrl-names = "default";
0625 pinctrl-0 = <&pinctrl_uart2>;
0626 status = "okay";
0627 };
0628
0629 /* bluetooth HCI */
0630 &uart3 {
0631 pinctrl-names = "default";
0632 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
0633 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
0634 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
0635 uart-has-rtscts;
0636 status = "okay";
0637
0638 bluetooth {
0639 compatible = "brcm,bcm4330-bt";
0640 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
0641 };
0642 };
0643
0644 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
0645 &uart4 {
0646 pinctrl-names = "default";
0647 pinctrl-0 = <&pinctrl_uart4>;
0648 status = "okay";
0649 };
0650
0651 &usbotg1 {
0652 dr_mode = "host";
0653 vbus-supply = <®_usb1_vbus>;
0654 disable-over-current;
0655 status = "okay";
0656 };
0657
0658 /* SDIO WiFi */
0659 &usdhc2 {
0660 pinctrl-names = "default";
0661 pinctrl-0 = <&pinctrl_usdhc2>;
0662 bus-width = <4>;
0663 non-removable;
0664 vmmc-supply = <®_wifi>;
0665 status = "okay";
0666 };
0667
0668 /* eMMC */
0669 &usdhc3 {
0670 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0671 pinctrl-0 = <&pinctrl_usdhc3>;
0672 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0673 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0674 bus-width = <8>;
0675 non-removable;
0676 status = "okay";
0677 };
0678
0679 &wdog1 {
0680 pinctrl-names = "default";
0681 pinctrl-0 = <&pinctrl_wdog>;
0682 fsl,ext-reset-output;
0683 status = "okay";
0684 };
0685
0686 &iomuxc {
0687 pinctrl-names = "default";
0688 pinctrl-0 = <&pinctrl_hog>;
0689
0690 pinctrl_hog: hoggrp {
0691 fsl,pins = <
0692 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
0693 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
0694 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
0695 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
0696 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
0697 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
0698 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
0699 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
0700 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
0701 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
0702 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
0703 >;
0704 };
0705
0706 pinctrl_accel: accelgrp {
0707 fsl,pins = <
0708 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
0709 >;
0710 };
0711
0712 pinctrl_fec1: fec1grp {
0713 fsl,pins = <
0714 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0715 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0716 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0717 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0718 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0719 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0720 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0721 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0722 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0723 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0724 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0725 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0726 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0727 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0728 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
0729 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
0730 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
0731 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
0732 >;
0733 };
0734
0735 pinctrl_gsc: gscgrp {
0736 fsl,pins = <
0737 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
0738 >;
0739 };
0740
0741 pinctrl_i2c1: i2c1grp {
0742 fsl,pins = <
0743 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0744 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0745 >;
0746 };
0747
0748 pinctrl_i2c2: i2c2grp {
0749 fsl,pins = <
0750 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0751 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0752 >;
0753 };
0754
0755 pinctrl_i2c3: i2c3grp {
0756 fsl,pins = <
0757 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0758 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0759 >;
0760 };
0761
0762 pinctrl_i2c4: i2c4grp {
0763 fsl,pins = <
0764 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
0765 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
0766 >;
0767 };
0768
0769 pinctrl_gpio_leds: gpioledgrp {
0770 fsl,pins = <
0771 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
0772 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
0773 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
0774 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
0775 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
0776 >;
0777 };
0778
0779 pinctrl_pmic: pmicgrp {
0780 fsl,pins = <
0781 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
0782 >;
0783 };
0784
0785 pinctrl_pps: ppsgrp {
0786 fsl,pins = <
0787 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
0788 >;
0789 };
0790
0791 pinctrl_reg_wl: regwlgrp {
0792 fsl,pins = <
0793 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
0794 >;
0795 };
0796
0797 pinctrl_reg_usb1: regusb1grp {
0798 fsl,pins = <
0799 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
0800 >;
0801 };
0802
0803 pinctrl_sai3: sai3grp {
0804 fsl,pins = <
0805 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0806 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0807 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0808 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0809 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0810 >;
0811 };
0812
0813 pinctrl_spi1: spi1grp {
0814 fsl,pins = <
0815 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
0816 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
0817 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
0818 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
0819 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
0820 >;
0821 };
0822
0823 pinctrl_spi2: spi2grp {
0824 fsl,pins = <
0825 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
0826 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
0827 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
0828 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
0829 >;
0830 };
0831
0832 pinctrl_uart1: uart1grp {
0833 fsl,pins = <
0834 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0835 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0836 >;
0837 };
0838
0839 pinctrl_uart1_gpio: uart1gpiogrp {
0840 fsl,pins = <
0841 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
0842 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
0843 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
0844 >;
0845 };
0846
0847 pinctrl_uart2: uart2grp {
0848 fsl,pins = <
0849 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0850 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0851 >;
0852 };
0853
0854 pinctrl_uart3_gpio: uart3_gpiogrp {
0855 fsl,pins = <
0856 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
0857 >;
0858 };
0859
0860 pinctrl_uart3: uart3grp {
0861 fsl,pins = <
0862 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0863 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0864 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
0865 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
0866 >;
0867 };
0868
0869 pinctrl_uart4: uart4grp {
0870 fsl,pins = <
0871 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0872 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0873 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
0874 >;
0875 };
0876
0877 pinctrl_usdhc2: usdhc2grp {
0878 fsl,pins = <
0879 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0880 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0881 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0882 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0883 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0884 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0885 >;
0886 };
0887
0888 pinctrl_usdhc3: usdhc3grp {
0889 fsl,pins = <
0890 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0891 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0892 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0893 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0894 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0895 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0896 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0897 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0898 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0899 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0900 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0901 >;
0902 };
0903
0904 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0905 fsl,pins = <
0906 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0907 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0908 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0909 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0910 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0911 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0912 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0913 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0914 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0915 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0916 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0917 >;
0918 };
0919
0920 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0921 fsl,pins = <
0922 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0923 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0924 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0925 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0926 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0927 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0928 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0929 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0930 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0931 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0932 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0933 >;
0934 };
0935
0936 pinctrl_wdog: wdoggrp {
0937 fsl,pins = <
0938 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0939 >;
0940 };
0941 };
