0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 * Copyright 2019-2020 Variscite Ltd.
0005 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
0006 */
0007
0008 #include "imx8mn.dtsi"
0009
0010 / {
0011 model = "Variscite VAR-SOM-MX8MN module";
0012 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
0013
0014 chosen {
0015 stdout-path = &uart4;
0016 };
0017
0018 memory@40000000 {
0019 device_type = "memory";
0020 reg = <0x0 0x40000000 0 0x40000000>;
0021 };
0022
0023 reg_eth_phy: regulator-eth-phy {
0024 compatible = "regulator-fixed";
0025 pinctrl-names = "default";
0026 pinctrl-0 = <&pinctrl_reg_eth_phy>;
0027 regulator-name = "eth_phy_pwr";
0028 regulator-min-microvolt = <3300000>;
0029 regulator-max-microvolt = <3300000>;
0030 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
0031 enable-active-high;
0032 };
0033 };
0034
0035 &A53_0 {
0036 cpu-supply = <&buck2_reg>;
0037 };
0038
0039 &A53_1 {
0040 cpu-supply = <&buck2_reg>;
0041 };
0042
0043 &A53_2 {
0044 cpu-supply = <&buck2_reg>;
0045 };
0046
0047 &A53_3 {
0048 cpu-supply = <&buck2_reg>;
0049 };
0050
0051 &ecspi1 {
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_ecspi1>;
0054 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
0055 <&gpio1 0 GPIO_ACTIVE_LOW>;
0056 /delete-property/ dmas;
0057 /delete-property/ dma-names;
0058 status = "okay";
0059
0060 /* Resistive touch controller */
0061 touchscreen@0 {
0062 reg = <0>;
0063 compatible = "ti,ads7846";
0064 pinctrl-names = "default";
0065 pinctrl-0 = <&pinctrl_restouch>;
0066 interrupt-parent = <&gpio1>;
0067 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
0068
0069 spi-max-frequency = <1500000>;
0070 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
0071
0072 ti,x-min = /bits/ 16 <125>;
0073 touchscreen-size-x = <4008>;
0074 ti,y-min = /bits/ 16 <282>;
0075 touchscreen-size-y = <3864>;
0076 ti,x-plate-ohms = /bits/ 16 <180>;
0077 touchscreen-max-pressure = <255>;
0078 touchscreen-average-samples = <10>;
0079 ti,debounce-tol = /bits/ 16 <3>;
0080 ti,debounce-rep = /bits/ 16 <1>;
0081 ti,settle-delay-usec = /bits/ 16 <150>;
0082 ti,keep-vref-on;
0083 wakeup-source;
0084 };
0085 };
0086
0087 &fec1 {
0088 pinctrl-names = "default", "sleep";
0089 pinctrl-0 = <&pinctrl_fec1>;
0090 pinctrl-1 = <&pinctrl_fec1_sleep>;
0091 phy-mode = "rgmii";
0092 phy-handle = <ðphy>;
0093 phy-supply = <®_eth_phy>;
0094 fsl,magic-packet;
0095 status = "okay";
0096
0097 mdio {
0098 #address-cells = <1>;
0099 #size-cells = <0>;
0100
0101 ethphy: ethernet-phy@4 {
0102 compatible = "ethernet-phy-ieee802.3-c22";
0103 reg = <4>;
0104 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0105 reset-assert-us = <10000>;
0106 };
0107 };
0108 };
0109
0110 &i2c1 {
0111 clock-frequency = <400000>;
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&pinctrl_i2c1>;
0114 status = "okay";
0115
0116 pmic@4b {
0117 compatible = "rohm,bd71847";
0118 reg = <0x4b>;
0119 pinctrl-names = "default";
0120 pinctrl-0 = <&pinctrl_pmic>;
0121 interrupt-parent = <&gpio2>;
0122 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0123 rohm,reset-snvs-powered;
0124
0125 regulators {
0126 buck1_reg: BUCK1 {
0127 regulator-name = "buck1";
0128 regulator-min-microvolt = <700000>;
0129 regulator-max-microvolt = <1300000>;
0130 regulator-boot-on;
0131 regulator-always-on;
0132 regulator-ramp-delay = <1250>;
0133 };
0134
0135 buck2_reg: BUCK2 {
0136 regulator-name = "buck2";
0137 regulator-min-microvolt = <700000>;
0138 regulator-max-microvolt = <1300000>;
0139 regulator-boot-on;
0140 regulator-always-on;
0141 regulator-ramp-delay = <1250>;
0142 rohm,dvs-run-voltage = <1000000>;
0143 rohm,dvs-idle-voltage = <900000>;
0144 };
0145
0146 buck3_reg: BUCK3 {
0147 regulator-name = "buck3";
0148 regulator-min-microvolt = <700000>;
0149 regulator-max-microvolt = <1350000>;
0150 regulator-boot-on;
0151 regulator-always-on;
0152 };
0153
0154 buck4_reg: BUCK4 {
0155 regulator-name = "buck4";
0156 regulator-min-microvolt = <2600000>;
0157 regulator-max-microvolt = <3300000>;
0158 regulator-boot-on;
0159 regulator-always-on;
0160 };
0161
0162 buck5_reg: BUCK5 {
0163 regulator-name = "buck5";
0164 regulator-min-microvolt = <1605000>;
0165 regulator-max-microvolt = <1995000>;
0166 regulator-boot-on;
0167 regulator-always-on;
0168 };
0169
0170 buck6_reg: BUCK6 {
0171 regulator-name = "buck6";
0172 regulator-min-microvolt = <800000>;
0173 regulator-max-microvolt = <1400000>;
0174 regulator-boot-on;
0175 regulator-always-on;
0176 };
0177
0178 ldo1_reg: LDO1 {
0179 regulator-name = "ldo1";
0180 regulator-min-microvolt = <1600000>;
0181 regulator-max-microvolt = <1900000>;
0182 regulator-boot-on;
0183 regulator-always-on;
0184 };
0185
0186 ldo2_reg: LDO2 {
0187 regulator-name = "ldo2";
0188 regulator-min-microvolt = <800000>;
0189 regulator-max-microvolt = <900000>;
0190 regulator-boot-on;
0191 regulator-always-on;
0192 };
0193
0194 ldo3_reg: LDO3 {
0195 regulator-name = "ldo3";
0196 regulator-min-microvolt = <1800000>;
0197 regulator-max-microvolt = <3300000>;
0198 regulator-boot-on;
0199 regulator-always-on;
0200 };
0201
0202 ldo4_reg: LDO4 {
0203 regulator-name = "ldo4";
0204 regulator-min-microvolt = <900000>;
0205 regulator-max-microvolt = <1800000>;
0206 regulator-always-on;
0207 };
0208
0209 ldo5_reg: LDO5 {
0210 regulator-compatible = "ldo5";
0211 regulator-min-microvolt = <1800000>;
0212 regulator-max-microvolt = <1800000>;
0213 regulator-always-on;
0214 };
0215
0216 ldo6_reg: LDO6 {
0217 regulator-name = "ldo6";
0218 regulator-min-microvolt = <900000>;
0219 regulator-max-microvolt = <1800000>;
0220 regulator-boot-on;
0221 regulator-always-on;
0222 };
0223 };
0224 };
0225 };
0226
0227 &i2c3 {
0228 clock-frequency = <400000>;
0229 pinctrl-names = "default";
0230 pinctrl-0 = <&pinctrl_i2c3>;
0231 status = "okay";
0232
0233 /* TODO: configure audio, as of now just put a placeholder */
0234 wm8904: codec@1a {
0235 compatible = "wlf,wm8904";
0236 reg = <0x1a>;
0237 status = "disabled";
0238 };
0239 };
0240
0241 &snvs_pwrkey {
0242 status = "okay";
0243 };
0244
0245 /* Bluetooth */
0246 &uart2 {
0247 pinctrl-names = "default";
0248 pinctrl-0 = <&pinctrl_uart2>;
0249 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
0250 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
0251 uart-has-rtscts;
0252 status = "okay";
0253 };
0254
0255 /* Console */
0256 &uart4 {
0257 pinctrl-names = "default";
0258 pinctrl-0 = <&pinctrl_uart4>;
0259 status = "okay";
0260 };
0261
0262 &usbotg1 {
0263 dr_mode = "otg";
0264 usb-role-switch;
0265 status = "okay";
0266 };
0267
0268 /* WIFI */
0269 &usdhc1 {
0270 #address-cells = <1>;
0271 #size-cells = <0>;
0272 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0273 pinctrl-0 = <&pinctrl_usdhc1>;
0274 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0275 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0276 bus-width = <4>;
0277 non-removable;
0278 keep-power-in-suspend;
0279 status = "okay";
0280
0281 brcmf: bcrmf@1 {
0282 reg = <1>;
0283 compatible = "brcm,bcm4329-fmac";
0284 };
0285 };
0286
0287 /* SD */
0288 &usdhc2 {
0289 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
0290 assigned-clock-rates = <200000000>;
0291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0292 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0293 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0294 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0295 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
0296 bus-width = <4>;
0297 vmmc-supply = <®_usdhc2_vmmc>;
0298 status = "okay";
0299 };
0300
0301 /* eMMC */
0302 &usdhc3 {
0303 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
0304 assigned-clock-rates = <400000000>;
0305 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0306 pinctrl-0 = <&pinctrl_usdhc3>;
0307 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0308 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0309 bus-width = <8>;
0310 non-removable;
0311 status = "okay";
0312 };
0313
0314 &wdog1 {
0315 pinctrl-names = "default";
0316 pinctrl-0 = <&pinctrl_wdog>;
0317 fsl,ext-reset-output;
0318 status = "okay";
0319 };
0320
0321 &iomuxc {
0322 pinctrl_ecspi1: ecspi1grp {
0323 fsl,pins = <
0324 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
0325 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
0326 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
0327 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
0328 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
0329 >;
0330 };
0331
0332 pinctrl_fec1: fec1grp {
0333 fsl,pins = <
0334 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0335 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0336 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0337 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0338 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0339 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0340 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0341 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0342 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0343 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0344 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0345 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0346 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0347 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0348 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0349 >;
0350 };
0351
0352 pinctrl_fec1_sleep: fec1sleepgrp {
0353 fsl,pins = <
0354 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
0355 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
0356 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
0357 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
0358 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
0359 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
0360 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
0361 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
0362 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
0363 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
0364 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
0365 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
0366 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
0367 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
0368 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
0369 >;
0370 };
0371
0372 pinctrl_i2c1: i2c1grp {
0373 fsl,pins = <
0374 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0375 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0376 >;
0377 };
0378
0379 pinctrl_i2c3: i2c3grp {
0380 fsl,pins = <
0381 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0382 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0383 >;
0384 };
0385
0386 pinctrl_pmic: pmicirqgrp {
0387 fsl,pins = <
0388 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
0389 >;
0390 };
0391
0392 pinctrl_reg_eth_phy: regethphygrp {
0393 fsl,pins = <
0394 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
0395 >;
0396 };
0397
0398 pinctrl_restouch: restouchgrp {
0399 fsl,pins = <
0400 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
0401 >;
0402 };
0403
0404 pinctrl_uart2: uart2grp {
0405 fsl,pins = <
0406 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
0407 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
0408 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
0409 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
0410 >;
0411 };
0412
0413 pinctrl_uart4: uart4grp {
0414 fsl,pins = <
0415 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
0416 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
0417 >;
0418 };
0419
0420 pinctrl_usdhc1: usdhc1grp {
0421 fsl,pins = <
0422 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
0423 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
0424 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
0425 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
0426 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
0427 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
0428 >;
0429 };
0430
0431 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0432 fsl,pins = <
0433 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
0434 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
0435 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
0436 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
0437 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
0438 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
0439 >;
0440 };
0441
0442 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0443 fsl,pins = <
0444 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
0445 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
0446 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
0447 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
0448 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
0449 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
0450 >;
0451 };
0452
0453 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0454 fsl,pins = <
0455 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
0456 >;
0457 };
0458
0459 pinctrl_usdhc2: usdhc2grp {
0460 fsl,pins = <
0461 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0462 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0463 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0464 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0465 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0466 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0467 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0468 >;
0469 };
0470
0471 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0472 fsl,pins = <
0473 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0474 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0475 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0476 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0477 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0478 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0479 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0480 >;
0481 };
0482
0483 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0484 fsl,pins = <
0485 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0486 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0487 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0488 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0489 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0490 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0491 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0492 >;
0493 };
0494
0495 pinctrl_usdhc3: usdhc3grp {
0496 fsl,pins = <
0497 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0498 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0499 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0500 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0501 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0502 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0503 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0504 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0505 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0506 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0507 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0508 >;
0509 };
0510
0511 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0512 fsl,pins = <
0513 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0514 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0515 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0516 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0517 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0518 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0519 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0520 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0521 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0522 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0523 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0524 >;
0525 };
0526
0527 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0528 fsl,pins = <
0529 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0530 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0531 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0532 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0533 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0534 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0535 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0536 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0537 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0538 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0539 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0540 >;
0541 };
0542
0543 pinctrl_wdog: wdoggrp {
0544 fsl,pins = <
0545 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
0546 >;
0547 };
0548 };
