0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/linux-event-codes.h>
0010 #include <dt-bindings/leds/common.h>
0011 #include <dt-bindings/phy/phy-imx8-pcie.h>
0012
0013 #include "imx8mm.dtsi"
0014
0015 / {
0016 model = "Gateworks Venice GW7903 i.MX8MM board";
0017 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
0018
0019 aliases {
0020 ethernet0 = &fec1;
0021 usb0 = &usbotg1;
0022 };
0023
0024 chosen {
0025 stdout-path = &uart2;
0026 };
0027
0028 memory@40000000 {
0029 device_type = "memory";
0030 reg = <0x0 0x40000000 0 0x80000000>;
0031 };
0032
0033 gpio-keys {
0034 compatible = "gpio-keys";
0035
0036 key-user-pb {
0037 label = "user_pb";
0038 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0039 linux,code = <BTN_0>;
0040 };
0041
0042 key-user-pb1x {
0043 label = "user_pb1x";
0044 linux,code = <BTN_1>;
0045 interrupt-parent = <&gsc>;
0046 interrupts = <0>;
0047 };
0048
0049 key-erased {
0050 label = "key_erased";
0051 linux,code = <BTN_2>;
0052 interrupt-parent = <&gsc>;
0053 interrupts = <1>;
0054 };
0055
0056 key-eeprom-wp {
0057 label = "eeprom_wp";
0058 linux,code = <BTN_3>;
0059 interrupt-parent = <&gsc>;
0060 interrupts = <2>;
0061 };
0062
0063 switch-hold {
0064 label = "switch_hold";
0065 linux,code = <BTN_5>;
0066 interrupt-parent = <&gsc>;
0067 interrupts = <7>;
0068 };
0069 };
0070
0071 led-controller {
0072 compatible = "gpio-leds";
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_gpio_leds>;
0075
0076 led-0 {
0077 function = LED_FUNCTION_STATUS;
0078 color = <LED_COLOR_ID_RED>;
0079 label = "led01_red";
0080 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0081 default-state = "off";
0082 };
0083
0084 led-1 {
0085 function = LED_FUNCTION_STATUS;
0086 color = <LED_COLOR_ID_GREEN>;
0087 label = "led01_grn";
0088 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
0089 default-state = "off";
0090 };
0091
0092 led-2 {
0093 function = LED_FUNCTION_STATUS;
0094 color = <LED_COLOR_ID_RED>;
0095 label = "led02_red";
0096 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
0097 default-state = "off";
0098 };
0099
0100 led-3 {
0101 function = LED_FUNCTION_STATUS;
0102 color = <LED_COLOR_ID_GREEN>;
0103 label = "led02_grn";
0104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
0105 default-state = "off";
0106 };
0107
0108 led-4 {
0109 function = LED_FUNCTION_STATUS;
0110 color = <LED_COLOR_ID_RED>;
0111 label = "led03_red";
0112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
0113 default-state = "off";
0114 };
0115
0116 led-5 {
0117 function = LED_FUNCTION_STATUS;
0118 color = <LED_COLOR_ID_GREEN>;
0119 label = "led03_grn";
0120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
0121 default-state = "off";
0122 };
0123
0124 led-6 {
0125 function = LED_FUNCTION_STATUS;
0126 color = <LED_COLOR_ID_RED>;
0127 label = "led04_red";
0128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
0129 default-state = "off";
0130 };
0131
0132 led-7 {
0133 function = LED_FUNCTION_STATUS;
0134 color = <LED_COLOR_ID_GREEN>;
0135 label = "led04_grn";
0136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0137 default-state = "off";
0138 };
0139
0140 led-8 {
0141 function = LED_FUNCTION_STATUS;
0142 color = <LED_COLOR_ID_RED>;
0143 label = "led05_red";
0144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
0145 default-state = "off";
0146 };
0147
0148 led-9 {
0149 function = LED_FUNCTION_STATUS;
0150 color = <LED_COLOR_ID_GREEN>;
0151 label = "led05_grn";
0152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
0153 default-state = "off";
0154 };
0155
0156 led-a {
0157 function = LED_FUNCTION_STATUS;
0158 color = <LED_COLOR_ID_RED>;
0159 label = "led06_red";
0160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0161 default-state = "off";
0162 };
0163
0164 led-b {
0165 function = LED_FUNCTION_STATUS;
0166 color = <LED_COLOR_ID_GREEN>;
0167 label = "led06_grn";
0168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0169 default-state = "off";
0170 };
0171 };
0172
0173 pcie0_refclk: pcie0-refclk {
0174 compatible = "fixed-clock";
0175 #clock-cells = <0>;
0176 clock-frequency = <100000000>;
0177 };
0178
0179 reg_3p3v: regulator-3p3v {
0180 compatible = "regulator-fixed";
0181 regulator-name = "3P3V";
0182 regulator-min-microvolt = <3300000>;
0183 regulator-max-microvolt = <3300000>;
0184 regulator-always-on;
0185 };
0186 };
0187
0188 &A53_0 {
0189 cpu-supply = <&buck2>;
0190 };
0191
0192 &A53_1 {
0193 cpu-supply = <&buck2>;
0194 };
0195
0196 &A53_2 {
0197 cpu-supply = <&buck2>;
0198 };
0199
0200 &A53_3 {
0201 cpu-supply = <&buck2>;
0202 };
0203
0204 &ddrc {
0205 operating-points-v2 = <&ddrc_opp_table>;
0206
0207 ddrc_opp_table: opp-table {
0208 compatible = "operating-points-v2";
0209
0210 opp-25M {
0211 opp-hz = /bits/ 64 <25000000>;
0212 };
0213
0214 opp-100M {
0215 opp-hz = /bits/ 64 <100000000>;
0216 };
0217
0218 opp-750M {
0219 opp-hz = /bits/ 64 <750000000>;
0220 };
0221 };
0222 };
0223
0224 &fec1 {
0225 pinctrl-names = "default";
0226 pinctrl-0 = <&pinctrl_fec1>;
0227 phy-mode = "rgmii-id";
0228 phy-handle = <ðphy0>;
0229 local-mac-address = [00 00 00 00 00 00];
0230 status = "okay";
0231
0232 mdio {
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235
0236 ethphy0: ethernet-phy@0 {
0237 compatible = "ethernet-phy-ieee802.3-c22";
0238 reg = <0>;
0239 rx-internal-delay-ps = <2000>;
0240 tx-internal-delay-ps = <2500>;
0241 };
0242 };
0243 };
0244
0245 &gpio1 {
0246 gpio-line-names = "", "", "", "", "", "", "", "",
0247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
0248 "", "", "", "", "", "", "", "",
0249 "", "", "", "", "", "", "", "";
0250 };
0251
0252 &gpio2 {
0253 gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
0254 "dig1_out#", "dig1_in", "", "", "", "", "", "",
0255 "", "", "", "", "", "", "", "",
0256 "", "", "", "", "", "", "", "";
0257 };
0258
0259 &gpio5 {
0260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
0261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
0262 "", "", "", "", "", "", "", "",
0263 "", "", "", "", "", "", "", "";
0264 };
0265
0266 &i2c1 {
0267 clock-frequency = <100000>;
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&pinctrl_i2c1>;
0270 status = "okay";
0271
0272 gsc: gsc@20 {
0273 compatible = "gw,gsc";
0274 reg = <0x20>;
0275 pinctrl-0 = <&pinctrl_gsc>;
0276 interrupt-parent = <&gpio4>;
0277 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
0278 interrupt-controller;
0279 #interrupt-cells = <1>;
0280
0281 adc {
0282 compatible = "gw,gsc-adc";
0283 #address-cells = <1>;
0284 #size-cells = <0>;
0285
0286 channel@6 {
0287 gw,mode = <0>;
0288 reg = <0x06>;
0289 label = "temp";
0290 };
0291
0292 channel@8 {
0293 gw,mode = <1>;
0294 reg = <0x08>;
0295 label = "vdd_bat";
0296 };
0297
0298 channel@82 {
0299 gw,mode = <2>;
0300 reg = <0x82>;
0301 label = "vin";
0302 gw,voltage-divider-ohms = <22100 1000>;
0303 gw,voltage-offset-microvolt = <700000>;
0304 };
0305
0306 channel@84 {
0307 gw,mode = <2>;
0308 reg = <0x84>;
0309 label = "vdd_5p0";
0310 gw,voltage-divider-ohms = <10000 10000>;
0311 };
0312
0313 channel@86 {
0314 gw,mode = <2>;
0315 reg = <0x86>;
0316 label = "vdd_3p3";
0317 gw,voltage-divider-ohms = <10000 10000>;
0318 };
0319
0320 channel@88 {
0321 gw,mode = <2>;
0322 reg = <0x88>;
0323 label = "vdd_0p9";
0324 };
0325
0326 channel@8c {
0327 gw,mode = <2>;
0328 reg = <0x8c>;
0329 label = "vdd_soc";
0330 };
0331
0332 channel@8e {
0333 gw,mode = <2>;
0334 reg = <0x8e>;
0335 label = "vdd_arm";
0336 };
0337
0338 channel@90 {
0339 gw,mode = <2>;
0340 reg = <0x90>;
0341 label = "vdd_1p8";
0342 };
0343
0344 channel@92 {
0345 gw,mode = <2>;
0346 reg = <0x92>;
0347 label = "vdd_dram";
0348 };
0349
0350 channel@a2 {
0351 gw,mode = <2>;
0352 reg = <0xa2>;
0353 label = "vdd_gsc";
0354 gw,voltage-divider-ohms = <10000 10000>;
0355 };
0356 };
0357 };
0358
0359 gpio: gpio@23 {
0360 compatible = "nxp,pca9555";
0361 reg = <0x23>;
0362 gpio-controller;
0363 #gpio-cells = <2>;
0364 interrupt-parent = <&gsc>;
0365 interrupts = <4>;
0366 };
0367
0368 eeprom@50 {
0369 compatible = "atmel,24c02";
0370 reg = <0x50>;
0371 pagesize = <16>;
0372 };
0373
0374 eeprom@51 {
0375 compatible = "atmel,24c02";
0376 reg = <0x51>;
0377 pagesize = <16>;
0378 };
0379
0380 eeprom@52 {
0381 compatible = "atmel,24c02";
0382 reg = <0x52>;
0383 pagesize = <16>;
0384 };
0385
0386 eeprom@53 {
0387 compatible = "atmel,24c02";
0388 reg = <0x53>;
0389 pagesize = <16>;
0390 };
0391
0392 rtc@68 {
0393 compatible = "dallas,ds1672";
0394 reg = <0x68>;
0395 };
0396 };
0397
0398 &i2c2 {
0399 clock-frequency = <400000>;
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&pinctrl_i2c2>;
0402 status = "okay";
0403
0404 pmic@4b {
0405 compatible = "rohm,bd71847";
0406 reg = <0x4b>;
0407 pinctrl-names = "default";
0408 pinctrl-0 = <&pinctrl_pmic>;
0409 interrupt-parent = <&gpio3>;
0410 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0411 rohm,reset-snvs-powered;
0412 #clock-cells = <0>;
0413 clocks = <&osc_32k 0>;
0414 clock-output-names = "clk-32k-out";
0415
0416 regulators {
0417 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
0418 BUCK1 {
0419 regulator-name = "buck1";
0420 regulator-min-microvolt = <700000>;
0421 regulator-max-microvolt = <1300000>;
0422 regulator-boot-on;
0423 regulator-always-on;
0424 regulator-ramp-delay = <1250>;
0425 };
0426
0427 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
0428 buck2: BUCK2 {
0429 regulator-name = "buck2";
0430 regulator-min-microvolt = <700000>;
0431 regulator-max-microvolt = <1300000>;
0432 regulator-boot-on;
0433 regulator-always-on;
0434 regulator-ramp-delay = <1250>;
0435 rohm,dvs-run-voltage = <1000000>;
0436 rohm,dvs-idle-voltage = <900000>;
0437 };
0438
0439 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
0440 BUCK3 {
0441 regulator-name = "buck3";
0442 regulator-min-microvolt = <700000>;
0443 regulator-max-microvolt = <1350000>;
0444 regulator-boot-on;
0445 regulator-always-on;
0446 };
0447
0448 /* vdd_3p3 */
0449 BUCK4 {
0450 regulator-name = "buck4";
0451 regulator-min-microvolt = <3000000>;
0452 regulator-max-microvolt = <3300000>;
0453 regulator-boot-on;
0454 regulator-always-on;
0455 };
0456
0457 /* vdd_1p8 */
0458 BUCK5 {
0459 regulator-name = "buck5";
0460 regulator-min-microvolt = <1605000>;
0461 regulator-max-microvolt = <1995000>;
0462 regulator-boot-on;
0463 regulator-always-on;
0464 };
0465
0466 /* vdd_dram */
0467 BUCK6 {
0468 regulator-name = "buck6";
0469 regulator-min-microvolt = <800000>;
0470 regulator-max-microvolt = <1400000>;
0471 regulator-boot-on;
0472 regulator-always-on;
0473 };
0474
0475 /* nvcc_snvs_1p8 */
0476 LDO1 {
0477 regulator-name = "ldo1";
0478 regulator-min-microvolt = <1600000>;
0479 regulator-max-microvolt = <1900000>;
0480 regulator-boot-on;
0481 regulator-always-on;
0482 };
0483
0484 /* vdd_snvs_0p8 */
0485 LDO2 {
0486 regulator-name = "ldo2";
0487 regulator-min-microvolt = <800000>;
0488 regulator-max-microvolt = <900000>;
0489 regulator-boot-on;
0490 regulator-always-on;
0491 };
0492
0493 /* vdda_1p8 */
0494 LDO3 {
0495 regulator-name = "ldo3";
0496 regulator-min-microvolt = <1800000>;
0497 regulator-max-microvolt = <3300000>;
0498 regulator-boot-on;
0499 regulator-always-on;
0500 };
0501
0502 LDO4 {
0503 regulator-name = "ldo4";
0504 regulator-min-microvolt = <900000>;
0505 regulator-max-microvolt = <1800000>;
0506 regulator-boot-on;
0507 regulator-always-on;
0508 };
0509
0510 LDO6 {
0511 regulator-name = "ldo6";
0512 regulator-min-microvolt = <900000>;
0513 regulator-max-microvolt = <1800000>;
0514 regulator-boot-on;
0515 regulator-always-on;
0516 };
0517 };
0518 };
0519 };
0520
0521 &i2c3 {
0522 clock-frequency = <400000>;
0523 pinctrl-names = "default";
0524 pinctrl-0 = <&pinctrl_i2c3>;
0525 status = "okay";
0526
0527 accelerometer@19 {
0528 pinctrl-names = "default";
0529 pinctrl-0 = <&pinctrl_accel>;
0530 compatible = "st,lis2de12";
0531 reg = <0x19>;
0532 st,drdy-int-pin = <1>;
0533 interrupt-parent = <&gpio1>;
0534 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
0535 interrupt-names = "INT1";
0536 };
0537 };
0538
0539 &pcie_phy {
0540 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0541 fsl,clkreq-unsupported;
0542 clocks = <&pcie0_refclk>;
0543 clock-names = "ref";
0544 status = "okay";
0545 };
0546
0547 &pcie0 {
0548 pinctrl-names = "default";
0549 pinctrl-0 = <&pinctrl_pcie0>;
0550 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
0551 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
0552 <&pcie0_refclk>;
0553 clock-names = "pcie", "pcie_aux", "pcie_bus";
0554 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
0555 <&clk IMX8MM_CLK_PCIE1_CTRL>;
0556 assigned-clock-rates = <10000000>, <250000000>;
0557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
0558 <&clk IMX8MM_SYS_PLL2_250M>;
0559 status = "okay";
0560 };
0561
0562 &pgc_mipi {
0563 status = "disabled";
0564 };
0565
0566 /* off-board RS232/RS485/RS422 */
0567 &uart1 {
0568 pinctrl-names = "default";
0569 pinctrl-0 = <&pinctrl_uart1>;
0570 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
0571 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
0572 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
0573 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0574 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
0575 uart-has-rtscts;
0576 status = "okay";
0577 };
0578
0579 /* console */
0580 &uart2 {
0581 pinctrl-names = "default";
0582 pinctrl-0 = <&pinctrl_uart2>;
0583 status = "okay";
0584 };
0585
0586 &usbotg1 {
0587 dr_mode = "host";
0588 disable-over-current;
0589 status = "okay";
0590 };
0591
0592 /* microSD */
0593 &usdhc2 {
0594 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0595 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0596 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0597 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0598 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0599 bus-width = <4>;
0600 vmmc-supply = <®_3p3v>;
0601 status = "okay";
0602 };
0603
0604 /* eMMC */
0605 &usdhc3 {
0606 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0607 pinctrl-0 = <&pinctrl_usdhc3>;
0608 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0609 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0610 bus-width = <8>;
0611 non-removable;
0612 status = "okay";
0613 };
0614
0615 &wdog1 {
0616 pinctrl-names = "default";
0617 pinctrl-0 = <&pinctrl_wdog>;
0618 fsl,ext-reset-output;
0619 status = "okay";
0620 };
0621
0622 &iomuxc {
0623 pinctrl-names = "default";
0624 pinctrl-0 = <&pinctrl_hog>;
0625
0626 pinctrl_hog: hoggrp {
0627 fsl,pins = <
0628 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
0629 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
0630 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
0631 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
0632 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
0633 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
0634 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
0635 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
0636 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
0637 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
0638 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
0639 >;
0640 };
0641
0642 pinctrl_accel: accelgrp {
0643 fsl,pins = <
0644 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
0645 >;
0646 };
0647
0648 pinctrl_fec1: fec1grp {
0649 fsl,pins = <
0650 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0651 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0652 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0653 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0654 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0655 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0656 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0657 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0658 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0659 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0660 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0661 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0662 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0663 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0664 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
0665 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
0666 >;
0667 };
0668
0669 pinctrl_gsc: gscgrp {
0670 fsl,pins = <
0671 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
0672 >;
0673 };
0674
0675 pinctrl_i2c1: i2c1grp {
0676 fsl,pins = <
0677 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0678 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0679 >;
0680 };
0681
0682 pinctrl_i2c2: i2c2grp {
0683 fsl,pins = <
0684 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0685 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0686 >;
0687 };
0688
0689 pinctrl_i2c3: i2c3grp {
0690 fsl,pins = <
0691 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0692 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0693 >;
0694 };
0695
0696 pinctrl_gpio_leds: gpioledgrp {
0697 fsl,pins = <
0698 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
0699 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
0700 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
0701 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
0702 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0703 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
0704 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
0705 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
0706 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
0707 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
0708 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
0709 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
0710 >;
0711 };
0712
0713 pinctrl_pcie0: pciegrp {
0714 fsl,pins = <
0715 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
0716 >;
0717 };
0718
0719 pinctrl_pmic: pmicgrp {
0720 fsl,pins = <
0721 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
0722 >;
0723 };
0724
0725 pinctrl_uart1: uart1grp {
0726 fsl,pins = <
0727 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0728 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0729 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
0730 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
0731 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
0732 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
0733 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
0734 >;
0735 };
0736
0737 pinctrl_uart2: uart2grp {
0738 fsl,pins = <
0739 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0740 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0741 >;
0742 };
0743
0744 pinctrl_usdhc2: usdhc2grp {
0745 fsl,pins = <
0746 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0747 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0748 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0749 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0750 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0751 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0752 >;
0753 };
0754
0755 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0756 fsl,pins = <
0757 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0758 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0759 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0760 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0761 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0762 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0763 >;
0764 };
0765
0766 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0767 fsl,pins = <
0768 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0769 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0770 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0771 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0772 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0773 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0774 >;
0775 };
0776
0777 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
0778 fsl,pins = <
0779 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
0780 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0781 >;
0782 };
0783
0784 pinctrl_usdhc3: usdhc3grp {
0785 fsl,pins = <
0786 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
0787 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0788 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0789 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0790 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0791 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0792 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0793 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0794 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0795 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0796 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0797 >;
0798 };
0799
0800 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0801 fsl,pins = <
0802 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
0803 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0804 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0805 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0806 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0807 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0808 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0809 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0810 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0811 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0812 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0813 >;
0814 };
0815
0816 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0817 fsl,pins = <
0818 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
0819 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0820 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0821 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0822 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0823 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0824 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0825 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0826 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0827 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0828 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0829 >;
0830 };
0831
0832 pinctrl_wdog: wdoggrp {
0833 fsl,pins = <
0834 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0835 >;
0836 };
0837 };
